URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sim/] [bin/] [ordb1a3pe1500-or1ksim.cfg] - Blame information for rev 508

Go to most recent revision | Details | Compare with Previous | View Log


/* ordb1a3pe1500-or1ksim.cfg -- Simulator configuration script file for
   ordb1a3pe1500 ORPSoC board build.
 
   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
   Copyright (C) 2010, Embecosm Limited
 
   Contributor Jeremy Bennett 
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see . */
 
 
/* -------------------------------------------------------------------------- */
/* The Ork1sim has various parameters, that can be set in configuration files
   like this one. The user can specify a configuration file at startu[ with
   the -f  option.
 
   The user guide (see the 'doc' directory) gives full details on
   configuration files. This is a reference configuration, which may be used
   as a starting point for customization.
 
   A number of peripherals are mapped at standard addresses (above 0x80000000)
   in the Verilog RTL of ORPSoC standard sitribution. The same values should
   be used in Or1ksim section definitions to match the behavior of the Verilog
 
      0x90000000 UART
      0x91000000 GPIO
      0x92000000 Ethernet
 
   Not all verilog modules are modeled in or1ksim.                            */
/* -------------------------------------------------------------------------- */
 
 
/* Simulator section
 
   verbose               = 0|1
   debug                 = 0-9
   profile               = 0|1
   prof_file             = "" (default: "sim.profile")
   mprofile              = 0|1
   mprof_file            = "" (default: "sim.mprofile")
   history               = 0|1
   exe_log               = 0|1
   exe_log_type          = hardware|simple|software|default
   exe_log_start         =  (default: 0)
   exe_log_end           =  (default: never end)
   exe_log_marker        =  (default: no markers)
   exe_log_file          = "" (default: "executed.log")
   exe_bin_insn_log      = 0|1
   exe_bin_insn_log_file = "" (default: "exe-insn.bin")
   clkcycle              = [ps|ns|us|ms]
*/
section sim
  clkcycle = 50ns
end
 
/* CPU section
 
   ver         =  (default: 0)
   cfg         =  (default: 0)
   rev         =  (default: 0)
   upr         =  (see user manual for default settings)
   cfgr        =  (default: 0x00000020)
   sr          =  (default: 0x00008001)
   superscalar = 0|1
   hazards     = 0|1
   dependstats = 0|1
   sbuf_len    =  (default: 0)
   hardfloat   = 0|1
*/
section cpu
  ver = 0x12
  cfg = 0x00
  rev = 0x0001
end
 
 
/* Memory section
 
   type        = unknown|random|unknown|pattern
   random_seed =  (default: -1)
   pattern     =  (default: 0)
   baseaddr    =  (default: 0)
   size        =  (default: 1024)
   name        = "" (default: "anonymous memory block")
   ce          =  (default: -1)
   mc          =  (default: 0)
   delayr      =  (default: 1)
   delayw      =  (default: 1)
   log         = "" (default: NULL)
*/
section memory
  name        = "RAM"
  type        = unknown
  baseaddr    = 0x00000000
  size        = 0x02000000
  delayr      = 1
  delayw      = 1
end
 
 
/* Data MMU section
 
   enabled   = 0|1
   nsets     =  (default: 1)
   nways     =  (default: 1)
   pagesize  =  (default: 8192)
   entrysize =  (default: 1)
   ustates   =  (default: 1)
   hitdelay  =  (default: 1)
   missdelay =  (default: 1)
*/
section dmmu
  enabled   = 1
  nsets     = 64
  nways     = 1
  pagesize  = 8192
  hitdelay  = 0
  missdelay = 0
end
 
 
/* Instruction MMU section
 
   enabled   = 0|1
   nsets     =  (default: 1)
   nways     =  (default: 1)
   pagesize  =  (default: 8192)
   entrysize =  (default: 1)
   ustates   =  (default: 1)
   hitdelay  =  (default: 1)
   missdelay =  (default: 1)
*/
section immu
  enabled   = 1
  nsets     = 64
  nways     = 1
  pagesize  = 8192
  hitdelay  = 0
  missdelay = 0
end
 
 
/* Data cache section
 
   enabled         = 0|1
   nsets           =  (default: 1)
   nways           =  (default: 1)
   blocksize       =  (default: 16)
   ustates         =  (default: 2)
   load_hitdelay   =  (default: 2)
   load_missdelay  =  (default: 2)
   store_hitdelay  =  (default: 0)
   store_missdelay =  (default: 0)
*/
 
section dc
  enabled         = 1
  nsets           = 256
  nways           = 1
  blocksize       = 16
  load_hitdelay   = 0
  load_missdelay  = 0
  store_hitdelay  = 0
  store_missdelay = 0
end
 
 
/* Instruction cache section
 
   enabled    = 0|1
   nsets      =  (default: 1)
   nways      =  (default: 1)
   blocksize  =  (default: 16)
   ustates    =  (default: 2)
   hitdelay   =  (default: 1)
   missdelay  =  (default: 1)
*/
section ic
  enabled   = 1
  nsets     = 512
  nways     = 1
  blocksize = 16
  hitdelay  = 0
  missdelay = 0
end
 
 
/* Programmable interrupt controller section
 
  enabled      = 0|1
  edge_trigger = 0|1 (default: 1)
*/
 
section pic
  enabled = 1
end
 
 
/* Power management section
 
   enabled = 0|1
*/
 
section pm
  enabled = 0
end
 
/* Debug unit section
 
   enabled     = 0|1
   rsp_enabled = 0|1
   rsp_port    =  (default: 51000)
   vapi_id     =  (default: 0)
*/
section debug
  enabled = 0
end
 
 
/* UART section
 
   enabled  = 0|1
   baseaddr =  (default: 0)
   channel  = "value>" (default: "xterm:")
   irq      =  (default: 0)
   16550    = 0|1
   jitter   =  (default: 0)
   vapi_id  =  (default: 0)
*/
 
section uart
  enabled  = 1
  baseaddr = 0x90000000
  irq      = 2
  16550    = 1
end
 
/* Ethernet section
 
   enabled    = 0|1
   baseaddr   =  (default: 0)
   dma        =  (default: 0)
   irq        =  (default: 0)
   rtx_type   = 0|1
   rx_channel =  (default: 0)
   tx_channel =  (default: 0)
   rxfile     = "" (default: "eth_rx")
   txfile     = "" (default: "eth_rx")
   sockif     = "" (default: "or1ksim_eth")
   vapi_id    =  (default: 0)
*/
section ethernet
  enabled  = 1
  baseaddr = 0x92000000
  irq      = 4
  rtx_type = "tap"
  tap_dev = "tap0"
  dummy_crc = 1
end

Browse

Tools

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sim/] [bin/] [ordb1a3pe1500-or1ksim.cfg] - Blame information for rev 508

Line No.	Rev	Author	Line
1	475	julius	`/* ordb1a3pe1500-or1ksim.cfg -- Simulator configuration script file for`
2			`ordb1a3pe1500 ORPSoC board build.`
3
4			`Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org`
5			`Copyright (C) 2010, Embecosm Limited`
6
7			`Contributor Jeremy Bennett`
8
9			`This file is part of OpenRISC 1000 Architectural Simulator.`
10
11			`This program is free software; you can redistribute it and/or modify it`
12			`under the terms of the GNU General Public License as published by the Free`
13			`Software Foundation; either version 3 of the License, or (at your option)`
14			`any later version.`
15
16			`This program is distributed in the hope that it will be useful, but WITHOUT`
17			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
18			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
19			`more details.`
20
21			`You should have received a copy of the GNU General Public License along`
22			`with this program. If not, see . */`
23
24
25			`/* -------------------------------------------------------------------------- */`
26			`/* The Ork1sim has various parameters, that can be set in configuration files`
27			`like this one. The user can specify a configuration file at startu[ with`
28			`the -f option.`
29
30			`The user guide (see the 'doc' directory) gives full details on`
31			`configuration files. This is a reference configuration, which may be used`
32			`as a starting point for customization.`
33
34			`A number of peripherals are mapped at standard addresses (above 0x80000000)`
35			`in the Verilog RTL of ORPSoC standard sitribution. The same values should`
36			`be used in Or1ksim section definitions to match the behavior of the Verilog`
37
38			`0x90000000 UART`
39			`0x91000000 GPIO`
40			`0x92000000 Ethernet`
41
42			`Not all verilog modules are modeled in or1ksim. */`
43			`/* -------------------------------------------------------------------------- */`
44
45
46			`/* Simulator section`
47
48			`verbose = 0\|1`
49			`debug = 0-9`
50			`profile = 0\|1`
51			`prof_file = "" (default: "sim.profile")`
52			`mprofile = 0\|1`
53			`mprof_file = "" (default: "sim.mprofile")`
54			`history = 0\|1`
55			`exe_log = 0\|1`
56			`exe_log_type = hardware\|simple\|software\|default`
57			`exe_log_start = (default: 0)`
58			`exe_log_end = (default: never end)`
59			`exe_log_marker = (default: no markers)`
60			`exe_log_file = "" (default: "executed.log")`
61			`exe_bin_insn_log = 0\|1`
62			`exe_bin_insn_log_file = "" (default: "exe-insn.bin")`
63			`clkcycle = [ps\|ns\|us\|ms]`
64			`*/`
65			`section sim`
66			`clkcycle = 50ns`
67			`end`
68
69			`/* CPU section`
70
71			`ver = (default: 0)`
72			`cfg = (default: 0)`
73			`rev = (default: 0)`
74			`upr = (see user manual for default settings)`
75			`cfgr = (default: 0x00000020)`
76			`sr = (default: 0x00008001)`
77			`superscalar = 0\|1`
78			`hazards = 0\|1`
79			`dependstats = 0\|1`
80			`sbuf_len = (default: 0)`
81			`hardfloat = 0\|1`
82			`*/`
83			`section cpu`
84			`ver = 0x12`
85			`cfg = 0x00`
86			`rev = 0x0001`
87			`end`
88
89
90			`/* Memory section`
91
92			`type = unknown\|random\|unknown\|pattern`
93			`random_seed = (default: -1)`
94			`pattern = (default: 0)`
95			`baseaddr = (default: 0)`
96			`size = (default: 1024)`
97			`name = "" (default: "anonymous memory block")`
98			`ce = (default: -1)`
99			`mc = (default: 0)`
100			`delayr = (default: 1)`
101			`delayw = (default: 1)`
102			`log = "" (default: NULL)`
103			`*/`
104			`section memory`
105			`name = "RAM"`
106			`type = unknown`
107			`baseaddr = 0x00000000`
108			`size = 0x02000000`
109			`delayr = 1`
110			`delayw = 1`
111			`end`
112
113
114			`/* Data MMU section`
115
116			`enabled = 0\|1`
117			`nsets = (default: 1)`
118			`nways = (default: 1)`
119			`pagesize = (default: 8192)`
120			`entrysize = (default: 1)`
121			`ustates = (default: 1)`
122			`hitdelay = (default: 1)`
123			`missdelay = (default: 1)`
124			`*/`
125			`section dmmu`
126			`enabled = 1`
127			`nsets = 64`
128			`nways = 1`
129			`pagesize = 8192`
130			`hitdelay = 0`
131			`missdelay = 0`
132			`end`
133
134
135			`/* Instruction MMU section`
136
137			`enabled = 0\|1`
138			`nsets = (default: 1)`
139			`nways = (default: 1)`
140			`pagesize = (default: 8192)`
141			`entrysize = (default: 1)`
142			`ustates = (default: 1)`
143			`hitdelay = (default: 1)`
144			`missdelay = (default: 1)`
145			`*/`
146			`section immu`
147			`enabled = 1`
148			`nsets = 64`
149			`nways = 1`
150			`pagesize = 8192`
151			`hitdelay = 0`
152			`missdelay = 0`
153			`end`
154
155
156			`/* Data cache section`
157
158			`enabled = 0\|1`
159			`nsets = (default: 1)`
160			`nways = (default: 1)`
161			`blocksize = (default: 16)`
162			`ustates = (default: 2)`
163			`load_hitdelay = (default: 2)`
164			`load_missdelay = (default: 2)`
165			`store_hitdelay = (default: 0)`
166			`store_missdelay = (default: 0)`
167			`*/`
168
169			`section dc`
170			`enabled = 1`
171			`nsets = 256`
172			`nways = 1`
173			`blocksize = 16`
174			`load_hitdelay = 0`
175			`load_missdelay = 0`
176			`store_hitdelay = 0`
177			`store_missdelay = 0`
178			`end`
179
180
181			`/* Instruction cache section`
182
183			`enabled = 0\|1`
184			`nsets = (default: 1)`
185			`nways = (default: 1)`
186			`blocksize = (default: 16)`
187			`ustates = (default: 2)`
188			`hitdelay = (default: 1)`
189			`missdelay = (default: 1)`
190			`*/`
191			`section ic`
192			`enabled = 1`
193			`nsets = 512`
194			`nways = 1`
195			`blocksize = 16`
196			`hitdelay = 0`
197			`missdelay = 0`
198			`end`
199
200
201			`/* Programmable interrupt controller section`
202
203			`enabled = 0\|1`
204			`edge_trigger = 0\|1 (default: 1)`
205			`*/`
206
207			`section pic`
208			`enabled = 1`
209			`end`
210
211
212			`/* Power management section`
213
214			`enabled = 0\|1`
215			`*/`
216
217			`section pm`
218			`enabled = 0`
219			`end`
220
221			`/* Debug unit section`
222
223			`enabled = 0\|1`
224			`rsp_enabled = 0\|1`
225			`rsp_port = (default: 51000)`
226			`vapi_id = (default: 0)`
227			`*/`
228			`section debug`
229			`enabled = 0`
230			`end`
231
232
233			`/* UART section`
234
235			`enabled = 0\|1`
236			`baseaddr = (default: 0)`
237			`channel = "value>" (default: "xterm:")`
238			`irq = (default: 0)`
239			`16550 = 0\|1`
240			`jitter = (default: 0)`
241			`vapi_id = (default: 0)`
242			`*/`
243
244			`section uart`
245			`enabled = 1`
246			`baseaddr = 0x90000000`
247			`irq = 2`
248			`16550 = 1`
249			`end`
250
251			`/* Ethernet section`
252
253			`enabled = 0\|1`
254			`baseaddr = (default: 0)`
255			`dma = (default: 0)`
256			`irq = (default: 0)`
257			`rtx_type = 0\|1`
258			`rx_channel = (default: 0)`
259			`tx_channel = (default: 0)`
260			`rxfile = "" (default: "eth_rx")`
261			`txfile = "" (default: "eth_rx")`
262			`sockif = "" (default: "or1ksim_eth")`
263			`vapi_id = (default: 0)`
264			`*/`
265			`section ethernet`
266			`enabled = 1`
267			`baseaddr = 0x92000000`
268			`irq = 4`
269			`rtx_type = "tap"`
270			`tap_dev = "tap0"`
271			`dummy_crc = 1`
272			`end`