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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sw/] [board/] [include/] [board.h] - Blame information for rev 438

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#ifndef _BOARD_H_
#define _BOARD_H_
 
//#define IN_CLK              50000000 // Hz
//#define IN_CLK              32000000 // Hz
//#define IN_CLK              30000000 // HZ
//#define IN_CLK              24000000 // HZ
#define IN_CLK                20000000 // HZ
//#define IN_CLK              18000000 // HZ
//#define IN_CLK              16000000 // HZ
 
//
// ROM bootloader
//
// Uncomment the appropriate bootloader define. This will effect the bootrom.S
// file, which is compiled and converted into Verilog for inclusion at 
// synthesis time. See bootloader/bootloader.S for details on each option.
 
#define BOOTROM_SPI_FLASH
//#define BOOTROM_GOTO_RESET
//#define BOOTROM_LOOP_AT_ZERO
//#define BOOTROM_LOOP_IN_ROM
 
//
// Defines for each core (memory map base, OR1200 interrupt line number, etc.)
//
#define SDRAM_BASE                 0x0
//#define MT48LC32M16A2 // 64MB SDRAM part
#define MT48LC16M16A2 // 32MB SDRAM part
//#define MT48LC4M16A2 // 8MB SDRAM part
 
#define FLASHROM_BASE       0xcf000000
#define FLASHROM_SIZE            0x100
 
#define GPIO_0_BASE         0x91000000
 
#define UART0_BASE          0x90000000
#define UART0_IRQ                    2
#define UART0_BAUD_RATE         115200
 
#define UART1_BASE          0x93000000
#define UART1_IRQ                    3
#define UART1_BAUD_RATE         115200
 
#define UART2_BASE          0x94000000
#define UART2_IRQ                    5
#define UART2_BAUD_RATE         115200
 
#define SPI0_BASE           0xb0000000
#define SPI0_IRQ                     6
 
#define SPI1_BASE           0xb1000000
#define SPI1_IRQ                     7
 
#define SPI2_BASE           0xb2000000
#define SPI2_IRQ                     8
 
#define I2C_0_BASE          0xa0000000
#define I2C_0_IRQ                   10
 
#define I2C_1_BASE          0xa1000000
#define I2C_1_IRQ                   11
 
#define I2C_2_BASE          0xa2000000
#define I2C_2_IRQ                   12
 
#define I2C_3_BASE          0xa3000000
#define I2C_3_IRQ                   13
 
#define USB0_BASE            0x9c000000
#define USB0_HOST_IRQ                20
#define USB0_SLAVE_IRQ               21
 
#define USB1_BASE            0x9d000000
#define USB1_HOST_IRQ                22
#define USB1_SLAVE_IRQ               23
 
#define ETH0_BASE            0x92000000
#define ETH0_IRQ                      4
 
#define ETH_MACADDR0               0x00
#define ETH_MACADDR1               0x12
#define ETH_MACADDR2               0x34
#define ETH_MACADDR3               0x56
#define ETH_MACADDR4               0x78
#define ETH_MACADDR5               0x9a
 
 
//
// OR1200 tick timer period define
//
#define TICKS_PER_SEC   100
 
#endif

Line No.	Rev	Author	Line
1	408	julius	`#ifndef _BOARD_H_`
2			`#define _BOARD_H_`
3
4			`//#define IN_CLK 50000000 // Hz`
5			`//#define IN_CLK 32000000 // Hz`
6			`//#define IN_CLK 30000000 // HZ`
7			`//#define IN_CLK 24000000 // HZ`
8			`#define IN_CLK 20000000 // HZ`
9			`//#define IN_CLK 18000000 // HZ`
10			`//#define IN_CLK 16000000 // HZ`
11
12			`//`
13			`// ROM bootloader`
14			`//`
15			`// Uncomment the appropriate bootloader define. This will effect the bootrom.S`
16			`// file, which is compiled and converted into Verilog for inclusion at`
17			`// synthesis time. See bootloader/bootloader.S for details on each option.`
18
19			`#define BOOTROM_SPI_FLASH`
20			`//#define BOOTROM_GOTO_RESET`
21			`//#define BOOTROM_LOOP_AT_ZERO`
22			`//#define BOOTROM_LOOP_IN_ROM`
23
24			`//`
25			`// Defines for each core (memory map base, OR1200 interrupt line number, etc.)`
26			`//`
27			`#define SDRAM_BASE 0x0`
28			`//#define MT48LC32M16A2 // 64MB SDRAM part`
29			`#define MT48LC16M16A2 // 32MB SDRAM part`
30			`//#define MT48LC4M16A2 // 8MB SDRAM part`
31
32			`#define FLASHROM_BASE 0xcf000000`
33			`#define FLASHROM_SIZE 0x100`
34
35			`#define GPIO_0_BASE 0x91000000`
36
37			`#define UART0_BASE 0x90000000`
38			`#define UART0_IRQ 2`
39			`#define UART0_BAUD_RATE 115200`
40
41			`#define UART1_BASE 0x93000000`
42			`#define UART1_IRQ 3`
43			`#define UART1_BAUD_RATE 115200`
44
45			`#define UART2_BASE 0x94000000`
46			`#define UART2_IRQ 5`
47			`#define UART2_BAUD_RATE 115200`
48
49			`#define SPI0_BASE 0xb0000000`
50			`#define SPI0_IRQ 6`
51
52			`#define SPI1_BASE 0xb1000000`
53			`#define SPI1_IRQ 7`
54
55			`#define SPI2_BASE 0xb2000000`
56			`#define SPI2_IRQ 8`
57
58			`#define I2C_0_BASE 0xa0000000`
59			`#define I2C_0_IRQ 10`
60
61			`#define I2C_1_BASE 0xa1000000`
62			`#define I2C_1_IRQ 11`
63
64			`#define I2C_2_BASE 0xa2000000`
65			`#define I2C_2_IRQ 12`
66
67			`#define I2C_3_BASE 0xa3000000`
68			`#define I2C_3_IRQ 13`
69
70			`#define USB0_BASE 0x9c000000`
71			`#define USB0_HOST_IRQ 20`
72			`#define USB0_SLAVE_IRQ 21`
73
74			`#define USB1_BASE 0x9d000000`
75			`#define USB1_HOST_IRQ 22`
76			`#define USB1_SLAVE_IRQ 23`
77
78			`#define ETH0_BASE 0x92000000`
79			`#define ETH0_IRQ 4`
80
81			`#define ETH_MACADDR0 0x00`
82			`#define ETH_MACADDR1 0x12`
83			`#define ETH_MACADDR2 0x34`
84			`#define ETH_MACADDR3 0x56`
85			`#define ETH_MACADDR4 0x78`
86			`#define ETH_MACADDR5 0x9a`
87
88
89			`//`
90			`// OR1200 tick timer period define`
91			`//`
92			`#define TICKS_PER_SEC 100`
93
94			`#endif`

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sw/] [board/] [include/] [board.h] - Blame information for rev 438