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408 |
julius |
/*
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*
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* USB usbhostslave core slave register defines
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*
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* Julius Baxter, julius@opencores.org
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*
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*/
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#ifndef _USBHOSTSLAVE_HOST_H_
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#define _USBHOSTSLAVE_HOST_H_
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extern const int USBHOSTSLAVE_HOST_CORE_ADR[2];
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char usb_host_init (int core);
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// ---
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// --- Host/slave constants
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// ---
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enum hostSlaveCommonRegs {
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HOST_SLAVE_MODE_CTRL = 0,
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HOST_SLAVE_VERSION_NUM
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};
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// ---
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// --- Slave constants
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// ---
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enum endPointConstants {
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NUM_OF_ENDPOINTS = 4,
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NUM_OF_REGISTERS_PER_ENDPOINT = 4,
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BASE_INDEX_FOR_ENDPOINT_REGS = 0,
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ENDPOINT_CONTROL_REG = 0,
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ENDPOINT_STATUS_REG = 1,
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ENDPOINT_TRANSTYPE_STATUS_REG = 2,
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NAK_TRANSTYPE_STATUS_REG = 3 };
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enum SCRegIndices {
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LAST_ENDP_REG = BASE_INDEX_FOR_ENDPOINT_REGS + (NUM_OF_REGISTERS_PER_ENDPOINT * NUM_OF_ENDPOINTS) - 1,
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SC_CONTROL_REG,
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SC_LINE_STATUS_REG,
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SC_INTERRUPT_STATUS_REG,
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SC_INTERRUPT_MASK_REG,
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SC_ADDRESS,
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SC_FRAME_NUM_MSP,
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SC_FRAME_NUM_LSP,
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SCREG_BUFFER_LEN };
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enum SCRXStatusRegIndices {
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SC_CRC_ERROR_BIT = 0,
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SC_BIT_STUFF_ERROR_BIT,
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SC_RX_OVERFLOW_BIT,
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SC_RX_TIME_OUT_BIT,
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SC_NAK_SENT_BIT,
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SC_STALL_SENT_BIT,
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SC_ACK_RXED_BIT,
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SC_DATA_SEQUENCE_BIT };
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enum SCEndPointControlRegIndices {
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ENDPOINT_ENABLE_BIT = 0,
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ENDPOINT_READY_BIT,
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ENDPOINT_OUTDATA_SEQUENCE_BIT,
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ENDPOINT_SEND_STALL_BIT,
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ENDPOINT_ISO_ENABLE_BIT };
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enum SCMasterControlegIndices {
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SC_GLOBAL_ENABLE_BIT = 0,
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SC_TX_LINE_STATE_LSBIT,
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SC_TX_LINE_STATE_MSBIT,
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SC_DIRECT_CONTROL_BIT,
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SC_FULL_SPEED_LINE_POLARITY_BIT,
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SC_FULL_SPEED_LINE_RATE_BIT,
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SC_CONNECT_TO_HOST_BIT };
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enum SCinterruptRegIndices {
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SC_TRANS_DONE_BIT = 0,
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SC_RESUME_INT_BIT,
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SC_RESET_EVENT_BIT, //Line has entered reset state, or left reset state
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SC_SOF_RECEIVED_BIT,
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SC_NAK_SENT_INT_BIT,
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SC_VBUS_DET_INT_BIT };
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enum SC_TXTransactionTypes {
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SC_SETUP_TRANS = 0,
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SC_IN_TRANS,
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SC_OUTDATA_TRANS };
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enum SC_timeOuts {
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SC_RX_PACKET_TOUT = 18 };
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enum SCFakeOutConstants {
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SC_TB_RX_TOUT = 0,
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SC_TB_DC_AND_IDLE_TRIG,
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SC_TB_RESET };
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enum RXConnectStateConstants {
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SC_VBUS_DETECT_BIT = 2};
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// ---
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// --- Host constants
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// ---
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enum timeOuts {
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RX_PACKET_TOUT = 18 };
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enum HCRegIndices {
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TX_CONTROL_REG=0,
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TX_TRANS_TYPE_REG,
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TX_LINE_CONTROL_REG,
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TX_SOF_ENABLE_REG,
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TX_ADDR_REG,
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TX_ENDP_REG,
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FRAME_NUM_MSB_REG,
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FRAME_NUM_LSB_REG,
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INTERRUPT_STATUS_REG,
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INTERRUPT_MASK_REG,
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RX_STATUS_REG,
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RX_PID_REG,
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RX_ADDR_REG,
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RX_ENDP_REG,
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RX_CONNECT_STATE_REG,
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SOF_TIMER_MSB_REG,
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HCREG_BUFFER_LEN /* must be last constant in this enum */
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};
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enum TXControlRegIndices {
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TRANS_REQ_BIT = 0,
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SOF_SYNC_BIT,
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PREAMBLE_ENABLE_BIT,
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ISO_ENABLE_BIT };
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enum interruptRegIndices {
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TRANS_DONE_BIT = 0,
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RESUME_INT_BIT,
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CONNECTION_EVENT_BIT,
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SOF_SENT_BIT };
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enum RXStatusRegIndices {
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CRC_ERROR_BIT = 0,
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BIT_STUFF_ERROR_BIT,
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RX_OVERFLOW_BIT,
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RX_TIME_OUT_BIT,
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NAK_RXED_BIT,
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STALL_RXED_BIT,
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ACK_RXED_BIT,
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DATA_SEQUENCE_BIT };
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enum TXTransactionTypes {
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SETUP_TRANS = 0,
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IN_TRANS,
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OUTDATA0_TRANS,
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OUTDATA1_TRANS };
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enum TXLineControlIndices {
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TX_LINE_STATE_LSBIT = 0,
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TX_LINE_STATE_MSBIT,
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DIRECT_CONTROL_BIT,
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FULL_SPEED_LINE_POLARITY_BIT,
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FULL_SPEED_LINE_RATE_BIT };
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enum TXSOFEnableIndices {
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SOF_EN_BIT = 0 };
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enum SOFTimeConstants {
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SOF_TX_TIME = 20,
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SOF_TX_MARGIN = 2 };
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enum HCFakeOutConstants {
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HC_TB_RX_TOUT = 0,
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HC_TB_DC_AND_IDLE_TRIG,
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HC_TB_SOF_TRIG,
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HC_TB_RESET };
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// ---
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// --- Fifo constants
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// ---
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// fifo adddresses
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enum FifoAddresses {
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FIFO_DATA_REG = 0,
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FIFO_STATUS_REG,
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FIFO_DATA_COUNT_MSB,
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FIFO_DATA_COUNT_LSB,
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FIFO_CONTROL_REG };
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enum fifoSizes {
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SMALLEST_FIFO_SIZE = 64,
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LARGEST_FIFO_SIZE = 64,
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HOST_TX_FIFO_SIZE = 64,
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HOST_RX_FIFO_SIZE = 64,
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SLAVE_TX0_FIFO_SIZE = 64,
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SLAVE_RX0_FIFO_SIZE = 64,
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SLAVE_TX1_FIFO_SIZE = 64,
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SLAVE_RX1_FIFO_SIZE = 64,
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SLAVE_TX2_FIFO_SIZE = 64,
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SLAVE_RX2_FIFO_SIZE = 64,
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SLAVE_TX3_FIFO_SIZE = 64,
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SLAVE_RX3_FIFO_SIZE = 64
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};
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// ---
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// --- Memory map
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// ---
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// top level memory regions
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enum memoryRegions {
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HCREG_BASE = 0x0,
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HOST_RX_FIFO_BASE = 0x20,
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HOST_TX_FIFO_BASE = 0x30,
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SCREG_BASE = 0x40,
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EP0_RX_FIFO_BASE = 0x60,
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EP0_TX_FIFO_BASE = 0x70,
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EP1_RX_FIFO_BASE = 0x80,
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EP1_TX_FIFO_BASE = 0x90,
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EP2_RX_FIFO_BASE = 0xa0,
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EP2_TX_FIFO_BASE = 0xb0,
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EP3_RX_FIFO_BASE = 0xc0,
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EP3_TX_FIFO_BASE = 0xd0,
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HOST_SLAVE_CONTROL_BASE = 0xe0 };
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// Host registers
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enum hostMemMap {
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RA_HC_TX_CONTROL_REG = HCREG_BASE+TX_CONTROL_REG,
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RA_HC_TX_TRANS_TYPE_REG = HCREG_BASE+TX_TRANS_TYPE_REG,
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RA_HC_TX_LINE_CONTROL_REG = HCREG_BASE+TX_LINE_CONTROL_REG,
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RA_HC_TX_SOF_ENABLE_REG = HCREG_BASE+TX_SOF_ENABLE_REG,
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RA_HC_TX_ADDR_REG = HCREG_BASE+TX_ADDR_REG,
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RA_HC_TX_ENDP_REG = HCREG_BASE+TX_ENDP_REG,
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RA_HC_FRAME_NUM_MSB_REG = HCREG_BASE+FRAME_NUM_MSB_REG,
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RA_HC_FRAME_NUM_LSB_REG = HCREG_BASE+FRAME_NUM_LSB_REG,
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RA_HC_INTERRUPT_STATUS_REG = HCREG_BASE+INTERRUPT_STATUS_REG,
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RA_HC_INTERRUPT_MASK_REG = HCREG_BASE+INTERRUPT_MASK_REG,
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RA_HC_RX_STATUS_REG = HCREG_BASE+RX_STATUS_REG,
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RA_HC_RX_PID_REG = HCREG_BASE+RX_PID_REG,
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RA_HC_RX_ADDR_REG = HCREG_BASE+RX_ADDR_REG,
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RA_HC_RX_ENDP_REG = HCREG_BASE+RX_ENDP_REG,
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RA_HC_RX_CONNECT_STATE_REG = HCREG_BASE+RX_CONNECT_STATE_REG,
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RA_HC_RX_SOF_TIMER_MSB_REG = HCREG_BASE+SOF_TIMER_MSB_REG,
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RA_HC_RX_FIFO_DATA_REG = HOST_RX_FIFO_BASE + FIFO_DATA_REG,
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RA_HC_RX_FIFO_STATUS_REG = HOST_RX_FIFO_BASE + FIFO_STATUS_REG,
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RA_HC_RX_FIFO_DATA_COUNT_MSB = HOST_RX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
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RA_HC_RX_FIFO_DATA_COUNT_LSB = HOST_RX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
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RA_HC_RX_FIFO_CONTROL_REG = HOST_RX_FIFO_BASE + FIFO_CONTROL_REG,
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RA_HC_TX_FIFO_DATA_REG = HOST_TX_FIFO_BASE + FIFO_DATA_REG,
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RA_HC_TX_FIFO_STATUS_REG = HOST_TX_FIFO_BASE + FIFO_STATUS_REG,
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RA_HC_TX_FIFO_DATA_COUNT_MSB = HOST_TX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
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RA_HC_TX_FIFO_DATA_COUNT_LSB = HOST_TX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
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RA_HC_TX_FIFO_CONTROL_REG = HOST_TX_FIFO_BASE + FIFO_CONTROL_REG,
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};
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enum slaveMemMap {
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RA_EP0_CONTROL_REG = SCREG_BASE + ENDPOINT_CONTROL_REG,
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RA_EP0_STATUS_REG = SCREG_BASE + ENDPOINT_STATUS_REG,
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RA_EP0_TRANSTYPE_STATUS_REG = SCREG_BASE + ENDPOINT_TRANSTYPE_STATUS_REG,
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RA_EP0_NAK_TRANSTYPE_STATUS_REG = SCREG_BASE + NAK_TRANSTYPE_STATUS_REG,
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RA_EP1_CONTROL_REG = SCREG_BASE + NUM_OF_REGISTERS_PER_ENDPOINT + ENDPOINT_CONTROL_REG,
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RA_EP1_STATUS_REG = SCREG_BASE + NUM_OF_REGISTERS_PER_ENDPOINT + ENDPOINT_STATUS_REG,
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RA_EP1_TRANSTYPE_STATUS_REG = SCREG_BASE + NUM_OF_REGISTERS_PER_ENDPOINT+ ENDPOINT_TRANSTYPE_STATUS_REG,
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RA_EP1_NAK_TRANSTYPE_STATUS_REG = SCREG_BASE + NUM_OF_REGISTERS_PER_ENDPOINT + NAK_TRANSTYPE_STATUS_REG,
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RA_EP2_CONTROL_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*2) + ENDPOINT_CONTROL_REG,
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RA_EP2_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*2) + ENDPOINT_STATUS_REG,
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RA_EP2_TRANSTYPE_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*2) + ENDPOINT_TRANSTYPE_STATUS_REG,
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RA_EP2_NAK_TRANSTYPE_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*2) + NAK_TRANSTYPE_STATUS_REG,
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RA_EP3_CONTROL_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*3) + ENDPOINT_CONTROL_REG,
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RA_EP3_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*3) + ENDPOINT_STATUS_REG,
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RA_EP3_TRANSTYPE_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*3) + ENDPOINT_TRANSTYPE_STATUS_REG,
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RA_EP3_NAK_TRANSTYPE_STATUS_REG = SCREG_BASE + (NUM_OF_REGISTERS_PER_ENDPOINT*3) + NAK_TRANSTYPE_STATUS_REG,
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RA_SC_CONTROL_REG = SCREG_BASE + SC_CONTROL_REG,
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RA_SC_LINE_STATUS_REG = SCREG_BASE + SC_LINE_STATUS_REG,
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254 |
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RA_SC_INTERRUPT_STATUS_REG = SCREG_BASE + SC_INTERRUPT_STATUS_REG,
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255 |
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RA_SC_INTERRUPT_MASK_REG = SCREG_BASE + SC_INTERRUPT_MASK_REG,
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256 |
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RA_SC_ADDRESS = SCREG_BASE + SC_ADDRESS,
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257 |
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RA_SC_FRAME_NUM_MSP = SCREG_BASE + SC_FRAME_NUM_MSP,
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RA_SC_FRAME_NUM_LSP = SCREG_BASE + SC_FRAME_NUM_LSP,
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259 |
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260 |
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RA_EP0_RX_FIFO_DATA_REG = EP0_RX_FIFO_BASE + FIFO_DATA_REG,
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RA_EP0_RX_FIFO_STATUS_REG = EP0_RX_FIFO_BASE + FIFO_STATUS_REG,
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RA_EP0_RX_FIFO_DATA_COUNT_MSB = EP0_RX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
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RA_EP0_RX_FIFO_DATA_COUNT_LSB = EP0_RX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
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264 |
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RA_EP0_RX_FIFO_CONTROL_REG = EP0_RX_FIFO_BASE + FIFO_CONTROL_REG,
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265 |
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RA_EP0_TX_FIFO_DATA_REG = EP0_TX_FIFO_BASE + FIFO_DATA_REG,
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266 |
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RA_EP0_TX_FIFO_STATUS_REG = EP0_TX_FIFO_BASE + FIFO_STATUS_REG,
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267 |
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RA_EP0_TX_FIFO_DATA_COUNT_MSB = EP0_TX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
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268 |
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RA_EP0_TX_FIFO_DATA_COUNT_LSB = EP0_TX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
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269 |
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RA_EP0_TX_FIFO_CONTROL_REG = EP0_TX_FIFO_BASE + FIFO_CONTROL_REG,
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270 |
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271 |
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RA_EP1_RX_FIFO_DATA_REG = EP1_RX_FIFO_BASE + FIFO_DATA_REG,
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272 |
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RA_EP1_RX_FIFO_STATUS_REG = EP1_RX_FIFO_BASE + FIFO_STATUS_REG,
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273 |
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RA_EP1_RX_FIFO_DATA_COUNT_MSB = EP1_RX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
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274 |
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RA_EP1_RX_FIFO_DATA_COUNT_LSB = EP1_RX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
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275 |
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RA_EP1_RX_FIFO_CONTROL_REG = EP1_RX_FIFO_BASE + FIFO_CONTROL_REG,
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276 |
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RA_EP1_TX_FIFO_DATA_REG = EP1_TX_FIFO_BASE + FIFO_DATA_REG,
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277 |
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RA_EP1_TX_FIFO_STATUS_REG = EP1_TX_FIFO_BASE + FIFO_STATUS_REG,
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278 |
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RA_EP1_TX_FIFO_DATA_COUNT_MSB = EP1_TX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
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279 |
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RA_EP1_TX_FIFO_DATA_COUNT_LSB = EP1_TX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
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280 |
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RA_EP1_TX_FIFO_CONTROL_REG = EP1_TX_FIFO_BASE + FIFO_CONTROL_REG,
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281 |
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282 |
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RA_EP2_RX_FIFO_DATA_REG = EP2_RX_FIFO_BASE + FIFO_DATA_REG,
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283 |
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RA_EP2_RX_FIFO_STATUS_REG = EP2_RX_FIFO_BASE + FIFO_STATUS_REG,
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284 |
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RA_EP2_RX_FIFO_DATA_COUNT_MSB = EP2_RX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
|
285 |
|
|
RA_EP2_RX_FIFO_DATA_COUNT_LSB = EP2_RX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
|
286 |
|
|
RA_EP2_RX_FIFO_CONTROL_REG = EP2_RX_FIFO_BASE + FIFO_CONTROL_REG,
|
287 |
|
|
RA_EP2_TX_FIFO_DATA_REG = EP2_TX_FIFO_BASE + FIFO_DATA_REG,
|
288 |
|
|
RA_EP2_TX_FIFO_STATUS_REG = EP2_TX_FIFO_BASE + FIFO_STATUS_REG,
|
289 |
|
|
RA_EP2_TX_FIFO_DATA_COUNT_MSB = EP2_TX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
|
290 |
|
|
RA_EP2_TX_FIFO_DATA_COUNT_LSB = EP2_TX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
|
291 |
|
|
RA_EP2_TX_FIFO_CONTROL_REG = EP2_TX_FIFO_BASE + FIFO_CONTROL_REG,
|
292 |
|
|
|
293 |
|
|
RA_EP3_RX_FIFO_DATA_REG = EP3_RX_FIFO_BASE + FIFO_DATA_REG,
|
294 |
|
|
RA_EP3_RX_FIFO_STATUS_REG = EP3_RX_FIFO_BASE + FIFO_STATUS_REG,
|
295 |
|
|
RA_EP3_RX_FIFO_DATA_COUNT_MSB = EP3_RX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
|
296 |
|
|
RA_EP3_RX_FIFO_DATA_COUNT_LSB = EP3_RX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
|
297 |
|
|
RA_EP3_RX_FIFO_CONTROL_REG = EP3_RX_FIFO_BASE + FIFO_CONTROL_REG,
|
298 |
|
|
RA_EP3_TX_FIFO_DATA_REG = EP3_TX_FIFO_BASE + FIFO_DATA_REG,
|
299 |
|
|
RA_EP3_TX_FIFO_STATUS_REG = EP3_TX_FIFO_BASE + FIFO_STATUS_REG,
|
300 |
|
|
RA_EP3_TX_FIFO_DATA_COUNT_MSB = EP3_TX_FIFO_BASE + FIFO_DATA_COUNT_MSB,
|
301 |
|
|
RA_EP3_TX_FIFO_DATA_COUNT_LSB = EP3_TX_FIFO_BASE + FIFO_DATA_COUNT_LSB,
|
302 |
|
|
RA_EP3_TX_FIFO_CONTROL_REG = EP3_TX_FIFO_BASE + FIFO_CONTROL_REG
|
303 |
|
|
};
|
304 |
|
|
|
305 |
|
|
enum hostSlaveCommonMemMap {
|
306 |
|
|
RA_HOST_SLAVE_MODE = HOST_SLAVE_CONTROL_BASE + HOST_SLAVE_MODE_CTRL,
|
307 |
|
|
RA_HOST_SLAVE_VERSION = HOST_SLAVE_CONTROL_BASE + HOST_SLAVE_VERSION_NUM
|
308 |
|
|
};
|
309 |
|
|
|
310 |
|
|
|
311 |
|
|
|
312 |
|
|
// ---
|
313 |
|
|
// --- USB SIE constants
|
314 |
|
|
// ---
|
315 |
|
|
enum USBLineStates {
|
316 |
|
|
// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
|
317 |
|
|
ONE_ZERO = 0x2,
|
318 |
|
|
ZERO_ONE = 0x1,
|
319 |
|
|
SE0 = 0x0,
|
320 |
|
|
SE1 = 0x3 };
|
321 |
|
|
|
322 |
|
|
enum limits {
|
323 |
|
|
MAX_CONSEC_SAME_BITS = 6,
|
324 |
|
|
RESUME_WAIT_TIME = 10,
|
325 |
|
|
RESUME_LEN = 40,
|
326 |
|
|
CONNECT_WAIT_TIME = 120,
|
327 |
|
|
DISCONNECT_WAIT_TIME = 120 };
|
328 |
|
|
|
329 |
|
|
enum RXConnectStates {
|
330 |
|
|
DISCONNECT = 0,
|
331 |
|
|
LOW_SPEED_CONNECT = 1,
|
332 |
|
|
FULL_SPEED_CONNECT = 2 };
|
333 |
|
|
|
334 |
|
|
|
335 |
|
|
// ---
|
336 |
|
|
// --- USB 1.1 constants
|
337 |
|
|
// ---
|
338 |
|
|
enum PIDTypes {
|
339 |
|
|
OUT = 0x1,
|
340 |
|
|
IN = 0x9,
|
341 |
|
|
SOF = 0x5,
|
342 |
|
|
SETUP = 0xd,
|
343 |
|
|
DATA0 = 0x3,
|
344 |
|
|
DATA1 = 0xb,
|
345 |
|
|
ACK = 0x2,
|
346 |
|
|
NAK = 0xa,
|
347 |
|
|
STALL = 0xe,
|
348 |
|
|
PREAMBLE = 0xc };
|
349 |
|
|
|
350 |
|
|
enum PIDGroups {
|
351 |
|
|
SPECIAL = 0x0,
|
352 |
|
|
TOKEN = 0x1,
|
353 |
|
|
HANDSHAKE = 0x2,
|
354 |
|
|
DATA = 0x3 };
|
355 |
|
|
|
356 |
|
|
enum SyncByte {
|
357 |
|
|
SYNC_BYTE = 0x80 };
|
358 |
|
|
|
359 |
|
|
enum hostSlaveFlags {
|
360 |
|
|
SLAVE = 0,
|
361 |
|
|
HOST};
|
362 |
|
|
|
363 |
|
|
enum dataGenFlags {
|
364 |
|
|
NO_GEN=0,
|
365 |
|
|
SEQ_GEN,
|
366 |
|
|
RAND_GEN};
|
367 |
|
|
|
368 |
|
|
|
369 |
|
|
// Added by Julius
|
370 |
|
|
enum usbStandardRequests {
|
371 |
|
|
GET_STATUS=0,
|
372 |
|
|
CLEAR_FEATURE,
|
373 |
|
|
RESERVED0,
|
374 |
|
|
SET_FEATURE,
|
375 |
|
|
RESERVED1,
|
376 |
|
|
SET_ADDRESS,
|
377 |
|
|
GET_DESCRIPTOR,
|
378 |
|
|
SET_DESCRIPTOR,
|
379 |
|
|
GET_CONFIGURATION,
|
380 |
|
|
SET_CONFIGURATION};
|
381 |
|
|
|
382 |
|
|
|
383 |
|
|
#endif
|