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julius |
/*
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*
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* USB usbhostslave core slave register defines
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*
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* Julius Baxter, julius@opencores.org
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*
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*/
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#ifndef _USBHOSTSLAVE_SLAVE_H_
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#define _USBHOSTSLAVE_SLAVE_H_
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extern const int USBHOSTSLAVE_SLAVE_CORE_ADR[2];
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void usb_slave_set_addr(int, char);
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void usb_slave_global_enable_endpoints(int);
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void usb_slave_global_disable_endpoints(int);
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void usb_slave_endpoint_enable(int, int);
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void usb_slave_endpoint_disable(int, int);
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void usb_slave_endpoint_ready(int, int);
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void usb_slave_endpoint_unready(int, int);
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void usb_slave_endpoint_outdataseqset(int, int, int);
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void usb_slave_endpoint_sendstallset(int, int, int);
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void usb_slave_endpoint_isoset(int, int, int);
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int usb_slave_get_frame_num(int);
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void usb_slave_endpoint_tx_fifo_write(int, int, char);
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char usb_slave_endpoint_rx_fifo_read_data(int, int);
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int usb_slave_endpoint_rx_fifo_read_count(int, int);
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void usb_slave_endpoint_rx_fifo_clear(int, int);
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#define USBSLAVE_EP0_CONTROL_REG 0x40
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#define USBSLAVE_EP0_STATUS_REG 0x41
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#define USBSLAVE_EP0_TRANSTYPE_STATUS_REG 0x42
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#define USBSLAVE_EP0_NAK_TRANSTYPE_STATUS_REG 0x43
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#define USBSLAVE_EP1_CONTROL_REG 0x44
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#define USBSLAVE_EP1_STATUS_REG 0x45
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#define USBSLAVE_EP1_TRANSTYPE_STATUS_REG 0x46
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#define USBSLAVE_EP1_NAK_TRANSTYPE_STATUS_REG 0x47
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#define USBSLAVE_EP2_CONTROL_REG 0x48
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#define USBSLAVE_EP2_STATUS_REG 0x49
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#define USBSLAVE_EP2_TRANSTYPE_STATUS_REG 0x4a
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#define USBSLAVE_EP2_NAK_TRANSTYPE_STATUS_REG 0x4b
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#define USBSLAVE_EP3_CONTROL_REG 0x4c
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#define USBSLAVE_EP3_STATUS_REG 0x4d
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#define USBSLAVE_EP3_TRANSTYPE_STATUS_REG 0x4e
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#define USBSLAVE_EP3_NAK_TRANSTYPE_STATUS_REG 0x4f
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#define USBSLAVE_SC_CONTROL_REG 0x50
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#define USBSLAVE_SC_LINE_STATUS_REG 0x51
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#define USBSLAVE_SC_INTERRUPT_STATUS_REG 0x52
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#define USBSLAVE_SC_INTERRUPT_MASK_REG 0x53
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#define USBSLAVE_SC_ADDRESS 0x54
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#define USBSLAVE_SC_FRAME_NUM_MSP 0x55
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#define USBSLAVE_SC_FRAME_NUM_LSP 0x56
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#define USBSLAVE_EP0_RX_FIFO_DATA 0x60
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#define USBSLAVE_EP0_RX_FIFO_DATA_CNT_MSB 0x62
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#define USBSLAVE_EP0_RX_FIFO_DATA_CNT_LSB 0x63
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#define USBSLAVE_EP0_RX_FIFO_CONTROL_REG 0x64
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#define USBSLAVE_EP0_TX_FIFO_DATA 0x70
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#define USBSLAVE_EP0_TX_FIFO_CONTROL_REG 0x74
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#define USBSLAVE_EP1_RX_FIFO_DATA 0x80
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#define USBSLAVE_EP1_RX_FIFO_DATA_CNT_MSB 0x82
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#define USBSLAVE_EP1_RX_FIFO_DATA_CNT_LSB 0x83
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#define USBSLAVE_EP1_RX_FIFO_CONTROL_REG 0x84
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#define USBSLAVE_EP1_TX_FIFO_DATA 0x90
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#define USBSLAVE_EP1_TX_FIFO_CONTROL_REG 0x94
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#define USBSLAVE_EP2_RX_FIFO_DATA 0xa0
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#define USBSLAVE_EP2_RX_FIFO_DATA_CNT_MSB 0xa2
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#define USBSLAVE_EP2_RX_FIFO_DATA_CNT_LSB 0xa3
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#define USBSLAVE_EP2_RX_FIFO_CONTROL_REG 0xa4
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#define USBSLAVE_EP2_TX_FIFO_DATA 0xb0
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#define USBSLAVE_EP2_TX_FIFO_CONTROL_REG 0xb4
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#define USBSLAVE_EP3_RX_FIFO_DATA 0xc0
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#define USBSLAVE_EP3_RX_FIFO_DATA_CNT_MSB 0xc2
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#define USBSLAVE_EP3_RX_FIFO_DATA_CNT_LSB 0xc3
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#define USBSLAVE_EP3_RX_FIFO_CONTROL_REG 0xc4
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#define USBSLAVE_EP3_TX_FIFO_DATA 0xd0
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#define USBSLAVE_EP3_TX_FIFO_CONTROL_REG 0xd4
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#define RX_FIFO_DATA 0x20
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#define TX_CONTROL_REG 0x00
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#define TX_TRANS_TYPE_REG 0x01
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#define TX_ADDR_REG 0x04
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#define TX_ENDP_REG 0x05
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#define TX_FIFO_DATA 0x30
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#define INTERRUPT_MASK_REG 0x09
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#define RX_CONNECT_STATE_REG 0x0e
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#define INTERRUPT_STATUS_REG 0x08
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#define HOST_SLAVE_CONTROL_REG 0xe0
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#define HOST_SLAVE_VERSION_REG 0xe1
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#define TX_LINE_CONTROL_REG 0x02
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// Bit masks for registers
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#define USBSLAVE_CONTROL_REG_ENDPOINT_ENABLE 0x01
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#define USBSLAVE_CONTROL_REG_ENDPOINT_READY 0x02
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#define USBSLAVE_CONTROL_REG_ENDPOINT_OUTDATA_SEQ 0x04
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#define USBSLAVE_CONTROL_REG_ENDPOINT_SEND_STALL 0x08
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#define USBSLAVE_CONTROL_REG_ENDPOINT_ISO_ENABLE 0x10
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#define USBSLAVE_STATUS_REG_SC_CRC_ERROR 0x01
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#define USBSLAVE_STATUS_REG_SC_BIT_STUFF_ERROR 0x02
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#define USBSLAVE_STATUS_REG_SC_RX_OVERFLOW 0x04
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#define USBSLAVE_STATUS_REG_SC_RX_TIME_OUT 0x08
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#define USBSLAVE_STATUS_REG_SC_NAK_SENT 0x10
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#define USBSLAVE_STATUS_REG_SC_STALL_SENT 0x20
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#define USBSLAVE_STATUS_REG_SC_ACK_RXED 0x40
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#define USBSLAVE_STATUS_REG_SC_DATA_SEQ 0x80
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#define USBSLAVE_TRANSTYPE_STATUS_REG_TRANS_TYPE_MASK 0x03
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#define USBSLAVE_TRANSTYPE_STATUS_REG_TRANS_TYPE_SETUP 0x00
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#define USBSLAVE_TRANSTYPE_STATUS_REG_TRANS_TYPE_IN 0x01
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#define USBSLAVE_TRANSTYPE_STATUS_REG_TRANS_TYPE_OUTDATA 0x02
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#define USBSLAVE_SC_CONTROL_REG_GLOBAL_ENABLE 0x01
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#define USBSLAVE_SC_CONTROL_REG_TX_LINE_STATE 0x06
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#define USBSLAVE_SC_CONTROL_REG_DIRECT_CONTROL 0x08
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#define USBSLAVE_SC_CONTROL_REG_FULL_SPEED_LINE_POLARITY 0x10
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#define USBSLAVE_SC_CONTROL_REG_FULL_SPEED_LINE_BITRATE 0x20
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#define USBSLAVE_SC_CONTROL_REG_CONNECT_TO_HOST 0x40
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#define USBSLAVE_SC_LINE_STATUS_REG_RX_LINE_STATE 0x3
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#define USBSLAVE_SC_LINE_STATUS_REG_VBUS_STATE 0x4
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#define USBSLAVE_SC_LINE_STATUS_REG_RX_LINE_STATE_RESET 0x0
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#define USBSLAVE_SC_LINE_STATUS_REG_RX_LINE_STATE_LSPEED 0x1
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#define USBSLAVE_SC_LINE_STATUS_REG_RX_LINE_STATE_FSPEED 0x2
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#define USBSLAVE_SC_INTERRUPT_STATUS_REG_TRANS_DONE 0x01
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#define USBSLAVE_SC_INTERRUPT_STATUS_REG_RESUME_INT 0x02
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#define USBSLAVE_SC_INTERRUPT_STATUS_REG_RESET_EVENT 0x04
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#define USBSLAVE_SC_INTERRUPT_STATUS_REG_SOF_RECEIVED 0x08
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#define USBSLAVE_SC_INTERRUPT_STATUS_REG_NAK_SENT 0x10
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#define USBSLAVE_SC_INTERRUPT_STATUS_REG_VBUS_DETECT 0x20
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#define TRANS_DONE_MASK 0x01
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#define RESUME_INT_MASK 0x02
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#define CONNECTION_EVENT 0x04
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#define SOF_SENT_BIT 0x08
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#define USBSLAVE_FIFO_CONTROL_REG_FORCE_EMPTY 0x1
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#endif
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