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408 |
julius |
/*
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*
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* Simple USB slave test
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*
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* Adam Edvardsson, adam.edvardsson@orsoc.se
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* Julius Baxter, julius.baxter@orsoc.se
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*
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*/
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#include "cpu-utils.h"
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#include "spr-defs.h"
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#include "board.h"
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#include "usbhostslave-slave.h"
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#include "int.h"
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#include "printf.h"
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volatile int i;
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// We rely on USB1 being a slave, check it's in the design.
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#include "orpsoc-defines.h"
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# ifndef USB1
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# error
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# error USB1 module not in design - enable it to run USB slave tests
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# error
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# else
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// Using USB1, check that it's a HOST
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# ifdef USB1_ONLY_HOST
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# error
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# error Module USB1 is a host only - must have slave capability to run tests
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# error
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# else
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# define USBSLAVECORE 1
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# endif
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# endif
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int main()
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{
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int usb_core = USBSLAVECORE;
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volatile unsigned char interrupt_status;
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// disable all endpoints first
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usb_slave_global_disable_endpoints(usb_core);
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printf("\nUSB Slave test for usb core %d\n", USBSLAVECORE);
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//Enable slave Setup slave
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//Enable fullspeed,
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//Connect to host (D+ pullup)
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REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] + USBSLAVE_SC_CONTROL_REG) =
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0x71;
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//Set Slave addres
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usb_slave_set_addr(usb_core, 0x63);
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//Enable endpont
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REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] + USBSLAVE_EP0_CONTROL_REG) =
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0x03;
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//Enable interupt
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REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_MASK_REG) = 0xff;
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//Test 1, check for VBUS connection
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//Poll for VBUS interupt.
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interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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while ((interrupt_status & USBSLAVE_SC_INTERRUPT_STATUS_REG_VBUS_DETECT)
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!= USBSLAVE_SC_INTERRUPT_STATUS_REG_VBUS_DETECT) {
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interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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}
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//VBUS change detected
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// Clear interrupt
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REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG)
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= USBSLAVE_SC_INTERRUPT_STATUS_REG_VBUS_DETECT;
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// Check so VBUS is present
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if ((REG8
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(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_LINE_STATUS_REG) &
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USBSLAVE_SC_LINE_STATUS_REG_VBUS_STATE)
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== USBSLAVE_SC_LINE_STATUS_REG_VBUS_STATE)
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{
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report(0x00000001);
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} else {
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report(0x00000001);
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exit(0xBAAAAAAD);
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}
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//Test 2, check for bus-reset and fullspeed present
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interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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while ((interrupt_status & USBSLAVE_SC_INTERRUPT_STATUS_REG_RESET_EVENT)
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!= USBSLAVE_SC_INTERRUPT_STATUS_REG_RESET_EVENT) {
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interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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}
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//Bus reset
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// Clear interrupt
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REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG)
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= USBSLAVE_SC_INTERRUPT_STATUS_REG_RESET_EVENT;
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//Check so Fullspeed is activated
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if ((REG8
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(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_LINE_STATUS_REG) &
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USBSLAVE_SC_LINE_STATUS_REG_RX_LINE_STATE_FSPEED)
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== USBSLAVE_SC_LINE_STATUS_REG_RX_LINE_STATE_FSPEED) {
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report(0x00000002);
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} else {
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report(0x00000002);
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exit(0xBAAAAAAD);
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}
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// Test 3, check for first transfer completion and check for correct data,
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// transfertype and nr byte sent.
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//
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interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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while ((interrupt_status & USBSLAVE_SC_INTERRUPT_STATUS_REG_TRANS_DONE)
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!= USBSLAVE_SC_INTERRUPT_STATUS_REG_TRANS_DONE) {
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interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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}
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//Transfer complete, check for correct typ of transfer (SETUP_TRANSFER)
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if (REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_EP0_TRANSTYPE_STATUS_REG) != 0) {
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report(0x10000003);
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exit(0xBAAAAAAD);
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}
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//Check nr byte sent
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if (REG8
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(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_EP0_RX_FIFO_DATA_CNT_LSB) != 2) {
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report(0x20000003);
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exit(0xBAAAAAAD);
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}
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//Check recived data
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if ((REG8
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(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_EP0_RX_FIFO_DATA) == 0)
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&&
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(REG8
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(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_EP0_RX_FIFO_DATA) == 1)) {
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report(0x00000003);
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} else {
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report(0x00000003);
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report(0xBAAAAAAD);
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exit(0);
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}
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//Enable endpoint again
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//Enable fullspeed,
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//Connect to host (D+ pullup)
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REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] + USBSLAVE_SC_CONTROL_REG) =
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0x71;
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//Enable endpont
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REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] + USBSLAVE_EP0_CONTROL_REG) =
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0x03;
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// Clear interrupt
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REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG)
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= USBSLAVE_SC_INTERRUPT_STATUS_REG_TRANS_DONE;
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// Test 4, check for first transfer completion and check for correct data,
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// transfertype and nr byte sent.
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//
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interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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while ((interrupt_status & USBSLAVE_SC_INTERRUPT_STATUS_REG_TRANS_DONE)
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!= USBSLAVE_SC_INTERRUPT_STATUS_REG_TRANS_DONE) {
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interrupt_status =
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REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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interrupt_status =
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REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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}
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//Transfer complete, check for correct typ of transfer (OUT_TRANSFER)
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if (REG8
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(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_EP0_TRANSTYPE_STATUS_REG)
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!= USBSLAVE_TRANSTYPE_STATUS_REG_TRANS_TYPE_OUTDATA) {
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report(0x10000004);
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exit(0xBAAAAAAD);
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}
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//Check nr byte sent
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if (REG8
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(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_EP0_RX_FIFO_DATA_CNT_LSB) != 20) {
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report(0x20000004);
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exit(0xBAAAAAAD);
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}
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//Check recived data
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for (i = 0; i < 20; i++) {
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if (REG8
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(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_EP0_RX_FIFO_DATA) != i) {
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report(0x00000004);
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report(0xBAAAAAAD);
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exit(0);
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}
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}
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report(0x00000004);
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//Test 5, check for NAK interupt, and type of transfer.
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//
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interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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while ((interrupt_status & USBSLAVE_SC_INTERRUPT_STATUS_REG_NAK_SENT)
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!= USBSLAVE_SC_INTERRUPT_STATUS_REG_NAK_SENT) {
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interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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}
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//Transfer NAK, check for correct typ of transfer (OUT_TRANSFER)
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if (REG8
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(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_EP0_NAK_TRANSTYPE_STATUS_REG)
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!= USBSLAVE_TRANSTYPE_STATUS_REG_TRANS_TYPE_OUTDATA) {
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report(0x10000005);
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exit(0xBAAAAAAD);
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}
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report(0x00000005);
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// Clear all interrupt
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REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG) = 0x3f;
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//Test 6, IN-transfer to endpoint 2
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//Connect to host (D+ pullup)
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REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] + USBSLAVE_SC_CONTROL_REG) =
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0x71;
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usb_slave_set_addr(usb_core, 0x63);
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//Enable endpoint
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REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] + USBSLAVE_EP2_CONTROL_REG) =
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0x03;
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//Fill TX_FIFO
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for (i = 0; i <= 20; i++) {
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REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_EP2_TX_FIFO_DATA) = i;
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}
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interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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while ((interrupt_status & USBSLAVE_SC_INTERRUPT_STATUS_REG_TRANS_DONE)
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!= USBSLAVE_SC_INTERRUPT_STATUS_REG_TRANS_DONE) {
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interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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interrupt_status = REG8(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_SC_INTERRUPT_STATUS_REG);
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282 |
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}
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284 |
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285 |
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//Transfer complete, check for correct typ of transfer (IN_TRANSFER)
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286 |
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if ((REG8
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(USBHOSTSLAVE_SLAVE_CORE_ADR[usb_core] +
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USBSLAVE_EP2_TRANSTYPE_STATUS_REG)
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& USBSLAVE_TRANSTYPE_STATUS_REG_TRANS_TYPE_IN) !=
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USBSLAVE_TRANSTYPE_STATUS_REG_TRANS_TYPE_IN) {
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report(0x10000006);
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exit(0xBAAAAAAD);
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}
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295 |
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296 |
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//Fill TX_FIFO
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297 |
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//while(1){}
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298 |
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299 |
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//When transfer request arrive, fill TX-FIFO 0-20, and start transfer
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300 |
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// data = 8'h00;
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//for (i=0; i<dataSize; i=i+1) begin
|
302 |
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// testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `EP2_TX_FIFO_BASE + `FIFO_DATA_REG , data);
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// data = data + 1'b1;
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// end
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305 |
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// testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
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306 |
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307 |
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// Finish simulation
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308 |
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exit(0x8000000d);
|
309 |
|
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}
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