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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [generic/] [ft/] [bench/] [verilog/] [or1200_ft_stim.v] - Blame information for rev 483

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`include "timescale.v"
`include "or1200_defines.v"
`include "orpsoc-testbench-defines.v"
`include "test-defines.v"
 
//
// Top of TB
//
`define TB_TOP orpsoc_testbench
 
//
// Top of DUT
//
`define DUT_TOP `TB_TOP.dut
 
//
// Top of OR1200 inside test bench
//
`define OR1200_TOP `DUT_TOP.or1200_top0
 
 
`define CPU or1200
`define CPU_cpu or1200_cpu
`define CPU_rf or1200_rf
`define CPU_except or1200_except
`define CPU_ctrl or1200_ctrl
`define CPU_sprs or1200_sprs
`define CPU_ic_top or1200_ic_top
`define CPU_ic_ram or1200_ic_ram
`define CPU_ic_tag or1200_ic_tag
`define CPU_dc_top or1200_dc_top
`define CPU_dc_ram or1200_dc_ram
`define CPU_dc_tag or1200_dc_tag
 
`define CPU_immu_top or1200_immu_top
`define CPU_immu_tlb or1200_immu_tlb
`define CPU_dmmu_top or1200_dmmu_top
`define CPU_dmmu_tlb or1200_dmmu_tlb
 
`define CPU_CORE_CLK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk
 
`define FT_STIM_MEM_LOC 32'h00000004
`define FT_STIM_GO_WORD 32'h88000000
 
module or1200_ft_stim;
 
   reg debug_on;
 
 
`ifdef OR1200_RAM_PARITY
 
 
 
 `define RAM_WB_TOP `DUT_TOP.ram_wb0.ram_wb_b3_0
   task get_ram_word;
      input [31:0] addr;
      output [31:0] insn;
      begin
         insn = `RAM_WB_TOP.get_mem32(addr[31:2]);
      end
   endtask // get_ram_word
 
   task set_ram_word;
      input [31:0] addr;
      input [31:0] word;
      reg          dummy;
      begin
         dummy = `RAM_WB_TOP.set_mem32(addr[31:2], word);
      end
   endtask // set_ram_word
 
 
   task wait_for_start;
      reg [31:0] mem_word;
      begin
         get_ram_word(`FT_STIM_MEM_LOC, mem_word);
         while(mem_word !== `FT_STIM_GO_WORD)
           begin
 
//            if (debug_on)
//              $display("%m: Wait for start, read %h",mem_word);
 
              #100000;
              get_ram_word(`FT_STIM_MEM_LOC, mem_word);
           end
      end
   endtask // wait_for_start
 
   task get_command;
      output [31:0] out_cmd;
 
      reg [31:0] mem_word;
      begin
         get_ram_word(`FT_STIM_MEM_LOC, mem_word);
         while(mem_word === 32'h0)
           begin
              #10000;
 
//            if (debug_on)
//              $display("%m: get_command %h",mem_word);
 
              get_ram_word(`FT_STIM_MEM_LOC, mem_word);
           end
         out_cmd = mem_word;
      end
   endtask // get_command
 
   task ack_command;
      begin
//       if (debug_on)
//         $display("%m: Ack command");
      set_ram_word(`FT_STIM_MEM_LOC, 0);
      end
   endtask // ack_command
 
   task inject_ic_ram_fault;
      input [31:0] cmd;
      reg [23:0]   word_number;
      reg [7:0]    bit_number;
 
      begin
         // Get line number from command
         word_number = cmd[15:0];
         bit_number = cmd[23:16];
         if (debug_on)
           $display("%m: inject error into IC RAM word 0x%h, data bit %02d",
                    word_number, bit_number);
 
         `OR1200_TOP.`CPU_ic_top.`CPU_ic_ram.ic_ram0.gen_parity_err(word_number,
                                                                    -1,
                                                                    bit_number);
         ack_command;
      end
   endtask // inject_ic_ram_fault
 
   task inject_ic_tag_fault;
      input [31:0] cmd;
      reg [23:0]   tag_word;
      reg [7:0]    bit_number;
      begin
         // Get line number from command
         tag_word = cmd[15:0];
         bit_number = cmd[23:16];
         if (debug_on)
           $display("%m: inject error into IC tag line 0x%h, data bit %02d",
                    tag_word, bit_number);
 
         `OR1200_TOP.`CPU_ic_top.`CPU_ic_tag.ic_tag0.gen_parity_err(tag_word,
                                                                    -1,
                                                                    bit_number);
         ack_command;
      end
   endtask
 
   task inject_dc_ram_fault;
      input [31:0] cmd;
      reg [23:0]   word_number;
      reg [7:0]    bit_number;
 
      begin
         // Get line number from command
         word_number = cmd[15:0];
         bit_number = cmd[23:16];
         if (debug_on)
           $display("%m: inject error into DC RAM word 0x%h, data bit %02d",
                    word_number, bit_number);
 
         `OR1200_TOP.`CPU_dc_top.`CPU_dc_ram.dc_ram0.gen_parity_err(word_number,
                                                                    bit_number);
         ack_command;
      end
   endtask
 
   task inject_dc_tag_fault;
      input [31:0] cmd;
      reg [23:0]   tag_word;
      reg [7:0]    bit_number;
      begin
         // Get line number from command
         tag_word = cmd[15:0];
         bit_number =cmd[23:16];
         if (debug_on)
           $display("%m: inject error into DC tag line 0x%h, data bit %02d",
                    tag_word, bit_number);
 
         `OR1200_TOP.`CPU_dc_top.`CPU_dc_tag.dc_tag0.gen_parity_err(tag_word,
                                                                    -1,
                                                                    bit_number);
         ack_command;
      end
   endtask
 
   task inject_immu_fault;
      input tr;
      input [31:0] cmd;
      reg [23:0]   mem_word;
      reg [7:0]    bit_number;
      begin
         // Get line number from command
         mem_word = cmd[15:0];
         bit_number =cmd[23:16];
         if (tr)
           begin
              if (debug_on)
                $display("%m: inject error into iTLB TR RAM, 0x%h, bit %02d",
                         mem_word, bit_number);
 
   `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_tr_ram.gen_parity_err(
                                                                   mem_word,
                                                                   -1,
                                                                   bit_number);
           end
         else
           begin
              if (debug_on)
                $display("%m: inject error into iTLB MR RAM, 0x%h, bit %02d",
                         mem_word, bit_number);
 
   `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_mr_ram.gen_parity_err(
                                                                   mem_word,
                                                                   -1,
                                                                   bit_number);
 
           end // else: !if(tr)
 
         ack_command;
 
      end
   endtask // inject_immu_fault
 
   task inject_dmmu_fault;
      input tr;
      input [31:0] cmd;
      reg [23:0]   mem_word;
      reg [7:0]    bit_number;
      begin
         // Get line number from command
         mem_word = cmd[15:0];
         bit_number =cmd[23:16];
         if (tr)
           begin
              if (debug_on)
                $display("%m: inject error into dtlb TR RAM, 0x%h, bit %02d",
                         mem_word, bit_number);
 
   `OR1200_TOP.`CPU_dmmu_top.`CPU_dmmu_tlb.dtlb_tr_ram.gen_parity_err(
                                                                   mem_word,
                                                                   -1,
                                                                   bit_number);
           end
         else
           begin
              if (debug_on)
                $display("%m: inject error into dtlb MR RAM, 0x%h, bit %02d",
                         mem_word, bit_number);
 
   `OR1200_TOP.`CPU_dmmu_top.`CPU_dmmu_tlb.dtlb_mr_ram.gen_parity_err(
                                                                   mem_word,
                                                                   -1,
                                                                   bit_number);
 
           end // else: !if(tr)
 
         ack_command;
 
      end
   endtask
 
 
   task inject_rf_fault;
      input [31:0] cmd;
      reg [23:0]   gpr_no;
      reg [7:0]    bit_number;
      begin
         bit_number =cmd[23:16];
         gpr_no = cmd[15:0];
 
         if (debug_on)
           $display("%m: inject error into register file, r%02d, bit %02d",
                    gpr_no, bit_number);
 
         `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.gen_parity_err(   gpr_no,
                                                             -1,
                                                             bit_number);
         `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_b.gen_parity_err(   gpr_no,
                                                             -1,
                                                             bit_number);
 
         ack_command;
 
      end
   endtask
 
   reg [31:0] cmd;
 
 
`define FT_STIM_CMD_WORD_CMD_POS 31:24
`define FT_STIM_CMD_WORD_CMD_WIDTH 8
`define FT_STIM_CMD_WORD_DATA_POS 23:0
`define FT_STIM_CMD_WORD_DATA_WIDTH 24
 
`define FT_STIM_CMD_IC_RAM_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h1
`define FT_STIM_CMD_IC_TAG_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h2
`define FT_STIM_CMD_DC_RAM_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h3
`define FT_STIM_CMD_DC_TAG_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h4
 
`define FT_STIM_CMD_DMMU_MR_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h5
`define FT_STIM_CMD_DMMU_TR_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h6
`define FT_STIM_CMD_IMMU_MR_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h7
`define FT_STIM_CMD_IMMU_TR_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h8
 
`define FT_STIM_CMD_RF_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h9
 
`define FT_STIM_CMD_DEBUG_ON `FT_STIM_CMD_WORD_CMD_WIDTH'hff
`define FT_STIM_CMD_DEBUG_OFF `FT_STIM_CMD_WORD_CMD_WIDTH'hfe
 
 
initial
  begin
     #10;
 
     // Disable to begin with
     debug_on = 1;
 
     // Wait for software to indicate the test is ready to run.
     wait_for_start;
 
     // Ack our receipt of start
     ack_command;
 
     while(1)
       begin
          cmd = 32'hdeaddead;
 
          get_command(cmd);
 
          case(cmd[`FT_STIM_CMD_WORD_CMD_POS])
            `FT_STIM_CMD_IC_RAM_FAULT: begin
               inject_ic_ram_fault(cmd);
            end
            `FT_STIM_CMD_IC_TAG_FAULT: begin
               inject_ic_tag_fault(cmd);
            end
            `FT_STIM_CMD_DC_RAM_FAULT: begin
               inject_dc_ram_fault(cmd);
            end
            `FT_STIM_CMD_DC_TAG_FAULT: begin
               inject_dc_tag_fault(cmd);
            end
            `FT_STIM_CMD_DMMU_MR_FAULT: begin
               inject_dmmu_fault(0, cmd);
            end
            `FT_STIM_CMD_DMMU_TR_FAULT: begin
               inject_dmmu_fault(1, cmd);
            end
            `FT_STIM_CMD_IMMU_MR_FAULT: begin
               inject_immu_fault(0, cmd);
            end
            `FT_STIM_CMD_IMMU_TR_FAULT: begin
               inject_immu_fault(1, cmd);
            end
            `FT_STIM_CMD_RF_FAULT: begin
               inject_rf_fault(cmd);
            end
            `FT_STIM_CMD_DEBUG_ON: begin
               $display("%m: Debug on");
               debug_on = 1;
               ack_command;
            end
            `FT_STIM_CMD_DEBUG_OFF: begin
               $display("%m: Debug off");
               debug_on = 0;
               ack_command;
            end
            default:
              begin
                 $display("%m: Unknown command %h",
                          cmd[`FT_STIM_CMD_WORD_CMD_POS]);
                 #10000;
                 $finish;
              end
 
          endcase // case (cmd[`FT_STIM_CMD_WORD_CMD_POS])
 
       end // while (1)
  end // initial begin
 
`endif
endmodule // or1200_ft_stim

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [generic/] [ft/] [bench/] [verilog/] [or1200_ft_stim.v] - Blame information for rev 483

Line No.	Rev	Author	Line
1	483	julius
2
3			`include "timescale.v"
4			`include "or1200_defines.v"
5			`include "orpsoc-testbench-defines.v"
6			`include "test-defines.v"
7
8			`//`
9			`// Top of TB`
10			`//`
11			`define TB_TOP orpsoc_testbench
12
13			`//`
14			`// Top of DUT`
15			`//`
16			`define DUT_TOP `TB_TOP.dut
17
18			`//`
19			`// Top of OR1200 inside test bench`
20			`//`
21			`define OR1200_TOP `DUT_TOP.or1200_top0
22
23
24			`define CPU or1200
25			`define CPU_cpu or1200_cpu
26			`define CPU_rf or1200_rf
27			`define CPU_except or1200_except
28			`define CPU_ctrl or1200_ctrl
29			`define CPU_sprs or1200_sprs
30			`define CPU_ic_top or1200_ic_top
31			`define CPU_ic_ram or1200_ic_ram
32			`define CPU_ic_tag or1200_ic_tag
33			`define CPU_dc_top or1200_dc_top
34			`define CPU_dc_ram or1200_dc_ram
35			`define CPU_dc_tag or1200_dc_tag
36
37			`define CPU_immu_top or1200_immu_top
38			`define CPU_immu_tlb or1200_immu_tlb
39			`define CPU_dmmu_top or1200_dmmu_top
40			`define CPU_dmmu_tlb or1200_dmmu_tlb
41
42			`define CPU_CORE_CLK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk
43
44			`define FT_STIM_MEM_LOC 32'h00000004
45			`define FT_STIM_GO_WORD 32'h88000000
46
47			`module or1200_ft_stim;`
48
49			`reg debug_on;`
50
51
52			`ifdef OR1200_RAM_PARITY
53
54
55
56			`define RAM_WB_TOP `DUT_TOP.ram_wb0.ram_wb_b3_0
57			`task get_ram_word;`
58			`input [31:0] addr;`
59			`output [31:0] insn;`
60			`begin`
61			insn = `RAM_WB_TOP.get_mem32(addr[31:2]);
62			`end`
63			`endtask // get_ram_word`
64
65			`task set_ram_word;`
66			`input [31:0] addr;`
67			`input [31:0] word;`
68			`reg dummy;`
69			`begin`
70			dummy = `RAM_WB_TOP.set_mem32(addr[31:2], word);
71			`end`
72			`endtask // set_ram_word`
73
74
75			`task wait_for_start;`
76			`reg [31:0] mem_word;`
77			`begin`
78			get_ram_word(`FT_STIM_MEM_LOC, mem_word);
79			while(mem_word !== `FT_STIM_GO_WORD)
80			`begin`
81
82			`// if (debug_on)`
83			`// $display("%m: Wait for start, read %h",mem_word);`
84
85			`#100000;`
86			get_ram_word(`FT_STIM_MEM_LOC, mem_word);
87			`end`
88			`end`
89			`endtask // wait_for_start`
90
91			`task get_command;`
92			`output [31:0] out_cmd;`
93
94			`reg [31:0] mem_word;`
95			`begin`
96			get_ram_word(`FT_STIM_MEM_LOC, mem_word);
97			`while(mem_word === 32'h0)`
98			`begin`
99			`#10000;`
100
101			`// if (debug_on)`
102			`// $display("%m: get_command %h",mem_word);`
103
104			get_ram_word(`FT_STIM_MEM_LOC, mem_word);
105			`end`
106			`out_cmd = mem_word;`
107			`end`
108			`endtask // get_command`
109
110			`task ack_command;`
111			`begin`
112			`// if (debug_on)`
113			`// $display("%m: Ack command");`
114			set_ram_word(`FT_STIM_MEM_LOC, 0);
115			`end`
116			`endtask // ack_command`
117
118			`task inject_ic_ram_fault;`
119			`input [31:0] cmd;`
120			`reg [23:0] word_number;`
121			`reg [7:0] bit_number;`
122
123			`begin`
124			`// Get line number from command`
125			`word_number = cmd[15:0];`
126			`bit_number = cmd[23:16];`
127			`if (debug_on)`
128			`$display("%m: inject error into IC RAM word 0x%h, data bit %02d",`
129			`word_number, bit_number);`
130
131			`OR1200_TOP.`CPU_ic_top.`CPU_ic_ram.ic_ram0.gen_parity_err(word_number,
132			`-1,`
133			`bit_number);`
134			`ack_command;`
135			`end`
136			`endtask // inject_ic_ram_fault`
137
138			`task inject_ic_tag_fault;`
139			`input [31:0] cmd;`
140			`reg [23:0] tag_word;`
141			`reg [7:0] bit_number;`
142			`begin`
143			`// Get line number from command`
144			`tag_word = cmd[15:0];`
145			`bit_number = cmd[23:16];`
146			`if (debug_on)`
147			`$display("%m: inject error into IC tag line 0x%h, data bit %02d",`
148			`tag_word, bit_number);`
149
150			`OR1200_TOP.`CPU_ic_top.`CPU_ic_tag.ic_tag0.gen_parity_err(tag_word,
151			`-1,`
152			`bit_number);`
153			`ack_command;`
154			`end`
155			`endtask`
156
157			`task inject_dc_ram_fault;`
158			`input [31:0] cmd;`
159			`reg [23:0] word_number;`
160			`reg [7:0] bit_number;`
161
162			`begin`
163			`// Get line number from command`
164			`word_number = cmd[15:0];`
165			`bit_number = cmd[23:16];`
166			`if (debug_on)`
167			`$display("%m: inject error into DC RAM word 0x%h, data bit %02d",`
168			`word_number, bit_number);`
169
170			`OR1200_TOP.`CPU_dc_top.`CPU_dc_ram.dc_ram0.gen_parity_err(word_number,
171			`bit_number);`
172			`ack_command;`
173			`end`
174			`endtask`
175
176			`task inject_dc_tag_fault;`
177			`input [31:0] cmd;`
178			`reg [23:0] tag_word;`
179			`reg [7:0] bit_number;`
180			`begin`
181			`// Get line number from command`
182			`tag_word = cmd[15:0];`
183			`bit_number =cmd[23:16];`
184			`if (debug_on)`
185			`$display("%m: inject error into DC tag line 0x%h, data bit %02d",`
186			`tag_word, bit_number);`
187
188			`OR1200_TOP.`CPU_dc_top.`CPU_dc_tag.dc_tag0.gen_parity_err(tag_word,
189			`-1,`
190			`bit_number);`
191			`ack_command;`
192			`end`
193			`endtask`
194
195			`task inject_immu_fault;`
196			`input tr;`
197			`input [31:0] cmd;`
198			`reg [23:0] mem_word;`
199			`reg [7:0] bit_number;`
200			`begin`
201			`// Get line number from command`
202			`mem_word = cmd[15:0];`
203			`bit_number =cmd[23:16];`
204			`if (tr)`
205			`begin`
206			`if (debug_on)`
207			`$display("%m: inject error into iTLB TR RAM, 0x%h, bit %02d",`
208			`mem_word, bit_number);`
209
210			`OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_tr_ram.gen_parity_err(
211			`mem_word,`
212			`-1,`
213			`bit_number);`
214			`end`
215			`else`
216			`begin`
217			`if (debug_on)`
218			`$display("%m: inject error into iTLB MR RAM, 0x%h, bit %02d",`
219			`mem_word, bit_number);`
220
221			`OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_mr_ram.gen_parity_err(
222			`mem_word,`
223			`-1,`
224			`bit_number);`
225
226			`end // else: !if(tr)`
227
228			`ack_command;`
229
230			`end`
231			`endtask // inject_immu_fault`
232
233			`task inject_dmmu_fault;`
234			`input tr;`
235			`input [31:0] cmd;`
236			`reg [23:0] mem_word;`
237			`reg [7:0] bit_number;`
238			`begin`
239			`// Get line number from command`
240			`mem_word = cmd[15:0];`
241			`bit_number =cmd[23:16];`
242			`if (tr)`
243			`begin`
244			`if (debug_on)`
245			`$display("%m: inject error into dtlb TR RAM, 0x%h, bit %02d",`
246			`mem_word, bit_number);`
247
248			`OR1200_TOP.`CPU_dmmu_top.`CPU_dmmu_tlb.dtlb_tr_ram.gen_parity_err(
249			`mem_word,`
250			`-1,`
251			`bit_number);`
252			`end`
253			`else`
254			`begin`
255			`if (debug_on)`
256			`$display("%m: inject error into dtlb MR RAM, 0x%h, bit %02d",`
257			`mem_word, bit_number);`
258
259			`OR1200_TOP.`CPU_dmmu_top.`CPU_dmmu_tlb.dtlb_mr_ram.gen_parity_err(
260			`mem_word,`
261			`-1,`
262			`bit_number);`
263
264			`end // else: !if(tr)`
265
266			`ack_command;`
267
268			`end`
269			`endtask`
270
271
272			`task inject_rf_fault;`
273			`input [31:0] cmd;`
274			`reg [23:0] gpr_no;`
275			`reg [7:0] bit_number;`
276			`begin`
277			`bit_number =cmd[23:16];`
278			`gpr_no = cmd[15:0];`
279
280			`if (debug_on)`
281			`$display("%m: inject error into register file, r%02d, bit %02d",`
282			`gpr_no, bit_number);`
283
284			`OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.gen_parity_err( gpr_no,
285			`-1,`
286			`bit_number);`
287			`OR1200_TOP.`CPU_cpu.`CPU_rf.rf_b.gen_parity_err( gpr_no,
288			`-1,`
289			`bit_number);`
290
291			`ack_command;`
292
293			`end`
294			`endtask`
295
296			`reg [31:0] cmd;`
297
298
299			`define FT_STIM_CMD_WORD_CMD_POS 31:24
300			`define FT_STIM_CMD_WORD_CMD_WIDTH 8
301			`define FT_STIM_CMD_WORD_DATA_POS 23:0
302			`define FT_STIM_CMD_WORD_DATA_WIDTH 24
303
304			`define FT_STIM_CMD_IC_RAM_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h1
305			`define FT_STIM_CMD_IC_TAG_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h2
306			`define FT_STIM_CMD_DC_RAM_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h3
307			`define FT_STIM_CMD_DC_TAG_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h4
308
309			`define FT_STIM_CMD_DMMU_MR_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h5
310			`define FT_STIM_CMD_DMMU_TR_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h6
311			`define FT_STIM_CMD_IMMU_MR_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h7
312			`define FT_STIM_CMD_IMMU_TR_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h8
313
314			`define FT_STIM_CMD_RF_FAULT `FT_STIM_CMD_WORD_CMD_WIDTH'h9
315
316			`define FT_STIM_CMD_DEBUG_ON `FT_STIM_CMD_WORD_CMD_WIDTH'hff
317			`define FT_STIM_CMD_DEBUG_OFF `FT_STIM_CMD_WORD_CMD_WIDTH'hfe
318
319
320			`initial`
321			`begin`
322			`#10;`
323
324			`// Disable to begin with`
325			`debug_on = 1;`
326
327			`// Wait for software to indicate the test is ready to run.`
328			`wait_for_start;`
329
330			`// Ack our receipt of start`
331			`ack_command;`
332
333			`while(1)`
334			`begin`
335			`cmd = 32'hdeaddead;`
336
337			`get_command(cmd);`
338
339			case(cmd[`FT_STIM_CMD_WORD_CMD_POS])
340			`FT_STIM_CMD_IC_RAM_FAULT: begin
341			`inject_ic_ram_fault(cmd);`
342			`end`
343			`FT_STIM_CMD_IC_TAG_FAULT: begin
344			`inject_ic_tag_fault(cmd);`
345			`end`
346			`FT_STIM_CMD_DC_RAM_FAULT: begin
347			`inject_dc_ram_fault(cmd);`
348			`end`
349			`FT_STIM_CMD_DC_TAG_FAULT: begin
350			`inject_dc_tag_fault(cmd);`
351			`end`
352			`FT_STIM_CMD_DMMU_MR_FAULT: begin
353			`inject_dmmu_fault(0, cmd);`
354			`end`
355			`FT_STIM_CMD_DMMU_TR_FAULT: begin
356			`inject_dmmu_fault(1, cmd);`
357			`end`
358			`FT_STIM_CMD_IMMU_MR_FAULT: begin
359			`inject_immu_fault(0, cmd);`
360			`end`
361			`FT_STIM_CMD_IMMU_TR_FAULT: begin
362			`inject_immu_fault(1, cmd);`
363			`end`
364			`FT_STIM_CMD_RF_FAULT: begin
365			`inject_rf_fault(cmd);`
366			`end`
367			`FT_STIM_CMD_DEBUG_ON: begin
368			`$display("%m: Debug on");`
369			`debug_on = 1;`
370			`ack_command;`
371			`end`
372			`FT_STIM_CMD_DEBUG_OFF: begin
373			`$display("%m: Debug off");`
374			`debug_on = 0;`
375			`ack_command;`
376			`end`
377			`default:`
378			`begin`
379			`$display("%m: Unknown command %h",`
380			cmd[`FT_STIM_CMD_WORD_CMD_POS]);
381			`#10000;`
382			`$finish;`
383			`end`
384
385			endcase // case (cmd[`FT_STIM_CMD_WORD_CMD_POS])
386
387			`end // while (1)`
388			`end // initial begin`
389
390			`endif
391			`endmodule // or1200_ft_stim`