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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [generic/] [ft/] [bench/] [verilog/] [orpsoc_testbench.v] - Blame information for rev 483

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//////////////////////////////////////////////////////////////////////
///                                                               //// 
/// ORPSoC testbench                                              ////
///                                                               ////
/// Instantiate ORPSoC, monitors, provide stimulus                ////
///                                                               ////
/// Julius Baxter, julius@opencores.org                           ////
///                                                               ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "orpsoc-defines.v"
`include "orpsoc-testbench-defines.v"
`include "test-defines.v"
 
`include "timescale.v"
 
module orpsoc_testbench;
 
   reg clk = 0;
   reg rst_n = 1; // Active LOW
 
   always
     #((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
 
   // Reset, ACTIVE LOW
   initial
     begin
        #1;
        repeat (32) @(negedge clk)
          rst_n <= 1;
        repeat (32) @(negedge clk)
          rst_n <= 0;
        repeat (32) @(negedge clk)
          rst_n <= 1;
     end
 
`include "orpsoc-params.v"
 
`ifdef JTAG_DEBUG
   wire                      tdo_pad_o;
   wire                      tck_pad_i;
   wire                      tms_pad_i;
   wire                      tdi_pad_i;
`endif
`ifdef UART0
   wire                      uart0_stx_pad_o;
   wire                      uart0_srx_pad_i;
`endif
 
   orpsoc_top dut
     (
      .clk_pad_i                        (clk),
`ifdef JTAG_DEBUG
      .tms_pad_i                        (tms_pad_i),
      .tck_pad_i                        (tck_pad_i),
      .tdi_pad_i                        (tdi_pad_i),
      .tdo_pad_o                        (tdo_pad_o),
`endif
`ifdef UART0
      .uart0_stx_pad_o                  (uart0_stx_pad_o),
      .uart0_srx_pad_i                  (uart0_srx_pad_i),
`endif
      .rst_n_pad_i                      (rst_n)
      );
 
   //
   // Instantiate OR1200 monitor
   //
   or1200_monitor monitor();
 
   or1200_ft_stim ft_stim();
 
`ifndef SIM_QUIET
 `define CPU_ic_top or1200_ic_top
 `define CPU_dc_top or1200_dc_top
   wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;
   always @(posedge ic_en)
     $display("Or1200 IC enabled at %t", $time);
 
   wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;
   always @(posedge dc_en)
     $display("Or1200 DC enabled at %t", $time);
`endif
 
 
`ifdef JTAG_DEBUG
 `ifdef VPI_DEBUG
   // Debugging interface
   vpi_debug_module vpi_dbg
     (
      .tms(tms_pad_i),
      .tck(tck_pad_i),
      .tdi(tdi_pad_i),
      .tdo(tdo_pad_o)
      );
 `else
   // If no VPI debugging, tie off JTAG inputs
   assign tdi_pad_i = 1;
   assign tck_pad_i = 0;
   assign tms_pad_i = 1;
 `endif // !`ifdef VPI_DEBUG_ENABLE
`endif //  `ifdef JTAG_DEBUG
 
 
   initial
     begin
`ifndef SIM_QUIET
        $display("\n* Starting simulation of ORPSoC RTL.\n* Test: %s\n",
                 `TEST_NAME_STRING );
`endif
 
`ifdef VCD
 `ifdef VCD_DELAY
        #(`VCD_DELAY);
 `endif
 
        // Delay by x insns
 `ifdef VCD_DELAY_INSNS
        #10; // Delay until after the value becomes valid
        while (monitor.insns < `VCD_DELAY_INSNS)
          @(posedge clk);
 `endif
 
 `ifdef SIMULATOR_MODELSIM
        // Modelsim can GZip VCDs on the fly if given in the suffix
  `define VCD_SUFFIX   ".vcd.gz"
 `else
  `define VCD_SUFFIX   ".vcd"
 `endif
 
`ifndef SIM_QUIET
        $display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
`endif
        $dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
 `ifndef VCD_DEPTH
  `define VCD_DEPTH 0
 `endif
        $dumpvars(`VCD_DEPTH);
`endif
 
   end // initial begin
 
`ifdef END_TIME
   initial begin
      #(`END_TIME);
`ifndef SIM_QUIET
      $display("* Finish simulation due to END_TIME being set at %t", $time);
`endif
      $finish;
   end
`endif
 
`ifdef END_INSNS
   initial begin
      #10
        while (monitor.insns < `END_INSNS)
          @(posedge clk);
 `ifndef SIM_QUIET
      $display("* Finish simulation due to END_INSNS count (%d) reached at %t",
               `END_INSNS, $time);
 `endif
      $finish;
   end
`endif
 
`ifdef UART0
   //   
   // UART0 decoder
   //   
   uart_decoder
     #(
        .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
        )
   uart0_decoder
     (
      .clk(clk),
      .uart_tx(uart0_stx_pad_o)
      );
 
   // UART0 stimulus
   /*
   uart_stim
     #(
        .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
        )
   uart0_stim
     (
      .clk(clk),
      .uart_rx(uart0_srx_pad_i)
      );
    */
   // UART0 is looped back for now
   assign uart0_srx_pad_i = uart0_stx_pad_o;
 
`endif //  `ifdef UART0
 
endmodule // orpsoc_testbench
 
// Local Variables:
// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")
// verilog-library-files:()
// verilog-library-extensions:(".v" ".h")
// End:
 

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [generic/] [ft/] [bench/] [verilog/] [orpsoc_testbench.v] - Blame information for rev 483

Line No.	Rev	Author	Line
1	483	julius	`//////////////////////////////////////////////////////////////////////`
2			`/// ////`
3			`/// ORPSoC testbench ////`
4			`/// ////`
5			`/// Instantiate ORPSoC, monitors, provide stimulus ////`
6			`/// ////`
7			`/// Julius Baxter, julius@opencores.org ////`
8			`/// ////`
9			`//////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer. ////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation; ////`
21			`//// either version 2.1 of the License, or (at your option) any ////`
22			`//// later version. ////`
23			`//// ////`
24			`//// This source is distributed in the hope that it will be ////`
25			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
26			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
27			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
28			`//// details. ////`
29			`//// ////`
30			`//// You should have received a copy of the GNU Lesser General ////`
31			`//// Public License along with this source; if not, download it ////`
32			`//// from http://www.opencores.org/lgpl.shtml ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35
36			`include "orpsoc-defines.v"
37			`include "orpsoc-testbench-defines.v"
38			`include "test-defines.v"
39
40			`include "timescale.v"
41
42			`module orpsoc_testbench;`
43
44			`reg clk = 0;`
45			`reg rst_n = 1; // Active LOW`
46
47			`always`
48			#((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
49
50			`// Reset, ACTIVE LOW`
51			`initial`
52			`begin`
53			`#1;`
54			`repeat (32) @(negedge clk)`
55			`rst_n <= 1;`
56			`repeat (32) @(negedge clk)`
57			`rst_n <= 0;`
58			`repeat (32) @(negedge clk)`
59			`rst_n <= 1;`
60			`end`
61
62			`include "orpsoc-params.v"
63
64			`ifdef JTAG_DEBUG
65			`wire tdo_pad_o;`
66			`wire tck_pad_i;`
67			`wire tms_pad_i;`
68			`wire tdi_pad_i;`
69			`endif
70			`ifdef UART0
71			`wire uart0_stx_pad_o;`
72			`wire uart0_srx_pad_i;`
73			`endif
74
75			`orpsoc_top dut`
76			`(`
77			`.clk_pad_i (clk),`
78			`ifdef JTAG_DEBUG
79			`.tms_pad_i (tms_pad_i),`
80			`.tck_pad_i (tck_pad_i),`
81			`.tdi_pad_i (tdi_pad_i),`
82			`.tdo_pad_o (tdo_pad_o),`
83			`endif
84			`ifdef UART0
85			`.uart0_stx_pad_o (uart0_stx_pad_o),`
86			`.uart0_srx_pad_i (uart0_srx_pad_i),`
87			`endif
88			`.rst_n_pad_i (rst_n)`
89			`);`
90
91			`//`
92			`// Instantiate OR1200 monitor`
93			`//`
94			`or1200_monitor monitor();`
95
96			`or1200_ft_stim ft_stim();`
97
98			`ifndef SIM_QUIET
99			`define CPU_ic_top or1200_ic_top
100			`define CPU_dc_top or1200_dc_top
101			`wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;`
102			`always @(posedge ic_en)`
103			`$display("Or1200 IC enabled at %t", $time);`
104
105			`wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;`
106			`always @(posedge dc_en)`
107			`$display("Or1200 DC enabled at %t", $time);`
108			`endif
109
110
111			`ifdef JTAG_DEBUG
112			`ifdef VPI_DEBUG
113			`// Debugging interface`
114			`vpi_debug_module vpi_dbg`
115			`(`
116			`.tms(tms_pad_i),`
117			`.tck(tck_pad_i),`
118			`.tdi(tdi_pad_i),`
119			`.tdo(tdo_pad_o)`
120			`);`
121			`else
122			`// If no VPI debugging, tie off JTAG inputs`
123			`assign tdi_pad_i = 1;`
124			`assign tck_pad_i = 0;`
125			`assign tms_pad_i = 1;`
126			`endif // !`ifdef VPI_DEBUG_ENABLE
127			`endif // `ifdef JTAG_DEBUG
128
129
130			`initial`
131			`begin`
132			`ifndef SIM_QUIET
133			`$display("\n* Starting simulation of ORPSoC RTL.\n* Test: %s\n",`
134			`TEST_NAME_STRING );
135			`endif
136
137			`ifdef VCD
138			`ifdef VCD_DELAY
139			#(`VCD_DELAY);
140			`endif
141
142			`// Delay by x insns`
143			`ifdef VCD_DELAY_INSNS
144			`#10; // Delay until after the value becomes valid`
145			while (monitor.insns < `VCD_DELAY_INSNS)
146			`@(posedge clk);`
147			`endif
148
149			`ifdef SIMULATOR_MODELSIM
150			`// Modelsim can GZip VCDs on the fly if given in the suffix`
151			`define VCD_SUFFIX ".vcd.gz"
152			`else
153			`define VCD_SUFFIX ".vcd"
154			`endif
155
156			`ifndef SIM_QUIET
157			$display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
158			`endif
159			$dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
160			`ifndef VCD_DEPTH
161			`define VCD_DEPTH 0
162			`endif
163			$dumpvars(`VCD_DEPTH);
164			`endif
165
166			`end // initial begin`
167
168			`ifdef END_TIME
169			`initial begin`
170			#(`END_TIME);
171			`ifndef SIM_QUIET
172			`$display("* Finish simulation due to END_TIME being set at %t", $time);`
173			`endif
174			`$finish;`
175			`end`
176			`endif
177
178			`ifdef END_INSNS
179			`initial begin`
180			`#10`
181			while (monitor.insns < `END_INSNS)
182			`@(posedge clk);`
183			`ifndef SIM_QUIET
184			`$display("* Finish simulation due to END_INSNS count (%d) reached at %t",`
185			`END_INSNS, $time);
186			`endif
187			`$finish;`
188			`end`
189			`endif
190
191			`ifdef UART0
192			`//`
193			`// UART0 decoder`
194			`//`
195			`uart_decoder`
196			`#(`
197			`.uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS`
198			`)`
199			`uart0_decoder`
200			`(`
201			`.clk(clk),`
202			`.uart_tx(uart0_stx_pad_o)`
203			`);`
204
205			`// UART0 stimulus`
206			`/*`
207			`uart_stim`
208			`#(`
209			`.uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS`
210			`)`
211			`uart0_stim`
212			`(`
213			`.clk(clk),`
214			`.uart_rx(uart0_srx_pad_i)`
215			`);`
216			`*/`
217			`// UART0 is looped back for now`
218			`assign uart0_srx_pad_i = uart0_stx_pad_o;`
219
220			`endif // `ifdef UART0
221
222			`endmodule // orpsoc_testbench`
223
224			`// Local Variables:`
225			`// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")`
226			`// verilog-library-files:()`
227			`// verilog-library-extensions:(".v" ".h")`
228			`// End:`
229