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                        OR1200 with Fault Tolerance features

                        ====================================

This technology-independent build tests the OR1200's fault tolerance features,

primarily parity error detection and behavior on its various internal RAMs.

OR1200 fault tolerance features

===============================

The OR1200's parity detection mechanisms are enabled by adding

"`define OR1200_RAM_PARITY" in the or1200_defines.v file.

This enables parity detection logic on the generic technology memory

implementations (to be inerred as block RAMs by FPGA synthesis tools, ASIC flow

will have to provide custom solution) throughout the processor.

The 5 places special control logic is added is in the instruction and data

cache modules, the instruction and data MMU TLB caches, and the register file.

An output vector is added to the top level of the OR1200 to indicate when a

parity error is detected.

The following behavior is exhibited when a parity error is detected in these

locations:

Instruction cache instruction RAM: Cache line refill

Instruction cache tag RAM: Cache line refill

Data cache data RAM: Cache line refill

Data cache tag RAM: Cache line refill

Instruction MMU TLB match register RAM: ITLB miss exception

Instruction MMU TLB translate register RAM: ITLB miss exception

Data MMU TLB match register RAM: DTLB miss exception

Data MMU TLB translate register RAM: DTLB miss exception

Register file: Execution continues, however a parity error in the register

               file is considered unrecoverable, and the OR1200 should be

               reset. This is not done automatically and should be the job

               of an external unit.

Testing System

==============

A special test-bench set up is contained in this testbench. The software test,

or1200ft-parity, communicates with a verilog module via some memory locations

in the main RAM on the Wishbone bus, sending commands which will inject errors

into various RAMs throughout the OR1200. The software then exercises these

areas of the RAM to ensure the parity error is detected.

ORPSoC Configuration

====================

ORPSoC is configured with no peripherals, just bus arbiters, and a 1MB RAM on

the Wishbone bus.

The only additional module is the parity error handler.

Parity Error Handler Module

===========================

This module is in rtl/verilog/parity_err_handler of this build's path.

It takes the wishbone clock, a reset and the OR1200's parity error indicator

vector, and will issue a reset to the OR1200 on detection of a RF parity error,

and assert its interrupt line (to IRQ5 of OR1200's PIC) on detection of any

instruction cache parity errors.

The interrupt is edge-triggered by the incoming parity error indicator vector

but behaves as a level-triggered interrupt source, and reading from it (it is

at address 0xe0000000 on the Wishbone data bus) will clear the pending

interrupt.

It can be configured to reset or interrupt on any incoming parity error vector.

Verilog Testbench Stimulus

==========================

The additional verilog testbench module, or1200_ft_stim, is used to inject

parity errors into specific bits and words of the various RAMs in the design,

to a simulate single event upset (SUE).

The stimulus is controlled by the software test running on the processor. It

(the testbench) polls some unused memory locations in the RAM on the Wishbone

data bus, and communicates via very simple protocol with the processor.

It can inject errors into all cache, MMU TLB and register file memories for

a generic technology configuration.

See the file for more details.

Software Test

=============

The software test configures the various memories to contain useful data before

commanding the verilog or1200_ft_stim module to inject errors there and

accessing them again. See the file sw/tests/or1200ft/or1200ft-parity.c for

exact details.

The software test checks every bit possible in an output word from the cache

and TLB memories,and checks every word and every bit of the register file

memories.

Running The Test

================

To run the fault tolerance test, the Modelsim simulator is used by default,

but to switch back to using Icarus Verilog, run:

 boards/generic/ft/sim/run$ make rtl-test TEST=or1200ft-parity SIMULATOR=icarus

Or to run with Modelsim, remove "SIMULATOR=icarus".