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//////////////////////////////////////////////////////////////////////
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//// ////
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//// orpsoc-params ////
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//// ////
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//// Top level ORPSoC parameters file ////
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//// ////
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//// Included in toplevel and testbench ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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///////////////////////////
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// //
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// Peripheral parameters //
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// //
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///////////////////////////
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// UART 0 params
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parameter wbs_d_uart0_data_width = 8;
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parameter uart0_wb_adr = 8'h90;
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parameter uart0_data_width = 8;
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parameter uart0_addr_width = 3;
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// Parity error unit
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parameter peh_wb_adr = 8'he0;
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// ROM
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parameter wbs_i_rom0_data_width = 32;
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parameter wbs_i_rom0_addr_width = 6;
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parameter rom0_wb_adr = 4'hf;
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//////////////////////////////////////////////////////
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// //
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// Wishbone bus parameters //
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// //
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//////////////////////////////////////////////////////
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////////////////////////
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// //
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// Arbiter parameters //
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// //
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////////////////////////
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parameter wb_dw = 32; // Default Wishbone full word width
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parameter wb_aw = 32; // Default Wishbone full address width
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///////////////////////////
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// //
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// Instruction bus //
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// //
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///////////////////////////
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parameter ibus_arb_addr_match_width = 4;
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// Slave addresses
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parameter ibus_arb_slave0_adr = rom0_wb_adr; // ROM
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parameter ibus_arb_slave1_adr = 4'h0; // Main memory
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///////////////////////////
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// //
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// Data bus //
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// //
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///////////////////////////
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// Has auto foward to last slave when no address hits
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parameter dbus_arb_wb_addr_match_width = 8;
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parameter dbus_arb_wb_num_slaves = 2;
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// Slave addresses
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parameter dbus_arb_slave0_adr = 4'h0; // Main memory (SDRAM/FPGA SRAM)
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parameter dbus_arb_slave1_adr = 8'hxx; // Default slave - address don't care (X)
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///////////////////////////////
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// //
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// Byte-wide peripheral bus //
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// //
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///////////////////////////////
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parameter bbus_arb_wb_addr_match_width = 8;
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parameter bbus_arb_wb_num_slaves = 1; // Update this when changing slaves!
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// Slave addresses
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parameter bbus_arb_slave0_adr = peh_wb_adr;
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parameter bbus_arb_slave1_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave2_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave3_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave4_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave5_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave6_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave7_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave8_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave9_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave10_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave11_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave12_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave13_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave14_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave15_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave16_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave17_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave18_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave19_adr = 0 /* UNASSIGNED */;
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