OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [Makefile.inc] - Blame information for rev 638

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 628 stekern
# Makefile fragment with some variables global to this board board
2
# Expects BOARD_ROOT to be set
3
 
4
FPGA_VENDOR=xilinx
5
FPGA_ARCH=spartan6
6
BOARD_NAME=atlys
7
BOARD=$(FPGA_VENDOR)/$(BOARD_NAME)
8
DESIGN_NAME=orpsoc
9
 
10
# Path down to root of project
11
PROJECT_ROOT=$(BOARD_ROOT)/../../..
12
 
13
SYNTHESIS_TOOL=xst
14
 
15
export BOARD
16
 
17
include $(PROJECT_ROOT)/scripts/make/Makefile-misc.inc
18
include $(PROJECT_ROOT)/scripts/make/Makefile-board-paths.inc
19
include $(PROJECT_ROOT)/scripts/make/Makefile-board-tops.inc
20
include $(PROJECT_ROOT)/scripts/make/Makefile-board-definesparse.inc
21
 
22 638 stekern
# Check that the Xilinx scripts have been sourced
23
ifndef XILINX
24
$(error The XILINX environment variable was not set, \
25
please run: 'source /path/to/xilinx_ise/settings{32|64}.sh')
26 628 stekern
endif
27
 
28
# Backend directories
29
# This one is the board build's backend dir.
30
BOARD_BACKEND_DIR=$(BOARD_ROOT)/backend
31
BOARD_BACKEND_VERILOG_DIR=$(BOARD_BACKEND_DIR)/rtl/verilog
32
BOARD_BACKEND_BIN_DIR=$(BOARD_BACKEND_DIR)/bin
33
# Technology backend (vendor-specific)
34
TECHNOLOGY_BACKEND_DIR=$(BOARD_ROOT)/../backend
35
# This path is for the technology library
36 638 stekern
TECHNOLOGY_LIBRARY_VERILOG_DIR=$(XILINX)/verilog
37 628 stekern
# This path is for the technology binaries
38 638 stekern
TECHNOLOGY_BACKEND_BIN_DIR=$(XILINX)/bin/lin
39 628 stekern
 
40
# Board specific modelsim options
41
VSIM_ARGS= -L secureip
42
VOPT_ARGS= -L secureip
43
 
44
# Xilinx Xlib specific settings
45
DO_XILINX_COMPXLIB=1
46
XLIB_ARGS=-intstyle silent -s mti_se -l all -arch $(FPGA_ARCH) -lib all
47
 
48
# Bootrom setup
49
# BootROM code, which generates a verilog array select values
50
BOOTROM_FILE=bootrom.v
51
BOOTROM_SW_DIR=$(BOARD_SW_DIR)/bootrom
52
BOOTROM_SRC=$(shell ls $(BOOTROM_SW_DIR)/* | grep -v $(BOOTROM_FILE))
53
BOOTROM_VERILOG=$(BOOTROM_SW_DIR)/$(BOOTROM_FILE)
54
 
55
bootrom: $(BOOTROM_VERILOG)
56
 
57
$(BOOTROM_VERILOG): $(BOOTROM_SRC)
58
        $(Q)echo; echo "\t### Generating bootup ROM ###"; echo
59
        $(Q)$(MAKE) -C $(BOOTROM_SW_DIR) $(BOOTROM_FILE)
60
 
61
clean-bootrom:
62
        $(Q)echo; echo "\t### Cleaning bootup ROM ###"; echo
63
        $(Q)$(MAKE) -C $(BOOTROM_SW_DIR) clean
64
 
65
include $(PROJECT_ROOT)/scripts/make/Makefile-board-rtlmodules.inc
66
 
67
# "Backend" source file stuff (PLL, RAM macro models.)
68
BOARD_BACKEND_VERILOG_SRC=$(shell ls $(BOARD_BACKEND_VERILOG_DIR)/*.v )
69
 
70
# Backend tool path
71
 
72
# BACKEND_TECHNOLOGY_VERILOG_SRC should be set if we need to compile specific
73
# libraries, as in the Actel and Altera case, and left empty for Xilinx who
74
# allow us to simply pass the path with the -y option because they have each
75
# bit of the tech library in individual files, and in which case this variable
76
# should be left unset.
77
 
78
# Keep this variable empty
79
BACKEND_TECHNOLOGY_VERILOG_SRC=

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.