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/****************************************************************************************

*

*    File Name:  ddr2_model.v

*      Version:  5.82

*        Model:  BUS Functional

*

* Dependencies:  ddr2_model_parameters.vh

*

*  Description:  Micron SDRAM DDR2 (Double Data Rate 2)

*

*   Limitation:  - doesn't check for average refresh timings

*                - positive ck and ck_n edges are used to form internal clock

*                - positive dqs and dqs_n edges are used to latch data

*                - test mode is not modeled

*

*         Note:  - Set simulator resolution to "ps" accuracy

*                - Set Debug = 0 to disable $display messages

*

*   Disclaimer   This software code and all associated documentation, comments or other

*  of Warranty:  information (collectively "Software") is provided "AS IS" without

*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY

*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED

*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES

*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT

*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE

*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.

*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR

*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,

*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE

*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,

*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,

*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,

*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,

*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE

*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH

*                DAMAGES. Because some jurisdictions prohibit the exclusion or

*                limitation of liability for consequential or incidental damages, the

*                above limitation may not apply to you.

*

*                Copyright 2003 Micron Technology, Inc. All rights reserved.

*

* Rev   Author   Date        Changes

* ---------------------------------------------------------------------------------------

* 1.00  JMK      07/29/03    Initial Release

* 1.10  JMK      08/09/03    Timing Parameter updates to tIS, tIH, tDS, tDH

* 2.20  JMK      08/07/03    General cleanup

* 2.30  JMK      11/26/03    Added CL_MIN, CL_MAX, wl_min and wl_max parameters.

*                            Added AL_MIN and AL_MAX parameters.

*                            Removed support for OCD.

* 2.40  JMK      01/15/04    Removed verilog 2001 constructs.

* 2.50  JMK      01/29/04    Removed tRP checks during Precharge command.

* 2.60  JMK      04/20/04    Fixed tWTR check.

* 2.70  JMK      04/30/04    Added tRFC maximum check.

*                            Combined Self Refresh and Power Down always blocks.

*                            Added Reset Function (CKE LOW Anytime).

* 2.80  JMK      08/19/04    Precharge is treated as NOP when bank is not active.

*                            Added checks for tRAS, tWR, tRTP to any bank during Pre-All.

*                            tRFC maximum violation will only display one time.

* 2.90  JMK      11/05/04    Fixed DQS checking during write.

*                            Fixed false tRFC max assertion during power up and self ref.

*                            Added warning for 200us CKE low time during initialization.

*                            Added -3, -3E, and -37V speed grades to ddr2_parameters.v

* 3.00  JMK      04/22/05    Removed ODT off requirement during power down.

*                            Added tAOND, tAOFD, tANPD, tAXPD, tAONPD, and tAOFPD parameters.

*                            Added ODT status messages.

*                            Updated the initialization sequence.

*                            Disable ODT and CLK pins during self refresh.

*                            Disable cmd and addr pins during power down and self refresh.

* 3.10  JMK      06/07/05    Disable trpa checking if the part does not have 8 banks.

*                            Changed tAXPD message from error to a warning.

*                            Added tDSS checking.

*                            Removed tDQSL checking during tWPRE and tWPST.

*                            Fixed a burst order error during writes.

*                            Renamed parameters file with .vh extension.

* 3.20  JMK      07/18/05    Removed 14 tCK requirement from LMR to READ.

* 3.30  JMK      08/03/05    Added check for interrupting a burst with auto precharge.

* 4.00  JMK      11/21/05    Parameter names all UPPERCASE, signal names all lowercase.

*                            Clock jitter can be tolerated within specification range.

*                            Clock frequency is sampled from the CK pin.

*                            Scaleable up to 64 DQ and 16 DQS bits.

*                            Read data can be randomly skewed using RANDOM_OUT_DELAY.

*                            Parameterized read and write DQS, and read DQ.

*                            Initialization can be bypassed using initialize task.

* 4.10  JMK      11/30/05    Fixed compile errors when `MAX_MEM was defined.

* 4.20  JMK      12/09/05    Fixed memory addressing error when `MAX_MEM was defined.

* 4.30  JMK      02/15/06    Added dummy write to initialization sequence.

*                            Removed tWPST maximum checking.

*                            Rising dqs_n edge latches data when enabled in EMR.

*                            Fixed a sign error in the tJIT(cc) calculation.

* 4.40  JMK      02/16/06    Fixed dummy write when`MAX_MEM was defined.

* 4.50  JMK      02/27/06    Fixed extra tDQSS assertions.

*                            Fixed tRCD and tWTR checking.

*                            Errors entering Power Down or Self Refresh will cause reset.

*                            Ignore dqs_n when disabled in EMR.

* 5.00  JMK      04/24/06    Test stimulus now included from external file (subtest.vh)

*                            Fixed tRFC max assertion during self refresh.

*                            Fixed tANPD checking during Power Down.

*                            Removed dummy write from initialization sequence.

* 5.01  JMK      04/28/06    Fixed Auto Precharge to Load Mode, Refresh and Self Refresh.

*                            Removed Auto Precharge error message during Power Down Enter.

* 5.10  JMK      07/26/06    Created internal clock using ck and ck_n.

*                            RDQS can only be enabled in EMR for x8 configurations.

*                            CAS latency is checked vs frequency when DLL locks.

*                            tMOD changed from tCK units to ns units.

*                            Added 50 Ohm setting for Rtt in EMR.

*                            Improved checking of DQS during writes.

* 5.20  JMK      10/02/06    Fixed DQS checking for interrupting write to write and x16.

* 5.30  JMK      05/25/07    Fixed checking for 0-Z transition on write postamble.

* 5.50  JMK      05/30/08    Renamed ddr2_dimm.v to ddr2_module.v and added SODIMM support.

*                            Added a register delay to ddr2_module.v when RDIMM is defined.

*                            Added multi-chip package model support in ddr2_mcp.v

*                            Added High Temp Self Refresh rate setting in EMRS2[7]

* 5.70  JMK      04/23/09    Updated tRPA definition

*                            Increased internal width to 72 bit DQ bus

* 5.80  SPH      08/12/09    Fixed tRAS maximum violation (only check if bank still open)

* 5.81  SPH      12/08/09    Only check tIH for cmd_addr if CS# LOW

* 5.82  SPH      04/08/10    Correct debug message for SRT in EMR2

* 5.81  SPH      12/08/09    Only check tIH for cmd_addr if CS# LOW

* 5.81  SPH      12/08/09    Only check tIH for cmd_addr if CS# LOW

****************************************************************************************/

// DO NOT CHANGE THE TIMESCALE

// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION

`timescale 1ps / 1ps

module ddr2_model (

    ck,

    ck_n,

    cke,

    cs_n,

    ras_n,

    cas_n,

    we_n,

    dm_rdqs,

    ba,

    addr,

    dq,

    dqs,

    dqs_n,

    rdqs_n,

    odt

);

`include "ddr2_model_parameters.v"

    // text macros

    `define DQ_PER_DQS DQ_BITS/DQS_BITS

    `define BANKS      (1<<BA_BITS)

    `define MAX_BITS   (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)

    `define MAX_SIZE   (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))

    `define MEM_SIZE   (1<<MEM_BITS)

    `define MAX_PIPE   2*(AL_MAX + CL_MAX)

    // Declare Ports

    input   ck;

    input   ck_n;

    input   cke;

    input   cs_n;

    input   ras_n;

    input   cas_n;

    input   we_n;

    inout   [DM_BITS-1:0]   dm_rdqs;

    input   [BA_BITS-1:0]   ba;

    input   [ADDR_BITS-1:0] addr;

    inout   [DQ_BITS-1:0]   dq;

    inout   [DQS_BITS-1:0]  dqs;

    inout   [DQS_BITS-1:0]  dqs_n;

    output  [DQS_BITS-1:0]  rdqs_n;

    input   odt;

    // clock jitter

    real    tck_avg;

    time    tck_sample [TDLLK-1:0];

    time    tch_sample [TDLLK-1:0];

    time    tcl_sample [TDLLK-1:0];

    time    tck_i;

    time    tch_i;

    time    tcl_i;

    real    tch_avg;

    real    tcl_avg;

    time    tm_ck_pos;

    time    tm_ck_neg;

    real    tjit_per_rtime;

    integer tjit_cc_time;

    real    terr_nper_rtime;

    // clock skew

    real    out_delay;

    integer dqsck [DQS_BITS-1:0];

    integer dqsck_min;

    integer dqsck_max;

    integer dqsq_min;

    integer dqsq_max;

    integer seed;

    // Mode Registers

    reg     burst_order;

    reg     [BL_BITS:0] burst_length;

    integer cas_latency;

    integer additive_latency;

    reg     dll_reset;

    reg     dll_locked;

    reg     dll_en;

    integer write_recovery;

    reg     low_power;

    reg     [1:0] odt_rtt;

    reg     odt_en;

    reg     [2:0] ocd;

    reg     dqs_n_en;

    reg     rdqs_en;

    reg     out_en;

    integer read_latency;

    integer write_latency;

    // cmd encoding

    parameter

        LOAD_MODE = 4'b0000,

        REFRESH   = 4'b0001,

        PRECHARGE = 4'b0010,

        ACTIVATE  = 4'b0011,

        WRITE     = 4'b0100,

        READ      = 4'b0101,

        NOP       = 4'b0111,

        PWR_DOWN  = 4'b1000,

        SELF_REF  = 4'b1001

    ;

    reg [8*9-1:0] cmd_string [9:0];

    initial begin

        cmd_string[LOAD_MODE] = "Load Mode";

        cmd_string[REFRESH  ] = "Refresh  ";

        cmd_string[PRECHARGE] = "Precharge";

        cmd_string[ACTIVATE ] = "Activate ";

        cmd_string[WRITE    ] = "Write    ";

        cmd_string[READ     ] = "Read     ";

        cmd_string[NOP      ] = "No Op    ";

        cmd_string[PWR_DOWN ] = "Pwr Down ";

        cmd_string[SELF_REF ] = "Self Ref ";

    end

    // command state

    reg     [`BANKS-1:0] active_bank;

    reg     [`BANKS-1:0] auto_precharge_bank;

    reg     [`BANKS-1:0] write_precharge_bank;

    reg     [`BANKS-1:0] read_precharge_bank;

    reg     [ROW_BITS-1:0] active_row [`BANKS-1:0];

    reg     in_power_down;

    reg     in_self_refresh;

    reg     [3:0] init_mode_reg;

    reg     init_done;

    integer init_step;

    reg     er_trfc_max;

    reg     odt_state;

    reg     prev_odt;

    // cmd timers/counters

    integer ref_cntr;

    integer ck_cntr;

    integer ck_load_mode;

    integer ck_write;

    integer ck_read;

    integer ck_write_ap;

    integer ck_power_down;

    integer ck_slow_exit_pd;

    integer ck_self_refresh;

    integer ck_cke;

    integer ck_odt;

    integer ck_dll_reset;

    integer ck_bank_write     [`BANKS-1:0];

    integer ck_bank_read      [`BANKS-1:0];

    time    tm_refresh;

    time    tm_precharge;

    time    tm_precharge_all;

    time    tm_activate;

    time    tm_write_end;

    time    tm_self_refresh;

    time    tm_odt_en;

    time    tm_bank_precharge [`BANKS-1:0];

    time    tm_bank_activate  [`BANKS-1:0];

    time    tm_bank_write_end [`BANKS-1:0];

    time    tm_bank_read_end  [`BANKS-1:0];

    // pipelines

    reg     [`MAX_PIPE:0]   al_pipeline;

    reg     [`MAX_PIPE:0]   wr_pipeline;

    reg     [`MAX_PIPE:0]   rd_pipeline;

    reg     [`MAX_PIPE:0]   odt_pipeline;

    reg     [BA_BITS-1:0]   ba_pipeline  [`MAX_PIPE:0];

    reg     [ROW_BITS-1:0]  row_pipeline [`MAX_PIPE:0];

    reg     [COL_BITS-1:0]  col_pipeline [`MAX_PIPE:0];

    reg     prev_cke;

    // data state

    reg     [BL_MAX*DQ_BITS-1:0] memory_data;

    reg     [BL_MAX*DQ_BITS-1:0] bit_mask;

    reg     [BL_BITS-1:0]        burst_position;

    reg     [BL_BITS:0]          burst_cntr;

    reg     [DQ_BITS-1:0]        dq_temp;

    reg     [35:0] check_write_postamble;

    reg     [35:0] check_write_preamble;

    reg     [35:0] check_write_dqs_high;

    reg     [35:0] check_write_dqs_low;

    reg     [17:0] check_dm_tdipw;

    reg     [71:0] check_dq_tdipw;

    // data timers/counters

    time    tm_cke;

    time    tm_odt;

    time    tm_tdqss;

    time    tm_dm        [17:0];

    time    tm_dqs       [17:0];

    time    tm_dqs_pos   [35:0];

    time    tm_dqss_pos  [35:0];

    time    tm_dqs_neg   [35:0];

    time    tm_dq        [71:0];

    time    tm_cmd_addr  [22:0];

    reg [8*7-1:0] cmd_addr_string [22:0];

    initial begin

        cmd_addr_string[ 0] = "CS_N   ";

        cmd_addr_string[ 1] = "RAS_N  ";

        cmd_addr_string[ 2] = "CAS_N  ";

        cmd_addr_string[ 3] = "WE_N   ";

        cmd_addr_string[ 4] = "BA 0   ";

        cmd_addr_string[ 5] = "BA 1   ";

        cmd_addr_string[ 6] = "BA 2   ";

        cmd_addr_string[ 7] = "ADDR  0";

        cmd_addr_string[ 8] = "ADDR  1";

        cmd_addr_string[ 9] = "ADDR  2";

        cmd_addr_string[10] = "ADDR  3";

        cmd_addr_string[11] = "ADDR  4";

        cmd_addr_string[12] = "ADDR  5";

        cmd_addr_string[13] = "ADDR  6";

        cmd_addr_string[14] = "ADDR  7";

        cmd_addr_string[15] = "ADDR  8";

        cmd_addr_string[16] = "ADDR  9";

        cmd_addr_string[17] = "ADDR 10";

        cmd_addr_string[18] = "ADDR 11";

        cmd_addr_string[19] = "ADDR 12";

        cmd_addr_string[20] = "ADDR 13";

        cmd_addr_string[21] = "ADDR 14";

        cmd_addr_string[22] = "ADDR 15";

    end

    reg [8*5-1:0] dqs_string [1:0];

    initial begin

        dqs_string[0] = "DQS  ";

        dqs_string[1] = "DQS_N";

    end

    // Memory Storage

`ifdef MAX_MEM

    reg     [BL_MAX*DQ_BITS-1:0] memory  [0:`MAX_SIZE-1];

`else

    reg     [BL_MAX*DQ_BITS-1:0] memory  [0:`MEM_SIZE-1];

    reg     [`MAX_BITS-1:0]      address [0:`MEM_SIZE-1];

    reg     [MEM_BITS:0]         memory_index;

    reg     [MEM_BITS:0]         memory_used;

`endif

    // receive

    reg            ck_in;

    reg            ck_n_in;

    reg            cke_in;

    reg            cs_n_in;

    reg            ras_n_in;

    reg            cas_n_in;

    reg            we_n_in;

    reg     [17:0] dm_in;

    reg     [2:0]  ba_in;

    reg     [15:0] addr_in;

    reg     [71:0] dq_in;

    reg     [35:0] dqs_in;

    reg            odt_in;

    reg     [17:0] dm_in_pos;

    reg     [17:0] dm_in_neg;

    reg     [71:0] dq_in_pos;

    reg     [71:0] dq_in_neg;

    reg            dq_in_valid;

    reg            dqs_in_valid;

    integer        wdqs_cntr;

    integer        wdq_cntr;

    integer        wdqs_pos_cntr [35:0];

    reg            b2b_write;

    reg     [35:0] prev_dqs_in;

    reg            diff_ck;

    always @(ck     ) ck_in     <= #BUS_DELAY ck;

    always @(ck_n   ) ck_n_in   <= #BUS_DELAY ck_n;

    always @(cke    ) cke_in    <= #BUS_DELAY cke;

    always @(cs_n   ) cs_n_in   <= #BUS_DELAY cs_n;

    always @(ras_n  ) ras_n_in  <= #BUS_DELAY ras_n;

    always @(cas_n  ) cas_n_in  <= #BUS_DELAY cas_n;

    always @(we_n   ) we_n_in   <= #BUS_DELAY we_n;

    always @(dm_rdqs) dm_in     <= #BUS_DELAY dm_rdqs;

    always @(ba     ) ba_in     <= #BUS_DELAY ba;

    always @(addr   ) addr_in   <= #BUS_DELAY addr;

    always @(dq     ) dq_in     <= #BUS_DELAY dq;

    always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<18) | dqs;

    always @(odt    ) odt_in    <= #BUS_DELAY odt;

    // create internal clock

    always @(posedge ck_in)   diff_ck <= ck_in;

    always @(posedge ck_n_in) diff_ck <= ~ck_n_in;

    wire    [17:0] dqs_even = dqs_in[17:0];

    wire    [17:0] dqs_odd  = dqs_n_en ? dqs_in[35:18] : ~dqs_in[17:0];

    wire    [3:0]  cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP;  //deselect = nop 

    // transmit

    reg                    dqs_out_en;

    reg     [DQS_BITS-1:0] dqs_out_en_dly;

    reg                    dqs_out;

    reg     [DQS_BITS-1:0] dqs_out_dly;

    reg                    dq_out_en;

    reg     [DQ_BITS-1:0]  dq_out_en_dly;

    reg     [DQ_BITS-1:0]  dq_out;

    reg     [DQ_BITS-1:0]  dq_out_dly;

    integer                rdqsen_cntr;

    integer                rdqs_cntr;

    integer                rdqen_cntr;

    integer                rdq_cntr;

    bufif1 buf_dqs    [DQS_BITS-1:0] (dqs,     dqs_out_dly,  dqs_out_en_dly & {DQS_BITS{out_en}});

    bufif1 buf_dm     [DM_BITS-1:0]  (dm_rdqs, dqs_out_dly,  dqs_out_en_dly & {DM_BITS {out_en}} & {DM_BITS{rdqs_en}});

    bufif1 buf_dqs_n  [DQS_BITS-1:0] (dqs_n,   ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}});

    bufif1 buf_rdqs_n [DQS_BITS-1:0] (rdqs_n,  ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}} & {DQS_BITS{rdqs_en}});

    bufif1 buf_dq     [DQ_BITS-1:0]  (dq,      dq_out_dly,   dq_out_en_dly  & {DQ_BITS {out_en}});

    initial begin

        if (BL_MAX < 2)

            $display("%m ERROR: BL_MAX parameter must be >= 2.  \nBL_MAX = %d", BL_MAX);

        if ((1<<BO_BITS) > BL_MAX)

            $display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");

        $timeformat (-12, 1, " ps", 1);

        reset_task;

        seed = RANDOM_SEED;

        ck_cntr = 0;

    end

    // calculate the absolute value of a real number

    function real abs_value;

    input arg;

    real arg;

    begin

        if (arg < 0.0)

            abs_value = -1.0 * arg;

        else

            abs_value = arg;

    end

    endfunction

`ifdef MAX_MEM

`else

    function get_index;

        input [`MAX_BITS-1:0] addr;

        begin : index

            get_index = 0;

            for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin

                if (address[memory_index] == addr) begin

                    get_index = 1;

                    disable index;

                end

            end

        end

    endfunction

`endif

    task memory_write;

        input  [BA_BITS-1:0]  bank;

        input  [ROW_BITS-1:0] row;

        input  [COL_BITS-1:0] col;

        input  [BL_MAX*DQ_BITS-1:0] data;

        reg    [`MAX_BITS-1:0] addr;

        begin

            // chop off the lowest address bits

            addr = {bank, row, col}/BL_MAX;

`ifdef MAX_MEM

            memory[addr] = data;

`else

            if (get_index(addr)) begin

                address[memory_index] = addr;

                memory[memory_index] = data;

            end else if (memory_used == `MEM_SIZE) begin

                $display ("%m: at time %t ERROR: Memory overflow.  Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);

                if (STOP_ON_ERROR) $stop(0);

            end else begin

                address[memory_used] = addr;

                memory[memory_used] = data;

                memory_used = memory_used + 1;

            end

`endif

        end

    endtask

    task memory_read;

        input  [BA_BITS-1:0]  bank;

        input  [ROW_BITS-1:0] row;

        input  [COL_BITS-1:0] col;

        output [BL_MAX*DQ_BITS-1:0] data;

        reg    [`MAX_BITS-1:0] addr;

        begin

            // chop off the lowest address bits

            addr = {bank, row, col}/BL_MAX;

`ifdef MAX_MEM

            data = memory[addr];

`else

            if (get_index(addr)) begin

                data = memory[memory_index];

            end else begin

                data = {BL_MAX*DQ_BITS{1'bx}};

            end

`endif

        end

    endtask

    // Before this task runs, the model must be in a valid state for precharge power down.

    // After this task runs, NOP commands must be issued until tRFC has been met

    task initialize;

        input [ADDR_BITS-1:0] mode_reg0;

        input [ADDR_BITS-1:0] mode_reg1;

        input [ADDR_BITS-1:0] mode_reg2;

        input [ADDR_BITS-1:0] mode_reg3;

        begin

            if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);

            cmd_task(1,       NOP, 'bx, 'bx);

            cmd_task(1, PRECHARGE, 'bx, 1<<AP);           // Precharege ALL

            cmd_task(1, LOAD_MODE, 3, mode_reg3);

            cmd_task(1, LOAD_MODE, 2, mode_reg2);

            cmd_task(1, LOAD_MODE, 1, mode_reg1);

            cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset

            cmd_task(1, PRECHARGE, 'bx, 1<<AP);           // Precharege ALL

            cmd_task(1,   REFRESH, 'bx, 'bx);

            cmd_task(1,   REFRESH, 'bx, 'bx);

            cmd_task(1, LOAD_MODE, 0, mode_reg0);

            cmd_task(1, LOAD_MODE, 1, mode_reg1 | 'h380); // OCD Default

            cmd_task(1, LOAD_MODE, 1, mode_reg1);

            cmd_task(0,       NOP, 'bx, 'bx);

        end

    endtask

    task reset_task;

        integer i;

        begin

            // disable inputs

            dq_in_valid          = 0;

            dqs_in_valid        <= 0;

            wdqs_cntr            = 0;

            wdq_cntr             = 0;

            for (i=0; i<36; i=i+1) begin

                wdqs_pos_cntr[i]    <= 0;

            end

            b2b_write           <= 0;

            // disable outputs

            out_en               = 0;

            dqs_n_en             = 0;

            rdqs_en              = 0;

            dq_out_en            = 0;

            rdq_cntr             = 0;

            dqs_out_en           = 0;

            rdqs_cntr            = 0;

            // disable ODT

            odt_en               = 0;

            odt_state            = 0;

            // reset bank state

            active_bank          = {`BANKS{1'b1}};

            auto_precharge_bank  = 0;

                read_precharge_bank  = 0;

                write_precharge_bank = 0;

            // require initialization sequence

            init_done            = 0;

            init_step            = 0;

            init_mode_reg        = 0;

            // reset DLL

            dll_en               = 0;

            dll_reset            = 0;

            dll_locked           = 0;

            ocd                  = 0;

            // exit power down and self refresh

            in_power_down        = 0;

            in_self_refresh      = 0;

            // clear pipelines

            al_pipeline          = 0;

            wr_pipeline          = 0;

            rd_pipeline          = 0;

            odt_pipeline         = 0;

            // clear memory

`ifdef MAX_MEM

            for (i=0; i<=`MAX_SIZE; i=i+1) begin //erase memory ... one address at a time

                memory[i] <= 'bx;

            end

`else

            memory_used <= 0; //erase memory

`endif

            // clear maximum timing checks

            tm_refresh <= 'bx;

            for (i=0; i<`BANKS; i=i+1) begin

                tm_bank_activate[i] <= 'bx;

            end

        end

    endtask

    task chk_err;

        input samebank;

        input [BA_BITS-1:0] bank;

        input [3:0] fromcmd;

        input [3:0] cmd;

        reg err;

    begin

        // all matching case expressions will be evaluated

        casex ({samebank, fromcmd, cmd})

            {1'b0, LOAD_MODE, 4'b0xxx  } : begin if (ck_cntr - ck_load_mode < TMRD)                                                                                       $display ("%m: at time %t ERROR:  tMRD violation during %s", $time, cmd_string[cmd]);                         end

            {1'b0, LOAD_MODE, 4'b100x  } : begin if (ck_cntr - ck_load_mode < TMRD)                                                                                 begin $display ("%m: at time %t INFO: Load Mode to Reset condition.", $time);                    init_done = 0; end end

            {1'b0, REFRESH  , 4'b0xxx  } : begin if ($time - tm_refresh < TRFC_MIN)                                                                                       $display ("%m: at time %t ERROR:  tRFC violation during %s", $time, cmd_string[cmd]);                         end

            {1'b0, REFRESH  , PWR_DOWN } : ; // 1 tCK

            {1'b0, REFRESH  , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN)                                                                                 begin $display ("%m: at time %t INFO: Refresh to Reset condition", $time);                       init_done = 0; end end

            {1'b0, PRECHARGE, 4'b000x  } : begin if ($time - tm_precharge_all < TRPA)                                                                                     $display ("%m: at time %t ERROR:  tRPA violation during %s", $time, cmd_string[cmd]);

                                                 if ($time - tm_precharge < TRP)                                                                                          $display ("%m: at time %t ERROR:   tRP violation during %s", $time, cmd_string[cmd]);                         end

            {1'b1, PRECHARGE, PRECHARGE} : begin if (DEBUG && ($time - tm_precharge_all < TRPA))                                                                          $display ("%m: at time %t INFO: Precharge All interruption during %s", $time, cmd_string[cmd]);