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/****************************************************************************************
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*
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* Disclaimer This software code and all associated documentation, comments or other
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* of Warranty: information (collectively "Software") is provided "AS IS" without
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* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGES. Because some jurisdictions prohibit the exclusion or
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* limitation of liability for consequential or incidental damages, the
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* above limitation may not apply to you.
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*
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* Copyright 2003 Micron Technology, Inc. All rights reserved.
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*
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****************************************************************************************/
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// Timing parameters based on Speed Grade
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// SYMBOL UNITS DESCRIPTION
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// ------ ----- -----------
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`define x1Gb
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`define x16
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`define sg25E
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`ifdef x256Mb
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`ifdef sg187E
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parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
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parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
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parameter TJIT_DUTY = 75; // tJIT(duty) ps Half Period Jitter
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parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
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parameter TERR_2PER = 132; // tERR(nper) ps Accumulated Error (2-cycle)
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parameter TERR_3PER = 157; // tERR(nper) ps Accumulated Error (3-cycle)
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parameter TERR_4PER = 175; // tERR(nper) ps Accumulated Error (4-cycle)
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parameter TERR_5PER = 188; // tERR(nper) ps Accumulated Error (5-cycle)
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parameter TERR_N1PER = 250; // tERR(nper) ps Accumulated Error (6-10-cycle)
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parameter TERR_N2PER = 425; // tERR(nper) ps Accumulated Error (11-50-cycle)
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parameter TQHS = 250; // tQHS ps Data hold skew factor
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parameter TAC = 350; // tAC ps DQ output access time from CK/CK#
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parameter TDS = 0; // tDS ps DQ and DM input setup time relative to DQS
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parameter TDH = 75; // tDH ps DQ and DM input hold time relative to DQS
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parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK#
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parameter TDQSQ = 175; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
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parameter TIS = 125; // tIS ps Input Setup Time
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parameter TIH = 200; // tIH ps Input Hold Time
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parameter TRC = 54000; // tRC ps Active to Active/Auto Refresh command time
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parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
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parameter TWTR = 7500; // tWTR ps Write to Read command delay
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parameter TRP = 13125; // tRP ps Precharge command period
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parameter TRPA = 13125; // tRPA ps Precharge All period
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parameter TXARDS = 10; // tXARDS tCK Exit low power active power down to a read command
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parameter TXARD = 3; // tXARD tCK Exit active power down to a read command
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parameter TXP = 3; // tXP tCK Exit power down to a non-read command
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parameter TANPD = 4; // tANPD tCK ODT to power-down entry latency
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parameter TAXPD = 11; // tAXPD tCK ODT power-down exit latency
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parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
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`else `ifdef sg25E
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parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
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parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
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parameter TJIT_DUTY = 100; // tJIT(duty) ps Half Period Jitter
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parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
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parameter TERR_2PER = 150; // tERR(nper) ps Accumulated Error (2-cycle)
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parameter TERR_3PER = 175; // tERR(nper) ps Accumulated Error (3-cycle)
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parameter TERR_4PER = 200; // tERR(nper) ps Accumulated Error (4-cycle)
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parameter TERR_5PER = 200; // tERR(nper) ps Accumulated Error (5-cycle)
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parameter TERR_N1PER = 300; // tERR(nper) ps Accumulated Error (6-10-cycle)
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parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
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parameter TQHS = 300; // tQHS ps Data hold skew factor
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parameter TAC = 400; // tAC ps DQ output access time from CK/CK#
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parameter TDS = 50; // tDS ps DQ and DM input setup time relative to DQS
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parameter TDH = 125; // tDH ps DQ and DM input hold time relative to DQS
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parameter TDQSCK = 350; // tDQSCK ps DQS output access time from CK/CK#
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parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
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parameter TIS = 175; // tIS ps Input Setup Time
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parameter TIH = 250; // tIH ps Input Hold Time
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parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
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parameter TRCD = 12500; // tRCD ps Active to Read/Write command time
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parameter TWTR = 7500; // tWTR ps Write to Read command delay
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parameter TRP = 12500; // tRP ps Precharge command period
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parameter TRPA = 12500; // tRPA ps Precharge All period
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parameter TXARDS = 8; // tXARDS tCK Exit low power active power down to a read command
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parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
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parameter TXP = 2; // tXP tCK Exit power down to a non-read command
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parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
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parameter TAXPD = 10; // tAXPD tCK ODT power-down exit latency
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parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
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`else `ifdef sg25
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parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
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parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
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parameter TJIT_DUTY = 100; // tJIT(duty) ps Half Period Jitter
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parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
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parameter TERR_2PER = 150; // tERR(nper) ps Accumulated Error (2-cycle)
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parameter TERR_3PER = 175; // tERR(nper) ps Accumulated Error (3-cycle)
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parameter TERR_4PER = 200; // tERR(nper) ps Accumulated Error (4-cycle)
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parameter TERR_5PER = 200; // tERR(nper) ps Accumulated Error (5-cycle)
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parameter TERR_N1PER = 300; // tERR(nper) ps Accumulated Error (6-10-cycle)
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parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
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parameter TQHS = 300; // tQHS ps Data hold skew factor
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parameter TAC = 400; // tAC ps DQ output access time from CK/CK#
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parameter TDS = 50; // tDS ps DQ and DM input setup time relative to DQS
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parameter TDH = 125; // tDH ps DQ and DM input hold time relative to DQS
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parameter TDQSCK = 350; // tDQSCK ps DQS output access time from CK/CK#
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parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
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parameter TIS = 175; // tIS ps Input Setup Time
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parameter TIH = 250; // tIH ps Input Hold Time
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parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
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parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
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parameter TWTR = 7500; // tWTR ps Write to Read command delay
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parameter TRP = 15000; // tRP ps Precharge command period
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parameter TRPA = 15000; // tRPA ps Precharge All period
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parameter TXARDS = 8; // tXARDS tCK Exit low power active power down to a read command
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parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
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parameter TXP = 2; // tXP tCK Exit power down to a non-read command
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parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
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parameter TAXPD = 10; // tAXPD tCK ODT power-down exit latency
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parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
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`else `ifdef sg3E
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parameter TCK_MIN = 3000; // tCK ps Minimum Clock Cycle Time
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parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
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parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
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parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
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parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
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parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
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parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
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parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
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parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
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parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
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parameter TQHS = 340; // tQHS ps Data hold skew factor
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parameter TAC = 450; // tAC ps DQ output access time from CK/CK#
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parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
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parameter TDH = 175; // tDH ps DQ and DM input hold time relative to DQS
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parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
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parameter TDQSQ = 240; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
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parameter TIS = 200; // tIS ps Input Setup Time
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parameter TIH = 275; // tIH ps Input Hold Time
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parameter TRC = 54000; // tRC ps Active to Active/Auto Refresh command time
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parameter TRCD = 12000; // tRCD ps Active to Read/Write command time
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parameter TWTR = 7500; // tWTR ps Write to Read command delay
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parameter TRP = 12000; // tRP ps Precharge command period
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parameter TRPA = 12000; // tRPA ps Precharge All period
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parameter TXARDS = 7; // tXARDS tCK Exit low power active power down to a read command
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parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
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parameter TXP = 2; // tXP tCK Exit power down to a non-read command
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parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
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parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
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parameter CL_TIME = 12000; // CL ps Minimum CAS Latency
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`else `ifdef sg3
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parameter TCK_MIN = 3000; // tCK ps Minimum Clock Cycle Time
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parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
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parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
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parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
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parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
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parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
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parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
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parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
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parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
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parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
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parameter TQHS = 340; // tQHS ps Data hold skew factor
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parameter TAC = 450; // tAC ps DQ output access time from CK/CK#
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parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
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parameter TDH = 175; // tDH ps DQ and DM input hold time relative to DQS
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parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
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parameter TDQSQ = 240; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
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parameter TIS = 200; // tIS ps Input Setup Time
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parameter TIH = 275; // tIH ps Input Hold Time
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parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
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parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
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parameter TWTR = 7500; // tWTR ps Write to Read command delay
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parameter TRP = 15000; // tRP ps Precharge command period
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parameter TRPA = 15000; // tRPA ps Precharge All period
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parameter TXARDS = 7; // tXARDS tCK Exit low power active power down to a read command
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parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
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parameter TXP = 2; // tXP tCK Exit power down to a non-read command
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parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
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parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
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parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
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`else `ifdef sg37E
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parameter TCK_MIN = 3750; // tCK ps Minimum Clock Cycle Time
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parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
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parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
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parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
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parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
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parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
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parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
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parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
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parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
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parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
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parameter TQHS = 400; // tQHS ps Data hold skew factor
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parameter TAC = 500; // tAC ps DQ output access time from CK/CK#
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parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
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parameter TDH = 225; // tDH ps DQ and DM input hold time relative to DQS
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parameter TDQSCK = 450; // tDQSCK ps DQS output access time from CK/CK#
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parameter TDQSQ = 300; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
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parameter TIS = 250; // tIS ps Input Setup Time
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parameter TIH = 375; // tIH ps Input Hold Time
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parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
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parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
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parameter TWTR = 7500; // tWTR ps Write to Read command delay
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parameter TRP = 15000; // tRP ps Precharge command period
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parameter TRPA = 15000; // tRPA ps Precharge All period
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parameter TXARDS = 6; // tXARDS tCK Exit low power active power down to a read command
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parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
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parameter TXP = 2; // tXP tCK Exit power down to a non-read command
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parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
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parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
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parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
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`else `define sg5E
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parameter TCK_MIN = 5000; // tCK ps Minimum Clock Cycle Time
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parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
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| 221 |
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parameter TJIT_DUTY = 150; // tJIT(duty) ps Half Period Jitter
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| 222 |
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parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
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| 223 |
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parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
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| 224 |
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parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
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| 225 |
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parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
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| 226 |
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parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
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| 227 |
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parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
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| 228 |
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parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
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| 229 |
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parameter TQHS = 450; // tQHS ps Data hold skew factor
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| 230 |
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parameter TAC = 600; // tAC ps DQ output access time from CK/CK#
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| 231 |
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parameter TDS = 150; // tDS ps DQ and DM input setup time relative to DQS
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| 232 |
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parameter TDH = 275; // tDH ps DQ and DM input hold time relative to DQS
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| 233 |
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parameter TDQSCK = 500; // tDQSCK ps DQS output access time from CK/CK#
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| 234 |
|
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parameter TDQSQ = 350; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 235 |
|
|
parameter TIS = 350; // tIS ps Input Setup Time
|
| 236 |
|
|
parameter TIH = 475; // tIH ps Input Hold Time
|
| 237 |
|
|
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
| 238 |
|
|
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
| 239 |
|
|
parameter TWTR = 10000; // tWTR ps Write to Read command delay
|
| 240 |
|
|
parameter TRP = 15000; // tRP ps Precharge command period
|
| 241 |
|
|
parameter TRPA = 15000; // tRPA ps Precharge All period
|
| 242 |
|
|
parameter TXARDS = 6; // tXARDS tCK Exit low power active power down to a read command
|
| 243 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 244 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 245 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 246 |
|
|
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
| 247 |
|
|
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
| 248 |
|
|
`endif `endif `endif `endif `endif `endif
|
| 249 |
|
|
|
| 250 |
|
|
`ifdef x16
|
| 251 |
|
|
`ifdef sg187E
|
| 252 |
|
|
parameter TFAW = 45000; // tFAW ps Four Bank Activate window
|
| 253 |
|
|
`else `ifdef sg25E
|
| 254 |
|
|
parameter TFAW = 45000; // tFAW ps Four Bank Activate window
|
| 255 |
|
|
`else `ifdef sg25
|
| 256 |
|
|
parameter TFAW = 45000; // tFAW ps Four Bank Activate window
|
| 257 |
|
|
`else // sg3E, sg3, sg37E, sg5E
|
| 258 |
|
|
parameter TFAW = 50000; // tFAW ps Four Bank Activate window
|
| 259 |
|
|
`endif `endif `endif
|
| 260 |
|
|
`else // x4, x8
|
| 261 |
|
|
`ifdef sg187E
|
| 262 |
|
|
parameter TFAW = 35000; // tFAW ps Four Bank Activate window
|
| 263 |
|
|
`else `ifdef sg25E
|
| 264 |
|
|
parameter TFAW = 35000; // tFAW ps Four Bank Activate window
|
| 265 |
|
|
`else `ifdef sg25
|
| 266 |
|
|
parameter TFAW = 35000; // tFAW ps Four Bank Activate window
|
| 267 |
|
|
`else // sg3E, sg3, sg37E, sg5E
|
| 268 |
|
|
parameter TFAW = 37500; // tFAW ps Four Bank Activate window
|
| 269 |
|
|
`endif `endif `endif
|
| 270 |
|
|
`endif
|
| 271 |
|
|
|
| 272 |
|
|
// Timing Parameters
|
| 273 |
|
|
|
| 274 |
|
|
// Mode Register
|
| 275 |
|
|
parameter AL_MIN = 0; // AL tCK Minimum Additive Latency
|
| 276 |
|
|
parameter AL_MAX = 6; // AL tCK Maximum Additive Latency
|
| 277 |
|
|
parameter CL_MIN = 3; // CL tCK Minimum CAS Latency
|
| 278 |
|
|
parameter CL_MAX = 7; // CL tCK Maximum CAS Latency
|
| 279 |
|
|
parameter WR_MIN = 2; // WR tCK Minimum Write Recovery
|
| 280 |
|
|
parameter WR_MAX = 8; // WR tCK Maximum Write Recovery
|
| 281 |
|
|
parameter BL_MIN = 4; // BL tCK Minimum Burst Length
|
| 282 |
|
|
parameter BL_MAX = 8; // BL tCK Minimum Burst Length
|
| 283 |
|
|
// Clock
|
| 284 |
|
|
parameter TCK_MAX = 8000; // tCK ps Maximum Clock Cycle Time
|
| 285 |
|
|
parameter TCH_MIN = 0.48; // tCH tCK Minimum Clock High-Level Pulse Width
|
| 286 |
|
|
parameter TCH_MAX = 0.52; // tCH tCK Maximum Clock High-Level Pulse Width
|
| 287 |
|
|
parameter TCL_MIN = 0.48; // tCL tCK Minimum Clock Low-Level Pulse Width
|
| 288 |
|
|
parameter TCL_MAX = 0.52; // tCL tCK Maximum Clock Low-Level Pulse Width
|
| 289 |
|
|
// Data
|
| 290 |
|
|
parameter TLZ = TAC; // tLZ ps Data-out low-impedance window from CK/CK#
|
| 291 |
|
|
parameter THZ = TAC; // tHZ ps Data-out high impedance window from CK/CK#
|
| 292 |
|
|
parameter TDIPW = 0.35; // tDIPW tCK DQ and DM input Pulse Width
|
| 293 |
|
|
// Data Strobe
|
| 294 |
|
|
parameter TDQSH = 0.35; // tDQSH tCK DQS input High Pulse Width
|
| 295 |
|
|
parameter TDQSL = 0.35; // tDQSL tCK DQS input Low Pulse Width
|
| 296 |
|
|
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
|
| 297 |
|
|
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
|
| 298 |
|
|
parameter TWPRE = 0.35; // tWPRE tCK DQS Write Preamble
|
| 299 |
|
|
parameter TWPST = 0.40; // tWPST tCK DQS Write Postamble
|
| 300 |
|
|
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
|
| 301 |
|
|
// Command and Address
|
| 302 |
|
|
parameter TIPW = 0.6; // tIPW tCK Control and Address input Pulse Width
|
| 303 |
|
|
parameter TCCD = 2; // tCCD tCK Cas to Cas command delay
|
| 304 |
|
|
parameter TRAS_MIN = 40000; // tRAS ps Minimum Active to Precharge command time
|
| 305 |
|
|
parameter TRAS_MAX =70000000; // tRAS ps Maximum Active to Precharge command time
|
| 306 |
|
|
parameter TRTP = 7500; // tRTP ps Read to Precharge command delay
|
| 307 |
|
|
parameter TWR = 15000; // tWR ps Write recovery time
|
| 308 |
|
|
parameter TMRD = 2; // tMRD tCK Load Mode Register command cycle time
|
| 309 |
|
|
parameter TDLLK = 200; // tDLLK tCK DLL locking time
|
| 310 |
|
|
// Refresh
|
| 311 |
|
|
parameter TRFC_MIN = 75000; // tRFC ps Refresh to Refresh Command interval minimum value
|
| 312 |
|
|
parameter TRFC_MAX =70000000; // tRFC ps Refresh to Refresh Command Interval maximum value
|
| 313 |
|
|
// Self Refresh
|
| 314 |
|
|
parameter TXSNR = TRFC_MIN + 10000; // tXSNR ps Exit self refesh to a non-read command
|
| 315 |
|
|
parameter TXSRD = 200; // tXSRD tCK Exit self refresh to a read command
|
| 316 |
|
|
parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit.
|
| 317 |
|
|
// ODT
|
| 318 |
|
|
parameter TAOND = 2; // tAOND tCK ODT turn-on delay
|
| 319 |
|
|
parameter TAOFD = 2.5; // tAOFD tCK ODT turn-off delay
|
| 320 |
|
|
parameter TAONPD = 2000; // tAONPD ps ODT turn-on (precharge power-down mode)
|
| 321 |
|
|
parameter TAOFPD = 2000; // tAOFPD ps ODT turn-off (precharge power-down mode)
|
| 322 |
|
|
parameter TMOD = 12000; // tMOD ps ODT enable in EMR to ODT pin transition
|
| 323 |
|
|
// Power Down
|
| 324 |
|
|
parameter TCKE = 3; // tCKE tCK CKE minimum high or low pulse width
|
| 325 |
|
|
|
| 326 |
|
|
// Size Parameters based on Part Width
|
| 327 |
|
|
|
| 328 |
|
|
`ifdef x4
|
| 329 |
|
|
parameter DM_BITS = 1; // Number of Data Mask bits
|
| 330 |
|
|
parameter ROW_BITS = 13; // Number of Address bits
|
| 331 |
|
|
parameter COL_BITS = 11; // Number of Column bits
|
| 332 |
|
|
parameter DQ_BITS = 4; // Number of Data bits
|
| 333 |
|
|
parameter DQS_BITS = 1; // Number of Dqs bits
|
| 334 |
|
|
parameter TRRD = 7500; // tRRD Active bank a to Active bank b command time
|
| 335 |
|
|
`else `ifdef x8
|
| 336 |
|
|
parameter DM_BITS = 1; // Number of Data Mask bits
|
| 337 |
|
|
parameter ROW_BITS = 13; // Number of Address bits
|
| 338 |
|
|
parameter COL_BITS = 10; // Number of Column bits
|
| 339 |
|
|
parameter DQ_BITS = 8; // Number of Data bits
|
| 340 |
|
|
parameter DQS_BITS = 1; // Number of Dqs bits
|
| 341 |
|
|
parameter TRRD = 7500; // tRRD Active bank a to Active bank b command time
|
| 342 |
|
|
`else `define x16
|
| 343 |
|
|
parameter DM_BITS = 2; // Number of Data Mask bits
|
| 344 |
|
|
parameter ROW_BITS = 13; // Number of Address bits
|
| 345 |
|
|
parameter COL_BITS = 9; // Number of Column bits
|
| 346 |
|
|
parameter DQ_BITS = 16; // Number of Data bits
|
| 347 |
|
|
parameter DQS_BITS = 2; // Number of Dqs bits
|
| 348 |
|
|
parameter TRRD = 10000; // tRRD Active bank a to Active bank b command time
|
| 349 |
|
|
`endif `endif
|
| 350 |
|
|
|
| 351 |
|
|
`ifdef QUAD_RANK
|
| 352 |
|
|
`define DUAL_RANK // also define DUAL_RANK
|
| 353 |
|
|
parameter CS_BITS = 4; // Number of Chip Select Bits
|
| 354 |
|
|
parameter RANKS = 4; // Number of Chip Select Bits
|
| 355 |
|
|
`else `ifdef DUAL_RANK
|
| 356 |
|
|
parameter CS_BITS = 2; // Number of Chip Select Bits
|
| 357 |
|
|
parameter RANKS = 2; // Number of Chip Select Bits
|
| 358 |
|
|
`else
|
| 359 |
|
|
parameter CS_BITS = 2; // Number of Chip Select Bits
|
| 360 |
|
|
parameter RANKS = 1; // Number of Chip Select Bits
|
| 361 |
|
|
`endif `endif
|
| 362 |
|
|
|
| 363 |
|
|
// Size Parameters
|
| 364 |
|
|
parameter BA_BITS = 2; // Set this parmaeter to control how many Bank Address bits
|
| 365 |
|
|
parameter ADDR_BITS = 13; // Address Bits
|
| 366 |
|
|
parameter MEM_BITS = 10; // Number of write data bursts can be stored in memory. The default is 2^10=1024.
|
| 367 |
|
|
parameter AP = 10; // the address bit that controls auto-precharge and precharge-all
|
| 368 |
|
|
parameter BL_BITS = 3; // the number of bits required to count to MAX_BL
|
| 369 |
|
|
parameter BO_BITS = 2; // the number of Burst Order Bits
|
| 370 |
|
|
|
| 371 |
|
|
`else `ifdef x512Mb
|
| 372 |
|
|
|
| 373 |
|
|
`ifdef sg187E
|
| 374 |
|
|
parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
|
| 375 |
|
|
parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
|
| 376 |
|
|
parameter TJIT_DUTY = 75; // tJIT(duty) ps Half Period Jitter
|
| 377 |
|
|
parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
|
| 378 |
|
|
parameter TERR_2PER = 132; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 379 |
|
|
parameter TERR_3PER = 157; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 380 |
|
|
parameter TERR_4PER = 175; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 381 |
|
|
parameter TERR_5PER = 188; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 382 |
|
|
parameter TERR_N1PER = 250; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 383 |
|
|
parameter TERR_N2PER = 425; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 384 |
|
|
parameter TQHS = 250; // tQHS ps Data hold skew factor
|
| 385 |
|
|
parameter TAC = 350; // tAC ps DQ output access time from CK/CK#
|
| 386 |
|
|
parameter TDS = 0; // tDS ps DQ and DM input setup time relative to DQS
|
| 387 |
|
|
parameter TDH = 75; // tDH ps DQ and DM input hold time relative to DQS
|
| 388 |
|
|
parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK#
|
| 389 |
|
|
parameter TDQSQ = 175; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 390 |
|
|
parameter TIS = 125; // tIS ps Input Setup Time
|
| 391 |
|
|
parameter TIH = 200; // tIH ps Input Hold Time
|
| 392 |
|
|
parameter TRC = 54000; // tRC ps Active to Active/Auto Refresh command time
|
| 393 |
|
|
parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
|
| 394 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 395 |
|
|
parameter TRP = 13125; // tRP ps Precharge command period
|
| 396 |
|
|
parameter TRPA = 13125; // tRPA ps Precharge All period
|
| 397 |
|
|
parameter TXARDS = 10; // tXARDS tCK Exit low power active power down to a read command
|
| 398 |
|
|
parameter TXARD = 3; // tXARD tCK Exit active power down to a read command
|
| 399 |
|
|
parameter TXP = 3; // tXP tCK Exit power down to a non-read command
|
| 400 |
|
|
parameter TANPD = 4; // tANPD tCK ODT to power-down entry latency
|
| 401 |
|
|
parameter TAXPD = 11; // tAXPD tCK ODT power-down exit latency
|
| 402 |
|
|
parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
|
| 403 |
|
|
`else `ifdef sg25E
|
| 404 |
|
|
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
|
| 405 |
|
|
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
|
| 406 |
|
|
parameter TJIT_DUTY = 100; // tJIT(duty) ps Half Period Jitter
|
| 407 |
|
|
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
|
| 408 |
|
|
parameter TERR_2PER = 150; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 409 |
|
|
parameter TERR_3PER = 175; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 410 |
|
|
parameter TERR_4PER = 200; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 411 |
|
|
parameter TERR_5PER = 200; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 412 |
|
|
parameter TERR_N1PER = 300; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 413 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 414 |
|
|
parameter TQHS = 300; // tQHS ps Data hold skew factor
|
| 415 |
|
|
parameter TAC = 400; // tAC ps DQ output access time from CK/CK#
|
| 416 |
|
|
parameter TDS = 50; // tDS ps DQ and DM input setup time relative to DQS
|
| 417 |
|
|
parameter TDH = 125; // tDH ps DQ and DM input hold time relative to DQS
|
| 418 |
|
|
parameter TDQSCK = 350; // tDQSCK ps DQS output access time from CK/CK#
|
| 419 |
|
|
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 420 |
|
|
parameter TIS = 175; // tIS ps Input Setup Time
|
| 421 |
|
|
parameter TIH = 250; // tIH ps Input Hold Time
|
| 422 |
|
|
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
| 423 |
|
|
parameter TRCD = 12500; // tRCD ps Active to Read/Write command time
|
| 424 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 425 |
|
|
parameter TRP = 12500; // tRP ps Precharge command period
|
| 426 |
|
|
parameter TRPA = 12500; // tRPA ps Precharge All period
|
| 427 |
|
|
parameter TXARDS = 8; // tXARDS tCK Exit low power active power down to a read command
|
| 428 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 429 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 430 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 431 |
|
|
parameter TAXPD = 10; // tAXPD tCK ODT power-down exit latency
|
| 432 |
|
|
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
|
| 433 |
|
|
`else `ifdef sg25
|
| 434 |
|
|
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
|
| 435 |
|
|
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
|
| 436 |
|
|
parameter TJIT_DUTY = 100; // tJIT(duty) ps Half Period Jitter
|
| 437 |
|
|
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
|
| 438 |
|
|
parameter TERR_2PER = 150; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 439 |
|
|
parameter TERR_3PER = 175; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 440 |
|
|
parameter TERR_4PER = 200; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 441 |
|
|
parameter TERR_5PER = 200; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 442 |
|
|
parameter TERR_N1PER = 300; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 443 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 444 |
|
|
parameter TQHS = 300; // tQHS ps Data hold skew factor
|
| 445 |
|
|
parameter TAC = 400; // tAC ps DQ output access time from CK/CK#
|
| 446 |
|
|
parameter TDS = 50; // tDS ps DQ and DM input setup time relative to DQS
|
| 447 |
|
|
parameter TDH = 125; // tDH ps DQ and DM input hold time relative to DQS
|
| 448 |
|
|
parameter TDQSCK = 350; // tDQSCK ps DQS output access time from CK/CK#
|
| 449 |
|
|
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 450 |
|
|
parameter TIS = 175; // tIS ps Input Setup Time
|
| 451 |
|
|
parameter TIH = 250; // tIH ps Input Hold Time
|
| 452 |
|
|
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
| 453 |
|
|
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
| 454 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 455 |
|
|
parameter TRP = 15000; // tRP ps Precharge command period
|
| 456 |
|
|
parameter TRPA = 15000; // tRPA ps Precharge All period
|
| 457 |
|
|
parameter TXARDS = 8; // tXARDS tCK Exit low power active power down to a read command
|
| 458 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 459 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 460 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 461 |
|
|
parameter TAXPD = 10; // tAXPD tCK ODT power-down exit latency
|
| 462 |
|
|
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
| 463 |
|
|
`else `ifdef sg3E
|
| 464 |
|
|
parameter TCK_MIN = 3000; // tCK ps Minimum Clock Cycle Time
|
| 465 |
|
|
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
|
| 466 |
|
|
parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
|
| 467 |
|
|
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
|
| 468 |
|
|
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 469 |
|
|
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 470 |
|
|
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 471 |
|
|
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 472 |
|
|
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 473 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 474 |
|
|
parameter TQHS = 340; // tQHS ps Data hold skew factor
|
| 475 |
|
|
parameter TAC = 450; // tAC ps DQ output access time from CK/CK#
|
| 476 |
|
|
parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
|
| 477 |
|
|
parameter TDH = 175; // tDH ps DQ and DM input hold time relative to DQS
|
| 478 |
|
|
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
|
| 479 |
|
|
parameter TDQSQ = 240; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 480 |
|
|
parameter TIS = 200; // tIS ps Input Setup Time
|
| 481 |
|
|
parameter TIH = 275; // tIH ps Input Hold Time
|
| 482 |
|
|
parameter TRC = 54000; // tRC ps Active to Active/Auto Refresh command time
|
| 483 |
|
|
parameter TRCD = 12000; // tRCD ps Active to Read/Write command time
|
| 484 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 485 |
|
|
parameter TRP = 12000; // tRP ps Precharge command period
|
| 486 |
|
|
parameter TRPA = 12000; // tRPA ps Precharge All period
|
| 487 |
|
|
parameter TXARDS = 7; // tXARDS tCK Exit low power active power down to a read command
|
| 488 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 489 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 490 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 491 |
|
|
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
| 492 |
|
|
parameter CL_TIME = 12000; // CL ps Minimum CAS Latency
|
| 493 |
|
|
`else `ifdef sg3
|
| 494 |
|
|
parameter TCK_MIN = 3000; // tCK ps Minimum Clock Cycle Time
|
| 495 |
|
|
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
|
| 496 |
|
|
parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
|
| 497 |
|
|
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
|
| 498 |
|
|
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 499 |
|
|
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 500 |
|
|
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 501 |
|
|
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 502 |
|
|
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 503 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 504 |
|
|
parameter TQHS = 340; // tQHS ps Data hold skew factor
|
| 505 |
|
|
parameter TAC = 450; // tAC ps DQ output access time from CK/CK#
|
| 506 |
|
|
parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
|
| 507 |
|
|
parameter TDH = 175; // tDH ps DQ and DM input hold time relative to DQS
|
| 508 |
|
|
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
|
| 509 |
|
|
parameter TDQSQ = 240; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 510 |
|
|
parameter TIS = 200; // tIS ps Input Setup Time
|
| 511 |
|
|
parameter TIH = 275; // tIH ps Input Hold Time
|
| 512 |
|
|
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
| 513 |
|
|
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
| 514 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 515 |
|
|
parameter TRP = 15000; // tRP ps Precharge command period
|
| 516 |
|
|
parameter TRPA = 15000; // tRPA ps Precharge All period
|
| 517 |
|
|
parameter TXARDS = 7; // tXARDS tCK Exit low power active power down to a read command
|
| 518 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 519 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 520 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 521 |
|
|
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
| 522 |
|
|
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
| 523 |
|
|
`else `ifdef sg37E
|
| 524 |
|
|
parameter TCK_MIN = 3750; // tCK ps Minimum Clock Cycle Time
|
| 525 |
|
|
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
|
| 526 |
|
|
parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
|
| 527 |
|
|
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
|
| 528 |
|
|
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 529 |
|
|
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 530 |
|
|
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 531 |
|
|
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 532 |
|
|
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 533 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 534 |
|
|
parameter TQHS = 400; // tQHS ps Data hold skew factor
|
| 535 |
|
|
parameter TAC = 500; // tAC ps DQ output access time from CK/CK#
|
| 536 |
|
|
parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
|
| 537 |
|
|
parameter TDH = 225; // tDH ps DQ and DM input hold time relative to DQS
|
| 538 |
|
|
parameter TDQSCK = 450; // tDQSCK ps DQS output access time from CK/CK#
|
| 539 |
|
|
parameter TDQSQ = 300; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 540 |
|
|
parameter TIS = 250; // tIS ps Input Setup Time
|
| 541 |
|
|
parameter TIH = 375; // tIH ps Input Hold Time
|
| 542 |
|
|
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
| 543 |
|
|
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
| 544 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 545 |
|
|
parameter TRP = 15000; // tRP ps Precharge command period
|
| 546 |
|
|
parameter TRPA = 15000; // tRPA ps Precharge All period
|
| 547 |
|
|
parameter TXARDS = 6; // tXARDS tCK Exit low power active power down to a read command
|
| 548 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 549 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 550 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 551 |
|
|
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
| 552 |
|
|
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
| 553 |
|
|
`else `define sg5E
|
| 554 |
|
|
parameter TCK_MIN = 5000; // tCK ps Minimum Clock Cycle Time
|
| 555 |
|
|
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
|
| 556 |
|
|
parameter TJIT_DUTY = 150; // tJIT(duty) ps Half Period Jitter
|
| 557 |
|
|
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
|
| 558 |
|
|
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 559 |
|
|
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 560 |
|
|
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 561 |
|
|
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 562 |
|
|
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 563 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 564 |
|
|
parameter TQHS = 450; // tQHS ps Data hold skew factor
|
| 565 |
|
|
parameter TAC = 600; // tAC ps DQ output access time from CK/CK#
|
| 566 |
|
|
parameter TDS = 150; // tDS ps DQ and DM input setup time relative to DQS
|
| 567 |
|
|
parameter TDH = 275; // tDH ps DQ and DM input hold time relative to DQS
|
| 568 |
|
|
parameter TDQSCK = 500; // tDQSCK ps DQS output access time from CK/CK#
|
| 569 |
|
|
parameter TDQSQ = 350; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 570 |
|
|
parameter TIS = 350; // tIS ps Input Setup Time
|
| 571 |
|
|
parameter TIH = 475; // tIH ps Input Hold Time
|
| 572 |
|
|
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
| 573 |
|
|
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
| 574 |
|
|
parameter TWTR = 10000; // tWTR ps Write to Read command delay
|
| 575 |
|
|
parameter TRP = 15000; // tRP ps Precharge command period
|
| 576 |
|
|
parameter TRPA = 15000; // tRPA ps Precharge All period
|
| 577 |
|
|
parameter TXARDS = 6; // tXARDS tCK Exit low power active power down to a read command
|
| 578 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 579 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 580 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 581 |
|
|
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
| 582 |
|
|
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
| 583 |
|
|
`endif `endif `endif `endif `endif `endif
|
| 584 |
|
|
|
| 585 |
|
|
`ifdef x16
|
| 586 |
|
|
`ifdef sg187E
|
| 587 |
|
|
parameter TFAW = 45000; // tFAW ps Four Bank Activate window
|
| 588 |
|
|
`else `ifdef sg25E
|
| 589 |
|
|
parameter TFAW = 45000; // tFAW ps Four Bank Activate window
|
| 590 |
|
|
`else `ifdef sg25
|
| 591 |
|
|
parameter TFAW = 45000; // tFAW ps Four Bank Activate window
|
| 592 |
|
|
`else // sg3E, sg3, sg37E, sg5E
|
| 593 |
|
|
parameter TFAW = 50000; // tFAW ps Four Bank Activate window
|
| 594 |
|
|
`endif `endif `endif
|
| 595 |
|
|
`else // x4, x8
|
| 596 |
|
|
`ifdef sg187E
|
| 597 |
|
|
parameter TFAW = 35000; // tFAW ps Four Bank Activate window
|
| 598 |
|
|
`else `ifdef sg25E
|
| 599 |
|
|
parameter TFAW = 35000; // tFAW ps Four Bank Activate window
|
| 600 |
|
|
`else `ifdef sg25
|
| 601 |
|
|
parameter TFAW = 35000; // tFAW ps Four Bank Activate window
|
| 602 |
|
|
`else // sg3E, sg3, sg37E, sg5E
|
| 603 |
|
|
parameter TFAW = 37500; // tFAW ps Four Bank Activate window
|
| 604 |
|
|
`endif `endif `endif
|
| 605 |
|
|
`endif
|
| 606 |
|
|
|
| 607 |
|
|
// Timing Parameters
|
| 608 |
|
|
|
| 609 |
|
|
// Mode Register
|
| 610 |
|
|
parameter AL_MIN = 0; // AL tCK Minimum Additive Latency
|
| 611 |
|
|
parameter AL_MAX = 6; // AL tCK Maximum Additive Latency
|
| 612 |
|
|
parameter CL_MIN = 3; // CL tCK Minimum CAS Latency
|
| 613 |
|
|
parameter CL_MAX = 7; // CL tCK Maximum CAS Latency
|
| 614 |
|
|
parameter WR_MIN = 2; // WR tCK Minimum Write Recovery
|
| 615 |
|
|
parameter WR_MAX = 8; // WR tCK Maximum Write Recovery
|
| 616 |
|
|
parameter BL_MIN = 4; // BL tCK Minimum Burst Length
|
| 617 |
|
|
parameter BL_MAX = 8; // BL tCK Minimum Burst Length
|
| 618 |
|
|
// Clock
|
| 619 |
|
|
parameter TCK_MAX = 8000; // tCK ps Maximum Clock Cycle Time
|
| 620 |
|
|
parameter TCH_MIN = 0.48; // tCH tCK Minimum Clock High-Level Pulse Width
|
| 621 |
|
|
parameter TCH_MAX = 0.52; // tCH tCK Maximum Clock High-Level Pulse Width
|
| 622 |
|
|
parameter TCL_MIN = 0.48; // tCL tCK Minimum Clock Low-Level Pulse Width
|
| 623 |
|
|
parameter TCL_MAX = 0.52; // tCL tCK Maximum Clock Low-Level Pulse Width
|
| 624 |
|
|
// Data
|
| 625 |
|
|
parameter TLZ = TAC; // tLZ ps Data-out low-impedance window from CK/CK#
|
| 626 |
|
|
parameter THZ = TAC; // tHZ ps Data-out high impedance window from CK/CK#
|
| 627 |
|
|
parameter TDIPW = 0.35; // tDIPW tCK DQ and DM input Pulse Width
|
| 628 |
|
|
// Data Strobe
|
| 629 |
|
|
parameter TDQSH = 0.35; // tDQSH tCK DQS input High Pulse Width
|
| 630 |
|
|
parameter TDQSL = 0.35; // tDQSL tCK DQS input Low Pulse Width
|
| 631 |
|
|
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
|
| 632 |
|
|
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
|
| 633 |
|
|
parameter TWPRE = 0.35; // tWPRE tCK DQS Write Preamble
|
| 634 |
|
|
parameter TWPST = 0.40; // tWPST tCK DQS Write Postamble
|
| 635 |
|
|
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
|
| 636 |
|
|
// Command and Address
|
| 637 |
|
|
parameter TIPW = 0.6; // tIPW tCK Control and Address input Pulse Width
|
| 638 |
|
|
parameter TCCD = 2; // tCCD tCK Cas to Cas command delay
|
| 639 |
|
|
parameter TRAS_MIN = 40000; // tRAS ps Minimum Active to Precharge command time
|
| 640 |
|
|
parameter TRAS_MAX =70000000; // tRAS ps Maximum Active to Precharge command time
|
| 641 |
|
|
parameter TRTP = 7500; // tRTP ps Read to Precharge command delay
|
| 642 |
|
|
parameter TWR = 15000; // tWR ps Write recovery time
|
| 643 |
|
|
parameter TMRD = 2; // tMRD tCK Load Mode Register command cycle time
|
| 644 |
|
|
parameter TDLLK = 200; // tDLLK tCK DLL locking time
|
| 645 |
|
|
// Refresh
|
| 646 |
|
|
parameter TRFC_MIN = 105000; // tRFC ps Refresh to Refresh Command interval minimum value
|
| 647 |
|
|
parameter TRFC_MAX =70000000; // tRFC ps Refresh to Refresh Command Interval maximum value
|
| 648 |
|
|
// Self Refresh
|
| 649 |
|
|
parameter TXSNR = TRFC_MIN + 10000; // tXSNR ps Exit self refesh to a non-read command
|
| 650 |
|
|
parameter TXSRD = 200; // tXSRD tCK Exit self refresh to a read command
|
| 651 |
|
|
parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit.
|
| 652 |
|
|
// ODT
|
| 653 |
|
|
parameter TAOND = 2; // tAOND tCK ODT turn-on delay
|
| 654 |
|
|
parameter TAOFD = 2.5; // tAOFD tCK ODT turn-off delay
|
| 655 |
|
|
parameter TAONPD = 2000; // tAONPD ps ODT turn-on (precharge power-down mode)
|
| 656 |
|
|
parameter TAOFPD = 2000; // tAOFPD ps ODT turn-off (precharge power-down mode)
|
| 657 |
|
|
parameter TMOD = 12000; // tMOD ps ODT enable in EMR to ODT pin transition
|
| 658 |
|
|
// Power Down
|
| 659 |
|
|
parameter TCKE = 3; // tCKE tCK CKE minimum high or low pulse width
|
| 660 |
|
|
|
| 661 |
|
|
// Size Parameters based on Part Width
|
| 662 |
|
|
|
| 663 |
|
|
`ifdef x4
|
| 664 |
|
|
parameter ADDR_BITS = 14; // Address Bits
|
| 665 |
|
|
parameter ROW_BITS = 14; // Number of Address bits
|
| 666 |
|
|
parameter COL_BITS = 11; // Number of Column bits
|
| 667 |
|
|
parameter DM_BITS = 1; // Number of Data Mask bits
|
| 668 |
|
|
parameter DQ_BITS = 4; // Number of Data bits
|
| 669 |
|
|
parameter DQS_BITS = 1; // Number of Dqs bits
|
| 670 |
|
|
parameter TRRD = 7500; // tRRD Active bank a to Active bank b command time
|
| 671 |
|
|
`else `ifdef x8
|
| 672 |
|
|
parameter ADDR_BITS = 14; // Address Bits
|
| 673 |
|
|
parameter ROW_BITS = 14; // Number of Address bits
|
| 674 |
|
|
parameter COL_BITS = 10; // Number of Column bits
|
| 675 |
|
|
parameter DM_BITS = 1; // Number of Data Mask bits
|
| 676 |
|
|
parameter DQ_BITS = 8; // Number of Data bits
|
| 677 |
|
|
parameter DQS_BITS = 1; // Number of Dqs bits
|
| 678 |
|
|
parameter TRRD = 7500; // tRRD Active bank a to Active bank b command time
|
| 679 |
|
|
`else `define x16
|
| 680 |
|
|
parameter ADDR_BITS = 13; // Address Bits
|
| 681 |
|
|
parameter ROW_BITS = 13; // Number of Address bits
|
| 682 |
|
|
parameter COL_BITS = 10; // Number of Column bits
|
| 683 |
|
|
parameter DM_BITS = 2; // Number of Data Mask bits
|
| 684 |
|
|
parameter DQ_BITS = 16; // Number of Data bits
|
| 685 |
|
|
parameter DQS_BITS = 2; // Number of Dqs bits
|
| 686 |
|
|
parameter TRRD = 10000; // tRRD Active bank a to Active bank b command time
|
| 687 |
|
|
`endif `endif
|
| 688 |
|
|
|
| 689 |
|
|
`ifdef QUAD_RANK
|
| 690 |
|
|
`define DUAL_RANK // also define DUAL_RANK
|
| 691 |
|
|
parameter CS_BITS = 4; // Number of Chip Select Bits
|
| 692 |
|
|
parameter RANKS = 4; // Number of Chip Select Bits
|
| 693 |
|
|
`else `ifdef DUAL_RANK
|
| 694 |
|
|
parameter CS_BITS = 2; // Number of Chip Select Bits
|
| 695 |
|
|
parameter RANKS = 2; // Number of Chip Select Bits
|
| 696 |
|
|
`else
|
| 697 |
|
|
parameter CS_BITS = 2; // Number of Chip Select Bits
|
| 698 |
|
|
parameter RANKS = 1; // Number of Chip Select Bits
|
| 699 |
|
|
`endif `endif
|
| 700 |
|
|
|
| 701 |
|
|
// Size Parameters
|
| 702 |
|
|
parameter BA_BITS = 2; // Set this parmaeter to control how many Bank Address bits
|
| 703 |
|
|
parameter MEM_BITS = 10; // Number of write data bursts can be stored in memory. The default is 2^10=1024.
|
| 704 |
|
|
parameter AP = 10; // the address bit that controls auto-precharge and precharge-all
|
| 705 |
|
|
parameter BL_BITS = 3; // the number of bits required to count to MAX_BL
|
| 706 |
|
|
parameter BO_BITS = 2; // the number of Burst Order Bits
|
| 707 |
|
|
|
| 708 |
|
|
`else `ifdef x1Gb
|
| 709 |
|
|
|
| 710 |
|
|
`ifdef sg187E
|
| 711 |
|
|
parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
|
| 712 |
|
|
parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
|
| 713 |
|
|
parameter TJIT_DUTY = 75; // tJIT(duty) ps Half Period Jitter
|
| 714 |
|
|
parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
|
| 715 |
|
|
parameter TERR_2PER = 132; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 716 |
|
|
parameter TERR_3PER = 157; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 717 |
|
|
parameter TERR_4PER = 175; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 718 |
|
|
parameter TERR_5PER = 188; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 719 |
|
|
parameter TERR_N1PER = 250; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 720 |
|
|
parameter TERR_N2PER = 425; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 721 |
|
|
parameter TQHS = 250; // tQHS ps Data hold skew factor
|
| 722 |
|
|
parameter TAC = 350; // tAC ps DQ output access time from CK/CK#
|
| 723 |
|
|
parameter TDS = 0; // tDS ps DQ and DM input setup time relative to DQS
|
| 724 |
|
|
parameter TDH = 75; // tDH ps DQ and DM input hold time relative to DQS
|
| 725 |
|
|
parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK#
|
| 726 |
|
|
parameter TDQSQ = 175; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 727 |
|
|
parameter TIS = 125; // tIS ps Input Setup Time
|
| 728 |
|
|
parameter TIH = 200; // tIH ps Input Hold Time
|
| 729 |
|
|
parameter TRC = 54000; // tRC ps Active to Active/Auto Refresh command time
|
| 730 |
|
|
parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
|
| 731 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 732 |
|
|
parameter TRP = 13125; // tRP ps Precharge command period
|
| 733 |
|
|
parameter TRPA = 15000; // tRPA ps Precharge All period
|
| 734 |
|
|
parameter TXARDS = 10; // tXARDS tCK Exit low power active power down to a read command
|
| 735 |
|
|
parameter TXARD = 3; // tXARD tCK Exit active power down to a read command
|
| 736 |
|
|
parameter TXP = 3; // tXP tCK Exit power down to a non-read command
|
| 737 |
|
|
parameter TANPD = 4; // tANPD tCK ODT to power-down entry latency
|
| 738 |
|
|
parameter TAXPD = 11; // tAXPD tCK ODT power-down exit latency
|
| 739 |
|
|
parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
|
| 740 |
|
|
`else `ifdef sg25E
|
| 741 |
|
|
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
|
| 742 |
|
|
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
|
| 743 |
|
|
parameter TJIT_DUTY = 100; // tJIT(duty) ps Half Period Jitter
|
| 744 |
|
|
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
|
| 745 |
|
|
parameter TERR_2PER = 150; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 746 |
|
|
parameter TERR_3PER = 175; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 747 |
|
|
parameter TERR_4PER = 200; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 748 |
|
|
parameter TERR_5PER = 200; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 749 |
|
|
parameter TERR_N1PER = 300; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 750 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 751 |
|
|
parameter TQHS = 300; // tQHS ps Data hold skew factor
|
| 752 |
|
|
parameter TAC = 400; // tAC ps DQ output access time from CK/CK#
|
| 753 |
|
|
parameter TDS = 50; // tDS ps DQ and DM input setup time relative to DQS
|
| 754 |
|
|
parameter TDH = 125; // tDH ps DQ and DM input hold time relative to DQS
|
| 755 |
|
|
parameter TDQSCK = 350; // tDQSCK ps DQS output access time from CK/CK#
|
| 756 |
|
|
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 757 |
|
|
parameter TIS = 175; // tIS ps Input Setup Time
|
| 758 |
|
|
parameter TIH = 250; // tIH ps Input Hold Time
|
| 759 |
|
|
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
| 760 |
|
|
parameter TRCD = 12500; // tRCD ps Active to Read/Write command time
|
| 761 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 762 |
|
|
parameter TRP = 12500; // tRP ps Precharge command period
|
| 763 |
|
|
parameter TRPA = 15000; // tRPA ps Precharge All period
|
| 764 |
|
|
parameter TXARDS = 8; // tXARDS tCK Exit low power active power down to a read command
|
| 765 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 766 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 767 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 768 |
|
|
parameter TAXPD = 10; // tAXPD tCK ODT power-down exit latency
|
| 769 |
|
|
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
|
| 770 |
|
|
`else `ifdef sg25
|
| 771 |
|
|
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
|
| 772 |
|
|
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
|
| 773 |
|
|
parameter TJIT_DUTY = 100; // tJIT(duty) ps Half Period Jitter
|
| 774 |
|
|
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
|
| 775 |
|
|
parameter TERR_2PER = 150; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 776 |
|
|
parameter TERR_3PER = 175; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 777 |
|
|
parameter TERR_4PER = 200; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 778 |
|
|
parameter TERR_5PER = 200; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 779 |
|
|
parameter TERR_N1PER = 300; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 780 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 781 |
|
|
parameter TQHS = 300; // tQHS ps Data hold skew factor
|
| 782 |
|
|
parameter TAC = 400; // tAC ps DQ output access time from CK/CK#
|
| 783 |
|
|
parameter TDS = 50; // tDS ps DQ and DM input setup time relative to DQS
|
| 784 |
|
|
parameter TDH = 125; // tDH ps DQ and DM input hold time relative to DQS
|
| 785 |
|
|
parameter TDQSCK = 350; // tDQSCK ps DQS output access time from CK/CK#
|
| 786 |
|
|
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 787 |
|
|
parameter TIS = 175; // tIS ps Input Setup Time
|
| 788 |
|
|
parameter TIH = 250; // tIH ps Input Hold Time
|
| 789 |
|
|
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
| 790 |
|
|
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
| 791 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 792 |
|
|
parameter TRP = 15000; // tRP ps Precharge command period
|
| 793 |
|
|
parameter TRPA = 17500; // tRPA ps Precharge All period
|
| 794 |
|
|
parameter TXARDS = 8; // tXARDS tCK Exit low power active power down to a read command
|
| 795 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 796 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 797 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 798 |
|
|
parameter TAXPD = 10; // tAXPD tCK ODT power-down exit latency
|
| 799 |
|
|
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
| 800 |
|
|
`else `ifdef sg3E
|
| 801 |
|
|
parameter TCK_MIN = 3000; // tCK ps Minimum Clock Cycle Time
|
| 802 |
|
|
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
|
| 803 |
|
|
parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
|
| 804 |
|
|
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
|
| 805 |
|
|
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 806 |
|
|
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 807 |
|
|
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 808 |
|
|
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 809 |
|
|
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 810 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 811 |
|
|
parameter TQHS = 340; // tQHS ps Data hold skew factor
|
| 812 |
|
|
parameter TAC = 450; // tAC ps DQ output access time from CK/CK#
|
| 813 |
|
|
parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
|
| 814 |
|
|
parameter TDH = 175; // tDH ps DQ and DM input hold time relative to DQS
|
| 815 |
|
|
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
|
| 816 |
|
|
parameter TDQSQ = 240; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 817 |
|
|
parameter TIS = 200; // tIS ps Input Setup Time
|
| 818 |
|
|
parameter TIH = 275; // tIH ps Input Hold Time
|
| 819 |
|
|
parameter TRC = 54000; // tRC ps Active to Active/Auto Refresh command time
|
| 820 |
|
|
parameter TRCD = 12000; // tRCD ps Active to Read/Write command time
|
| 821 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 822 |
|
|
parameter TRP = 12000; // tRP ps Precharge command period
|
| 823 |
|
|
parameter TRPA = 15000; // tRPA ps Precharge All period
|
| 824 |
|
|
parameter TXARDS = 7; // tXARDS tCK Exit low power active power down to a read command
|
| 825 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 826 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 827 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 828 |
|
|
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
| 829 |
|
|
parameter CL_TIME = 12000; // CL ps Minimum CAS Latency
|
| 830 |
|
|
`else `ifdef sg3
|
| 831 |
|
|
parameter TCK_MIN = 3000; // tCK ps Minimum Clock Cycle Time
|
| 832 |
|
|
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
|
| 833 |
|
|
parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
|
| 834 |
|
|
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
|
| 835 |
|
|
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 836 |
|
|
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 837 |
|
|
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 838 |
|
|
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 839 |
|
|
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 840 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 841 |
|
|
parameter TQHS = 340; // tQHS ps Data hold skew factor
|
| 842 |
|
|
parameter TAC = 450; // tAC ps DQ output access time from CK/CK#
|
| 843 |
|
|
parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
|
| 844 |
|
|
parameter TDH = 175; // tDH ps DQ and DM input hold time relative to DQS
|
| 845 |
|
|
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
|
| 846 |
|
|
parameter TDQSQ = 240; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 847 |
|
|
parameter TIS = 200; // tIS ps Input Setup Time
|
| 848 |
|
|
parameter TIH = 275; // tIH ps Input Hold Time
|
| 849 |
|
|
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
| 850 |
|
|
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
| 851 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 852 |
|
|
parameter TRP = 15000; // tRP ps Precharge command period
|
| 853 |
|
|
parameter TRPA = 18000; // tRPA ps Precharge All period
|
| 854 |
|
|
parameter TXARDS = 7; // tXARDS tCK Exit low power active power down to a read command
|
| 855 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 856 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 857 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 858 |
|
|
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
| 859 |
|
|
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
| 860 |
|
|
`else `ifdef sg37E
|
| 861 |
|
|
parameter TCK_MIN = 3750; // tCK ps Minimum Clock Cycle Time
|
| 862 |
|
|
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
|
| 863 |
|
|
parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
|
| 864 |
|
|
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
|
| 865 |
|
|
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 866 |
|
|
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 867 |
|
|
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 868 |
|
|
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 869 |
|
|
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 870 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 871 |
|
|
parameter TQHS = 400; // tQHS ps Data hold skew factor
|
| 872 |
|
|
parameter TAC = 500; // tAC ps DQ output access time from CK/CK#
|
| 873 |
|
|
parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
|
| 874 |
|
|
parameter TDH = 225; // tDH ps DQ and DM input hold time relative to DQS
|
| 875 |
|
|
parameter TDQSCK = 450; // tDQSCK ps DQS output access time from CK/CK#
|
| 876 |
|
|
parameter TDQSQ = 300; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 877 |
|
|
parameter TIS = 250; // tIS ps Input Setup Time
|
| 878 |
|
|
parameter TIH = 375; // tIH ps Input Hold Time
|
| 879 |
|
|
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
| 880 |
|
|
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
| 881 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 882 |
|
|
parameter TRP = 15000; // tRP ps Precharge command period
|
| 883 |
|
|
parameter TRPA = 18750; // tRPA ps Precharge All period
|
| 884 |
|
|
parameter TXARDS = 6; // tXARDS tCK Exit low power active power down to a read command
|
| 885 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 886 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 887 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 888 |
|
|
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
| 889 |
|
|
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
| 890 |
|
|
`else `define sg5E
|
| 891 |
|
|
parameter TCK_MIN = 5000; // tCK ps Minimum Clock Cycle Time
|
| 892 |
|
|
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
|
| 893 |
|
|
parameter TJIT_DUTY = 150; // tJIT(duty) ps Half Period Jitter
|
| 894 |
|
|
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
|
| 895 |
|
|
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 896 |
|
|
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 897 |
|
|
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 898 |
|
|
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 899 |
|
|
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 900 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 901 |
|
|
parameter TQHS = 450; // tQHS ps Data hold skew factor
|
| 902 |
|
|
parameter TAC = 600; // tAC ps DQ output access time from CK/CK#
|
| 903 |
|
|
parameter TDS = 150; // tDS ps DQ and DM input setup time relative to DQS
|
| 904 |
|
|
parameter TDH = 275; // tDH ps DQ and DM input hold time relative to DQS
|
| 905 |
|
|
parameter TDQSCK = 500; // tDQSCK ps DQS output access time from CK/CK#
|
| 906 |
|
|
parameter TDQSQ = 350; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 907 |
|
|
parameter TIS = 350; // tIS ps Input Setup Time
|
| 908 |
|
|
parameter TIH = 475; // tIH ps Input Hold Time
|
| 909 |
|
|
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
| 910 |
|
|
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
| 911 |
|
|
parameter TWTR = 10000; // tWTR ps Write to Read command delay
|
| 912 |
|
|
parameter TRP = 15000; // tRP ps Precharge command period
|
| 913 |
|
|
parameter TRPA = 20000; // tRPA ps Precharge All period
|
| 914 |
|
|
parameter TXARDS = 6; // tXARDS tCK Exit low power active power down to a read command
|
| 915 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 916 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 917 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 918 |
|
|
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
| 919 |
|
|
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
| 920 |
|
|
`endif `endif `endif `endif `endif `endif
|
| 921 |
|
|
|
| 922 |
|
|
`ifdef x16
|
| 923 |
|
|
`ifdef sg187E
|
| 924 |
|
|
parameter TFAW = 45000; // tFAW ps Four Bank Activate window
|
| 925 |
|
|
`else `ifdef sg25E
|
| 926 |
|
|
parameter TFAW = 45000; // tFAW ps Four Bank Activate window
|
| 927 |
|
|
`else `ifdef sg25
|
| 928 |
|
|
parameter TFAW = 45000; // tFAW ps Four Bank Activate window
|
| 929 |
|
|
`else // sg3E, sg3, sg37E, sg5E
|
| 930 |
|
|
parameter TFAW = 50000; // tFAW ps Four Bank Activate window
|
| 931 |
|
|
`endif `endif `endif
|
| 932 |
|
|
`else // x4, x8
|
| 933 |
|
|
`ifdef sg187E
|
| 934 |
|
|
parameter TFAW = 35000; // tFAW ps Four Bank Activate window
|
| 935 |
|
|
`else `ifdef sg25E
|
| 936 |
|
|
parameter TFAW = 35000; // tFAW ps Four Bank Activate window
|
| 937 |
|
|
`else `ifdef sg25
|
| 938 |
|
|
parameter TFAW = 35000; // tFAW ps Four Bank Activate window
|
| 939 |
|
|
`else // sg3E, sg3, sg37E, sg5E
|
| 940 |
|
|
parameter TFAW = 37500; // tFAW ps Four Bank Activate window
|
| 941 |
|
|
`endif `endif `endif
|
| 942 |
|
|
`endif
|
| 943 |
|
|
|
| 944 |
|
|
// Timing Parameters
|
| 945 |
|
|
|
| 946 |
|
|
// Mode Register
|
| 947 |
|
|
parameter AL_MIN = 0; // AL tCK Minimum Additive Latency
|
| 948 |
|
|
parameter AL_MAX = 6; // AL tCK Maximum Additive Latency
|
| 949 |
|
|
parameter CL_MIN = 3; // CL tCK Minimum CAS Latency
|
| 950 |
|
|
parameter CL_MAX = 7; // CL tCK Maximum CAS Latency
|
| 951 |
|
|
parameter WR_MIN = 2; // WR tCK Minimum Write Recovery
|
| 952 |
|
|
parameter WR_MAX = 8; // WR tCK Maximum Write Recovery
|
| 953 |
|
|
parameter BL_MIN = 4; // BL tCK Minimum Burst Length
|
| 954 |
|
|
parameter BL_MAX = 8; // BL tCK Minimum Burst Length
|
| 955 |
|
|
// Clock
|
| 956 |
|
|
parameter TCK_MAX = 8000; // tCK ps Maximum Clock Cycle Time
|
| 957 |
|
|
parameter TCH_MIN = 0.48; // tCH tCK Minimum Clock High-Level Pulse Width
|
| 958 |
|
|
parameter TCH_MAX = 0.52; // tCH tCK Maximum Clock High-Level Pulse Width
|
| 959 |
|
|
parameter TCL_MIN = 0.48; // tCL tCK Minimum Clock Low-Level Pulse Width
|
| 960 |
|
|
parameter TCL_MAX = 0.52; // tCL tCK Maximum Clock Low-Level Pulse Width
|
| 961 |
|
|
// Data
|
| 962 |
|
|
parameter TLZ = TAC; // tLZ ps Data-out low-impedance window from CK/CK#
|
| 963 |
|
|
parameter THZ = TAC; // tHZ ps Data-out high impedance window from CK/CK#
|
| 964 |
|
|
parameter TDIPW = 0.35; // tDIPW tCK DQ and DM input Pulse Width
|
| 965 |
|
|
// Data Strobe
|
| 966 |
|
|
parameter TDQSH = 0.35; // tDQSH tCK DQS input High Pulse Width
|
| 967 |
|
|
parameter TDQSL = 0.35; // tDQSL tCK DQS input Low Pulse Width
|
| 968 |
|
|
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
|
| 969 |
|
|
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
|
| 970 |
|
|
parameter TWPRE = 0.35; // tWPRE tCK DQS Write Preamble
|
| 971 |
|
|
parameter TWPST = 0.40; // tWPST tCK DQS Write Postamble
|
| 972 |
|
|
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
|
| 973 |
|
|
// Command and Address
|
| 974 |
|
|
parameter TIPW = 0.6; // tIPW tCK Control and Address input Pulse Width
|
| 975 |
|
|
parameter TCCD = 2; // tCCD tCK Cas to Cas command delay
|
| 976 |
|
|
parameter TRAS_MIN = 40000; // tRAS ps Minimum Active to Precharge command time
|
| 977 |
|
|
parameter TRAS_MAX =70000000; // tRAS ps Maximum Active to Precharge command time
|
| 978 |
|
|
parameter TRTP = 7500; // tRTP ps Read to Precharge command delay
|
| 979 |
|
|
parameter TWR = 15000; // tWR ps Write recovery time
|
| 980 |
|
|
parameter TMRD = 2; // tMRD tCK Load Mode Register command cycle time
|
| 981 |
|
|
parameter TDLLK = 200; // tDLLK tCK DLL locking time
|
| 982 |
|
|
// Refresh
|
| 983 |
|
|
parameter TRFC_MIN = 127500; // tRFC ps Refresh to Refresh Command interval minimum value
|
| 984 |
|
|
parameter TRFC_MAX =70000000; // tRFC ps Refresh to Refresh Command Interval maximum value
|
| 985 |
|
|
// Self Refresh
|
| 986 |
|
|
parameter TXSNR = TRFC_MIN + 10000; // tXSNR ps Exit self refesh to a non-read command
|
| 987 |
|
|
parameter TXSRD = 200; // tXSRD tCK Exit self refresh to a read command
|
| 988 |
|
|
parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit.
|
| 989 |
|
|
// ODT
|
| 990 |
|
|
parameter TAOND = 2; // tAOND tCK ODT turn-on delay
|
| 991 |
|
|
parameter TAOFD = 2.5; // tAOFD tCK ODT turn-off delay
|
| 992 |
|
|
parameter TAONPD = 2000; // tAONPD ps ODT turn-on (precharge power-down mode)
|
| 993 |
|
|
parameter TAOFPD = 2000; // tAOFPD ps ODT turn-off (precharge power-down mode)
|
| 994 |
|
|
parameter TMOD = 12000; // tMOD ps ODT enable in EMR to ODT pin transition
|
| 995 |
|
|
// Power Down
|
| 996 |
|
|
parameter TCKE = 3; // tCKE tCK CKE minimum high or low pulse width
|
| 997 |
|
|
|
| 998 |
|
|
// Size Parameters based on Part Width
|
| 999 |
|
|
|
| 1000 |
|
|
`ifdef x4
|
| 1001 |
|
|
parameter ADDR_BITS = 14; // Address Bits
|
| 1002 |
|
|
parameter ROW_BITS = 14; // Number of Address bits
|
| 1003 |
|
|
parameter COL_BITS = 11; // Number of Column bits
|
| 1004 |
|
|
parameter DM_BITS = 1; // Number of Data Mask bits
|
| 1005 |
|
|
parameter DQ_BITS = 4; // Number of Data bits
|
| 1006 |
|
|
parameter DQS_BITS = 1; // Number of Dqs bits
|
| 1007 |
|
|
parameter TRRD = 7500; // tRRD Active bank a to Active bank b command time
|
| 1008 |
|
|
`else `ifdef x8
|
| 1009 |
|
|
parameter ADDR_BITS = 14; // Address Bits
|
| 1010 |
|
|
parameter ROW_BITS = 14; // Number of Address bits
|
| 1011 |
|
|
parameter COL_BITS = 10; // Number of Column bits
|
| 1012 |
|
|
parameter DM_BITS = 1; // Number of Data Mask bits
|
| 1013 |
|
|
parameter DQ_BITS = 8; // Number of Data bits
|
| 1014 |
|
|
parameter DQS_BITS = 1; // Number of Dqs bits
|
| 1015 |
|
|
parameter TRRD = 7500; // tRRD Active bank a to Active bank b command time
|
| 1016 |
|
|
`else `define x16
|
| 1017 |
|
|
parameter ADDR_BITS = 13; // Address Bits
|
| 1018 |
|
|
parameter ROW_BITS = 13; // Number of Address bits
|
| 1019 |
|
|
parameter COL_BITS = 10; // Number of Column bits
|
| 1020 |
|
|
parameter DM_BITS = 2; // Number of Data Mask bits
|
| 1021 |
|
|
parameter DQ_BITS = 16; // Number of Data bits
|
| 1022 |
|
|
parameter DQS_BITS = 2; // Number of Dqs bits
|
| 1023 |
|
|
parameter TRRD = 10000; // tRRD Active bank a to Active bank b command time
|
| 1024 |
|
|
`endif `endif
|
| 1025 |
|
|
|
| 1026 |
|
|
`ifdef QUAD_RANK
|
| 1027 |
|
|
`define DUAL_RANK // also define DUAL_RANK
|
| 1028 |
|
|
parameter CS_BITS = 4; // Number of Chip Select Bits
|
| 1029 |
|
|
parameter RANKS = 4; // Number of Chip Select Bits
|
| 1030 |
|
|
`else `ifdef DUAL_RANK
|
| 1031 |
|
|
parameter CS_BITS = 2; // Number of Chip Select Bits
|
| 1032 |
|
|
parameter RANKS = 2; // Number of Chip Select Bits
|
| 1033 |
|
|
`else
|
| 1034 |
|
|
parameter CS_BITS = 2; // Number of Chip Select Bits
|
| 1035 |
|
|
parameter RANKS = 1; // Number of Chip Select Bits
|
| 1036 |
|
|
`endif `endif
|
| 1037 |
|
|
|
| 1038 |
|
|
// Size Parameters
|
| 1039 |
|
|
parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits
|
| 1040 |
|
|
//parameter MEM_BITS = 10; // Number of write data bursts can be stored in memory. The default is 2^10=1024.
|
| 1041 |
|
|
parameter MEM_BITS = 17; // Number of write data bursts can be stored in memory.
|
| 1042 |
|
|
parameter AP = 10; // the address bit that controls auto-precharge and precharge-all
|
| 1043 |
|
|
parameter BL_BITS = 3; // the number of bits required to count to MAX_BL
|
| 1044 |
|
|
parameter BO_BITS = 2; // the number of Burst Order Bits
|
| 1045 |
|
|
|
| 1046 |
|
|
`else `define x2Gb
|
| 1047 |
|
|
|
| 1048 |
|
|
`ifdef sg187E
|
| 1049 |
|
|
parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
|
| 1050 |
|
|
parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
|
| 1051 |
|
|
parameter TJIT_DUTY = 75; // tJIT(duty) ps Half Period Jitter
|
| 1052 |
|
|
parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
|
| 1053 |
|
|
parameter TERR_2PER = 132; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 1054 |
|
|
parameter TERR_3PER = 157; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 1055 |
|
|
parameter TERR_4PER = 175; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 1056 |
|
|
parameter TERR_5PER = 188; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 1057 |
|
|
parameter TERR_N1PER = 250; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 1058 |
|
|
parameter TERR_N2PER = 425; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 1059 |
|
|
parameter TQHS = 250; // tQHS ps Data hold skew factor
|
| 1060 |
|
|
parameter TAC = 350; // tAC ps DQ output access time from CK/CK#
|
| 1061 |
|
|
parameter TDS = 0; // tDS ps DQ and DM input setup time relative to DQS
|
| 1062 |
|
|
parameter TDH = 75; // tDH ps DQ and DM input hold time relative to DQS
|
| 1063 |
|
|
parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK#
|
| 1064 |
|
|
parameter TDQSQ = 175; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 1065 |
|
|
parameter TIS = 125; // tIS ps Input Setup Time
|
| 1066 |
|
|
parameter TIH = 200; // tIH ps Input Hold Time
|
| 1067 |
|
|
parameter TRC = 54000; // tRC ps Active to Active/Auto Refresh command time
|
| 1068 |
|
|
parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
|
| 1069 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 1070 |
|
|
parameter TRP = 13125; // tRP ps Precharge command period
|
| 1071 |
|
|
parameter TRPA = 15000; // tRPA ps Precharge All period
|
| 1072 |
|
|
parameter TXARDS = 10; // tXARDS tCK Exit low power active power down to a read command
|
| 1073 |
|
|
parameter TXARD = 3; // tXARD tCK Exit active power down to a read command
|
| 1074 |
|
|
parameter TXP = 3; // tXP tCK Exit power down to a non-read command
|
| 1075 |
|
|
parameter TANPD = 4; // tANPD tCK ODT to power-down entry latency
|
| 1076 |
|
|
parameter TAXPD = 11; // tAXPD tCK ODT power-down exit latency
|
| 1077 |
|
|
parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
|
| 1078 |
|
|
`else `ifdef sg25E
|
| 1079 |
|
|
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
|
| 1080 |
|
|
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
|
| 1081 |
|
|
parameter TJIT_DUTY = 100; // tJIT(duty) ps Half Period Jitter
|
| 1082 |
|
|
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
|
| 1083 |
|
|
parameter TERR_2PER = 150; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 1084 |
|
|
parameter TERR_3PER = 175; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 1085 |
|
|
parameter TERR_4PER = 200; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 1086 |
|
|
parameter TERR_5PER = 200; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 1087 |
|
|
parameter TERR_N1PER = 300; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 1088 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 1089 |
|
|
parameter TQHS = 300; // tQHS ps Data hold skew factor
|
| 1090 |
|
|
parameter TAC = 400; // tAC ps DQ output access time from CK/CK#
|
| 1091 |
|
|
parameter TDS = 50; // tDS ps DQ and DM input setup time relative to DQS
|
| 1092 |
|
|
parameter TDH = 125; // tDH ps DQ and DM input hold time relative to DQS
|
| 1093 |
|
|
parameter TDQSCK = 350; // tDQSCK ps DQS output access time from CK/CK#
|
| 1094 |
|
|
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 1095 |
|
|
parameter TIS = 175; // tIS ps Input Setup Time
|
| 1096 |
|
|
parameter TIH = 250; // tIH ps Input Hold Time
|
| 1097 |
|
|
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
| 1098 |
|
|
parameter TRCD = 12500; // tRCD ps Active to Read/Write command time
|
| 1099 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 1100 |
|
|
parameter TRP = 12500; // tRP ps Precharge command period
|
| 1101 |
|
|
parameter TRPA = 15000; // tRPA ps Precharge All period
|
| 1102 |
|
|
parameter TXARDS = 8; // tXARDS tCK Exit low power active power down to a read command
|
| 1103 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 1104 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 1105 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 1106 |
|
|
parameter TAXPD = 10; // tAXPD tCK ODT power-down exit latency
|
| 1107 |
|
|
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
|
| 1108 |
|
|
`else `ifdef sg25
|
| 1109 |
|
|
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
|
| 1110 |
|
|
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
|
| 1111 |
|
|
parameter TJIT_DUTY = 100; // tJIT(duty) ps Half Period Jitter
|
| 1112 |
|
|
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
|
| 1113 |
|
|
parameter TERR_2PER = 150; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 1114 |
|
|
parameter TERR_3PER = 175; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 1115 |
|
|
parameter TERR_4PER = 200; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 1116 |
|
|
parameter TERR_5PER = 200; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 1117 |
|
|
parameter TERR_N1PER = 300; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 1118 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 1119 |
|
|
parameter TQHS = 300; // tQHS ps Data hold skew factor
|
| 1120 |
|
|
parameter TAC = 400; // tAC ps DQ output access time from CK/CK#
|
| 1121 |
|
|
parameter TDS = 50; // tDS ps DQ and DM input setup time relative to DQS
|
| 1122 |
|
|
parameter TDH = 125; // tDH ps DQ and DM input hold time relative to DQS
|
| 1123 |
|
|
parameter TDQSCK = 350; // tDQSCK ps DQS output access time from CK/CK#
|
| 1124 |
|
|
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 1125 |
|
|
parameter TIS = 175; // tIS ps Input Setup Time
|
| 1126 |
|
|
parameter TIH = 250; // tIH ps Input Hold Time
|
| 1127 |
|
|
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
| 1128 |
|
|
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
| 1129 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 1130 |
|
|
parameter TRP = 15000; // tRP ps Precharge command period
|
| 1131 |
|
|
parameter TRPA = 17500; // tRPA ps Precharge All period
|
| 1132 |
|
|
parameter TXARDS = 8; // tXARDS tCK Exit low power active power down to a read command
|
| 1133 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 1134 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 1135 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 1136 |
|
|
parameter TAXPD = 10; // tAXPD tCK ODT power-down exit latency
|
| 1137 |
|
|
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
| 1138 |
|
|
`else `ifdef sg3E
|
| 1139 |
|
|
parameter TCK_MIN = 3000; // tCK ps Minimum Clock Cycle Time
|
| 1140 |
|
|
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
|
| 1141 |
|
|
parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
|
| 1142 |
|
|
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
|
| 1143 |
|
|
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 1144 |
|
|
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 1145 |
|
|
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 1146 |
|
|
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 1147 |
|
|
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 1148 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 1149 |
|
|
parameter TQHS = 340; // tQHS ps Data hold skew factor
|
| 1150 |
|
|
parameter TAC = 450; // tAC ps DQ output access time from CK/CK#
|
| 1151 |
|
|
parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
|
| 1152 |
|
|
parameter TDH = 175; // tDH ps DQ and DM input hold time relative to DQS
|
| 1153 |
|
|
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
|
| 1154 |
|
|
parameter TDQSQ = 240; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 1155 |
|
|
parameter TIS = 200; // tIS ps Input Setup Time
|
| 1156 |
|
|
parameter TIH = 275; // tIH ps Input Hold Time
|
| 1157 |
|
|
parameter TRC = 54000; // tRC ps Active to Active/Auto Refresh command time
|
| 1158 |
|
|
parameter TRCD = 12000; // tRCD ps Active to Read/Write command time
|
| 1159 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 1160 |
|
|
parameter TRP = 12000; // tRP ps Precharge command period
|
| 1161 |
|
|
parameter TRPA = 15000; // tRPA ps Precharge All period
|
| 1162 |
|
|
parameter TXARDS = 7; // tXARDS tCK Exit low power active power down to a read command
|
| 1163 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 1164 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 1165 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 1166 |
|
|
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
| 1167 |
|
|
parameter CL_TIME = 12000; // CL ps Minimum CAS Latency
|
| 1168 |
|
|
`else `ifdef sg3
|
| 1169 |
|
|
parameter TCK_MIN = 3000; // tCK ps Minimum Clock Cycle Time
|
| 1170 |
|
|
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
|
| 1171 |
|
|
parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
|
| 1172 |
|
|
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
|
| 1173 |
|
|
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 1174 |
|
|
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 1175 |
|
|
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 1176 |
|
|
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 1177 |
|
|
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 1178 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 1179 |
|
|
parameter TQHS = 340; // tQHS ps Data hold skew factor
|
| 1180 |
|
|
parameter TAC = 450; // tAC ps DQ output access time from CK/CK#
|
| 1181 |
|
|
parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
|
| 1182 |
|
|
parameter TDH = 175; // tDH ps DQ and DM input hold time relative to DQS
|
| 1183 |
|
|
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
|
| 1184 |
|
|
parameter TDQSQ = 240; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 1185 |
|
|
parameter TIS = 200; // tIS ps Input Setup Time
|
| 1186 |
|
|
parameter TIH = 275; // tIH ps Input Hold Time
|
| 1187 |
|
|
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
| 1188 |
|
|
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
| 1189 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 1190 |
|
|
parameter TRP = 15000; // tRP ps Precharge command period
|
| 1191 |
|
|
parameter TRPA = 18000; // tRPA ps Precharge All period
|
| 1192 |
|
|
parameter TXARDS = 7; // tXARDS tCK Exit low power active power down to a read command
|
| 1193 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 1194 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 1195 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 1196 |
|
|
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
| 1197 |
|
|
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
| 1198 |
|
|
`else `ifdef sg37E
|
| 1199 |
|
|
parameter TCK_MIN = 3750; // tCK ps Minimum Clock Cycle Time
|
| 1200 |
|
|
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
|
| 1201 |
|
|
parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
|
| 1202 |
|
|
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
|
| 1203 |
|
|
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 1204 |
|
|
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 1205 |
|
|
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 1206 |
|
|
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 1207 |
|
|
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 1208 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 1209 |
|
|
parameter TQHS = 400; // tQHS ps Data hold skew factor
|
| 1210 |
|
|
parameter TAC = 500; // tAC ps DQ output access time from CK/CK#
|
| 1211 |
|
|
parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
|
| 1212 |
|
|
parameter TDH = 225; // tDH ps DQ and DM input hold time relative to DQS
|
| 1213 |
|
|
parameter TDQSCK = 450; // tDQSCK ps DQS output access time from CK/CK#
|
| 1214 |
|
|
parameter TDQSQ = 300; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 1215 |
|
|
parameter TIS = 250; // tIS ps Input Setup Time
|
| 1216 |
|
|
parameter TIH = 375; // tIH ps Input Hold Time
|
| 1217 |
|
|
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
| 1218 |
|
|
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
| 1219 |
|
|
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
| 1220 |
|
|
parameter TRP = 15000; // tRP ps Precharge command period
|
| 1221 |
|
|
parameter TRPA = 18750; // tRPA ps Precharge All period
|
| 1222 |
|
|
parameter TXARDS = 6; // tXARDS tCK Exit low power active power down to a read command
|
| 1223 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 1224 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 1225 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 1226 |
|
|
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
| 1227 |
|
|
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
| 1228 |
|
|
`else `define sg5E
|
| 1229 |
|
|
parameter TCK_MIN = 5000; // tCK ps Minimum Clock Cycle Time
|
| 1230 |
|
|
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
|
| 1231 |
|
|
parameter TJIT_DUTY = 150; // tJIT(duty) ps Half Period Jitter
|
| 1232 |
|
|
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
|
| 1233 |
|
|
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
|
| 1234 |
|
|
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
|
| 1235 |
|
|
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
|
| 1236 |
|
|
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
|
| 1237 |
|
|
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
| 1238 |
|
|
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
| 1239 |
|
|
parameter TQHS = 450; // tQHS ps Data hold skew factor
|
| 1240 |
|
|
parameter TAC = 600; // tAC ps DQ output access time from CK/CK#
|
| 1241 |
|
|
parameter TDS = 150; // tDS ps DQ and DM input setup time relative to DQS
|
| 1242 |
|
|
parameter TDH = 275; // tDH ps DQ and DM input hold time relative to DQS
|
| 1243 |
|
|
parameter TDQSCK = 500; // tDQSCK ps DQS output access time from CK/CK#
|
| 1244 |
|
|
parameter TDQSQ = 350; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
| 1245 |
|
|
parameter TIS = 350; // tIS ps Input Setup Time
|
| 1246 |
|
|
parameter TIH = 475; // tIH ps Input Hold Time
|
| 1247 |
|
|
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
| 1248 |
|
|
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
| 1249 |
|
|
parameter TWTR = 10000; // tWTR ps Write to Read command delay
|
| 1250 |
|
|
parameter TRP = 15000; // tRP ps Precharge command period
|
| 1251 |
|
|
parameter TRPA = 20000; // tRPA ps Precharge All period
|
| 1252 |
|
|
parameter TXARDS = 6; // tXARDS tCK Exit low power active power down to a read command
|
| 1253 |
|
|
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
| 1254 |
|
|
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
| 1255 |
|
|
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
| 1256 |
|
|
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
| 1257 |
|
|
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
| 1258 |
|
|
`endif `endif `endif `endif `endif `endif
|
| 1259 |
|
|
|
| 1260 |
|
|
`ifdef x16
|
| 1261 |
|
|
`ifdef sg187E
|
| 1262 |
|
|
parameter TFAW = 45000; // tFAW ps Four Bank Activate window
|
| 1263 |
|
|
`else `ifdef sg25E
|
| 1264 |
|
|
parameter TFAW = 45000; // tFAW ps Four Bank Activate window
|
| 1265 |
|
|
`else `ifdef sg25
|
| 1266 |
|
|
parameter TFAW = 45000; // tFAW ps Four Bank Activate window
|
| 1267 |
|
|
`else // sg3E, sg3, sg37E, sg5E
|
| 1268 |
|
|
parameter TFAW = 50000; // tFAW ps Four Bank Activate window
|
| 1269 |
|
|
`endif `endif `endif
|
| 1270 |
|
|
`else // x4, x8
|
| 1271 |
|
|
`ifdef sg187E
|
| 1272 |
|
|
parameter TFAW = 35000; // tFAW ps Four Bank Activate window
|
| 1273 |
|
|
`else `ifdef sg25E
|
| 1274 |
|
|
parameter TFAW = 35000; // tFAW ps Four Bank Activate window
|
| 1275 |
|
|
`else `ifdef sg25
|
| 1276 |
|
|
parameter TFAW = 35000; // tFAW ps Four Bank Activate window
|
| 1277 |
|
|
`else // sg3E, sg3, sg37E, sg5E
|
| 1278 |
|
|
parameter TFAW = 37500; // tFAW ps Four Bank Activate window
|
| 1279 |
|
|
`endif `endif `endif
|
| 1280 |
|
|
`endif
|
| 1281 |
|
|
|
| 1282 |
|
|
// Timing Parameters
|
| 1283 |
|
|
|
| 1284 |
|
|
// Mode Register
|
| 1285 |
|
|
parameter AL_MIN = 0; // AL tCK Minimum Additive Latency
|
| 1286 |
|
|
parameter AL_MAX = 6; // AL tCK Maximum Additive Latency
|
| 1287 |
|
|
parameter CL_MIN = 3; // CL tCK Minimum CAS Latency
|
| 1288 |
|
|
parameter CL_MAX = 7; // CL tCK Maximum CAS Latency
|
| 1289 |
|
|
parameter WR_MIN = 2; // WR tCK Minimum Write Recovery
|
| 1290 |
|
|
parameter WR_MAX = 8; // WR tCK Maximum Write Recovery
|
| 1291 |
|
|
parameter BL_MIN = 4; // BL tCK Minimum Burst Length
|
| 1292 |
|
|
parameter BL_MAX = 8; // BL tCK Minimum Burst Length
|
| 1293 |
|
|
// Clock
|
| 1294 |
|
|
parameter TCK_MAX = 8000; // tCK ps Maximum Clock Cycle Time
|
| 1295 |
|
|
parameter TCH_MIN = 0.48; // tCH tCK Minimum Clock High-Level Pulse Width
|
| 1296 |
|
|
parameter TCH_MAX = 0.52; // tCH tCK Maximum Clock High-Level Pulse Width
|
| 1297 |
|
|
parameter TCL_MIN = 0.48; // tCL tCK Minimum Clock Low-Level Pulse Width
|
| 1298 |
|
|
parameter TCL_MAX = 0.52; // tCL tCK Maximum Clock Low-Level Pulse Width
|
| 1299 |
|
|
// Data
|
| 1300 |
|
|
parameter TLZ = TAC; // tLZ ps Data-out low-impedance window from CK/CK#
|
| 1301 |
|
|
parameter THZ = TAC; // tHZ ps Data-out high impedance window from CK/CK#
|
| 1302 |
|
|
parameter TDIPW = 0.35; // tDIPW tCK DQ and DM input Pulse Width
|
| 1303 |
|
|
// Data Strobe
|
| 1304 |
|
|
parameter TDQSH = 0.35; // tDQSH tCK DQS input High Pulse Width
|
| 1305 |
|
|
parameter TDQSL = 0.35; // tDQSL tCK DQS input Low Pulse Width
|
| 1306 |
|
|
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
|
| 1307 |
|
|
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
|
| 1308 |
|
|
parameter TWPRE = 0.35; // tWPRE tCK DQS Write Preamble
|
| 1309 |
|
|
parameter TWPST = 0.40; // tWPST tCK DQS Write Postamble
|
| 1310 |
|
|
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
|
| 1311 |
|
|
// Command and Address
|
| 1312 |
|
|
parameter TIPW = 0.6; // tIPW tCK Control and Address input Pulse Width
|
| 1313 |
|
|
parameter TCCD = 2; // tCCD tCK Cas to Cas command delay
|
| 1314 |
|
|
parameter TRAS_MIN = 40000; // tRAS ps Minimum Active to Precharge command time
|
| 1315 |
|
|
parameter TRAS_MAX =70000000; // tRAS ps Maximum Active to Precharge command time
|
| 1316 |
|
|
parameter TRTP = 7500; // tRTP ps Read to Precharge command delay
|
| 1317 |
|
|
parameter TWR = 15000; // tWR ps Write recovery time
|
| 1318 |
|
|
parameter TMRD = 2; // tMRD tCK Load Mode Register command cycle time
|
| 1319 |
|
|
parameter TDLLK = 200; // tDLLK tCK DLL locking time
|
| 1320 |
|
|
// Refresh
|
| 1321 |
|
|
parameter TRFC_MIN = 197500; // tRFC ps Refresh to Refresh Command interval minimum value
|
| 1322 |
|
|
parameter TRFC_MAX =70000000; // tRFC ps Refresh to Refresh Command Interval maximum value
|
| 1323 |
|
|
// Self Refresh
|
| 1324 |
|
|
parameter TXSNR = TRFC_MIN + 10000; // tXSNR ps Exit self refesh to a non-read command
|
| 1325 |
|
|
parameter TXSRD = 200; // tXSRD tCK Exit self refresh to a read command
|
| 1326 |
|
|
parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit.
|
| 1327 |
|
|
// ODT
|
| 1328 |
|
|
parameter TAOND = 2; // tAOND tCK ODT turn-on delay
|
| 1329 |
|
|
parameter TAOFD = 2.5; // tAOFD tCK ODT turn-off delay
|
| 1330 |
|
|
parameter TAONPD = 2000; // tAONPD ps ODT turn-on (precharge power-down mode)
|
| 1331 |
|
|
parameter TAOFPD = 2000; // tAOFPD ps ODT turn-off (precharge power-down mode)
|
| 1332 |
|
|
parameter TMOD = 12000; // tMOD ps ODT enable in EMR to ODT pin transition
|
| 1333 |
|
|
// Power Down
|
| 1334 |
|
|
parameter TCKE = 3; // tCKE tCK CKE minimum high or low pulse width
|
| 1335 |
|
|
|
| 1336 |
|
|
// Size Parameters based on Part Width
|
| 1337 |
|
|
|
| 1338 |
|
|
`ifdef x4
|
| 1339 |
|
|
parameter ADDR_BITS = 15; // Address Bits
|
| 1340 |
|
|
parameter ROW_BITS = 15; // Number of Address bits
|
| 1341 |
|
|
parameter COL_BITS = 11; // Number of Column bits
|
| 1342 |
|
|
parameter DM_BITS = 1; // Number of Data Mask bits
|
| 1343 |
|
|
parameter DQ_BITS = 4; // Number of Data bits
|
| 1344 |
|
|
parameter DQS_BITS = 1; // Number of Dqs bits
|
| 1345 |
|
|
parameter TRRD = 7500; // tRRD Active bank a to Active bank b command time
|
| 1346 |
|
|
`else `ifdef x8
|
| 1347 |
|
|
parameter ADDR_BITS = 15; // Address Bits
|
| 1348 |
|
|
parameter ROW_BITS = 15; // Number of Address bits
|
| 1349 |
|
|
parameter COL_BITS = 10; // Number of Column bits
|
| 1350 |
|
|
parameter DM_BITS = 1; // Number of Data Mask bits
|
| 1351 |
|
|
parameter DQ_BITS = 8; // Number of Data bits
|
| 1352 |
|
|
parameter DQS_BITS = 1; // Number of Dqs bits
|
| 1353 |
|
|
parameter TRRD = 7500; // tRRD Active bank a to Active bank b command time
|
| 1354 |
|
|
`else `define x16
|
| 1355 |
|
|
parameter ADDR_BITS = 14; // Address Bits
|
| 1356 |
|
|
parameter ROW_BITS = 14; // Number of Address bits
|
| 1357 |
|
|
parameter COL_BITS = 10; // Number of Column bits
|
| 1358 |
|
|
parameter DM_BITS = 2; // Number of Data Mask bits
|
| 1359 |
|
|
parameter DQ_BITS = 16; // Number of Data bits
|
| 1360 |
|
|
parameter DQS_BITS = 2; // Number of Dqs bits
|
| 1361 |
|
|
parameter TRRD = 10000; // tRRD Active bank a to Active bank b command time
|
| 1362 |
|
|
`endif `endif
|
| 1363 |
|
|
|
| 1364 |
|
|
`ifdef QUAD_RANK
|
| 1365 |
|
|
`define DUAL_RANK // also define DUAL_RANK
|
| 1366 |
|
|
parameter CS_BITS = 4; // Number of Chip Select Bits
|
| 1367 |
|
|
parameter RANKS = 4; // Number of Chip Select Bits
|
| 1368 |
|
|
`else `ifdef DUAL_RANK
|
| 1369 |
|
|
parameter CS_BITS = 2; // Number of Chip Select Bits
|
| 1370 |
|
|
parameter RANKS = 2; // Number of Chip Select Bits
|
| 1371 |
|
|
`else
|
| 1372 |
|
|
parameter CS_BITS = 2; // Number of Chip Select Bits
|
| 1373 |
|
|
parameter RANKS = 1; // Number of Chip Select Bits
|
| 1374 |
|
|
`endif `endif
|
| 1375 |
|
|
|
| 1376 |
|
|
// Size Parameters
|
| 1377 |
|
|
parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits
|
| 1378 |
|
|
parameter MEM_BITS = 10; // Number of write data bursts can be stored in memory. The default is 2^10=1024.
|
| 1379 |
|
|
parameter AP = 10; // the address bit that controls auto-precharge and precharge-all
|
| 1380 |
|
|
parameter BL_BITS = 3; // the number of bits required to count to MAX_BL
|
| 1381 |
|
|
parameter BO_BITS = 2; // the number of Burst Order Bits
|
| 1382 |
|
|
|
| 1383 |
|
|
`endif `endif `endif
|
| 1384 |
|
|
|
| 1385 |
|
|
// Simulation parameters
|
| 1386 |
|
|
parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors
|
| 1387 |
|
|
parameter DEBUG = 0; // Turn on Debug messages
|
| 1388 |
|
|
parameter BUS_DELAY = 0; // delay in nanoseconds
|
| 1389 |
|
|
parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
|
| 1390 |
|
|
parameter RANDOM_SEED = 711689044; //seed value for random generator.
|
| 1391 |
|
|
|
| 1392 |
|
|
parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe
|
| 1393 |
|
|
parameter RDQSEN_PST = 1; // DQS driving time after last read strobe
|
| 1394 |
|
|
parameter RDQS_PRE = 2; // DQS low time prior to first read strobe
|
| 1395 |
|
|
parameter RDQS_PST = 1; // DQS low time after last valid read strobe
|
| 1396 |
|
|
parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data
|
| 1397 |
|
|
parameter RDQEN_PST = 0; // DQ/DM driving time after last read data
|
| 1398 |
|
|
parameter WDQS_PRE = 1; // DQS half clock periods prior to first write strobe
|
| 1399 |
|
|
parameter WDQS_PST = 1; // DQS half clock periods after last valid write strobe
|
