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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [bench/] [verilog/] [include/] [eth_stim.v] - Blame information for rev 631

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//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Ethernet MAC Stimulus                                       ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Ethernet MAC stimulus tasks. Taken from the project         ////
7
////  testbench in the ethmac core.                               ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////                                                              ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Tadej Markovic, tadej@opencores.org                   ////
14
////      - Igor Mohor,     igorM@opencores.org                   ////
15
////      - Julius Baxter   julius.baxter@orsoc.se                ////
16
////                                                              ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
`define TIME $display("Time: %0t", $time)
45
 
46
// Defines for ethernet test to trigger sending/receiving
47
// Is straight forward when using RTL design, but if using netlist then paths to
48
// the RX/TX enabled bits depend on synthesis tool, etc, but ones here appear to
49
// work with design put through Synplify, with hierarchy maintained.
50
`define ETH_TOP dut.ethmac0
51
`define ETH_BD_RAM_PATH `ETH_TOP.wishbone.bd_ram
52
`define ETH_MODER_PATH `ETH_TOP.ethreg1.MODER_0
53
 
54
`ifdef RTL_SIM
55
 `ifdef ethmac_IS_GATELEVEL
56
  `define ETH_MODER_TXEN_BIT `ETH_MODER_PATH.r_TxEn;
57
  `define ETH_MODER_RXEN_BIT `ETH_MODER_PATH.r_RxEn;
58
 `else
59
  `define ETH_MODER_TXEN_BIT `ETH_MODER_PATH.DataOut[1];
60
  `define ETH_MODER_RXEN_BIT `ETH_MODER_PATH.DataOut[0];
61
 `endif
62
`endif
63
 
64
`ifdef GATE_SIM
65
 `define ETH_MODER_TXEN_BIT `ETH_MODER_PATH.r_TxEn;
66
 `define ETH_MODER_RXEN_BIT `ETH_MODER_PATH.r_RxEn;
67
`endif
68
 
69
reg [15:0] eth_stim_rx_packet_length;
70
reg [7:0] st_data;
71
reg [31:0] lfsr;
72
integer lfsr_last_byte;
73
 
74
// Is number of ethernet packets to send if doing the eth-rx test.
75
parameter eth_stim_num_rx_only_num_packets = 12; // Set to 0 for continuous RX
76
parameter eth_stim_num_rx_only_packet_size = 60;
77
parameter eth_stim_num_rx_only_packet_size_change = 2'b01;  // 2'b01: Increment
78
parameter eth_stim_num_rx_only_packet_size_change_amount = 127;
79
parameter eth_stim_num_rx_only_IPG = 800_000; // ps
80
 
81
// Do call/response test
82
reg eth_stim_do_rx_reponse_to_tx;
83
reg eth_stim_do_overflow_test;
84
 
85
parameter num_tx_bds = 16;
86
parameter num_tx_bds_mask = 4'hf;
87
parameter num_rx_bds = 16;
88
parameter num_rx_bds_mask = 4'hf;
89
parameter max_eth_packet_size = 16'h0600;
90
 
91
// If running eth-rxtxbig test (sending and receiving maximum packets), then
92
// set this parameter to the max packet size, otherwise min packet size
93
//parameter rx_while_tx_min_packet_size = max_eth_packet_size;
94
parameter rx_while_tx_min_packet_size = 32;
95
 
96
// Use the smallest possible IPG
97
parameter eth_stim_use_min_IPG = 0;
98
parameter eth_stim_IPG_delay_max = 100_000_000; // Maximum 100 us
99
//parameter eth_stim_IPG_delay_max = 100_000_000; // Maximum 100mS between packets
100
parameter eth_stim_IPG_min_10mb = 9600_000; // 9.6 uS
101
parameter eth_stim_IPG_min_100mb = 800_000; // 860+~100 = 960 nS 100MBit min IPG
102
parameter eth_stim_check_rx_packet_contents = 1;
103
parameter eth_stim_check_tx_packet_contents = 1;
104
 
105
parameter eth_inject_errors = 0;
106
 
107
// When running simulations where you don't want to feed packets to the design
108
// like this...
109
parameter eth_stim_disable_rx_stim = 0;
110
 
111
// Delay between seeing that the buffer descriptor for an RX packet says it's
112
// been received and ending up in the memory.
113
// For 25MHz sdram controller, use following:
114
//parameter  Td_rx_packet_check = (`BOARD_CLOCK_PERIOD * 2000);
115
// For 64MHz sdram controller, use following:
116
parameter  Td_rx_packet_check = (`BOARD_CLOCK_PERIOD * 500);
117
 
118
integer expected_rxbd;// init to 0
119
integer expected_txbd;
120
 
121
wire ethmac_rxen;
122
wire ethmac_txen;
123
assign ethmac_rxen = eth_stim_disable_rx_stim ? 0 : `ETH_MODER_RXEN_BIT;
124
assign ethmac_txen = `ETH_MODER_TXEN_BIT;
125
 
126
integer eth_rx_num_packets_sent = 0;
127
integer eth_rx_num_packets_checked = 0;
128
integer num_tx_packets = 1;
129
 
130
integer rx_packet_lengths [0:1023]; // Array of packet lengths
131
 
132
 
133
integer speed_loop;
134
 
135
// When txen is (re)enabled, the tx bd pointer goes back to 0
136
always @(posedge ethmac_txen)
137
  expected_txbd = 0;
138
 
139
   reg  eth_stim_waiting;
140
 
141
initial
142
  begin
143
     #1;
144
     //lfsr = 32'h84218421; // Init pseudo lfsr
145
     lfsr = 32'h00700001; // Init pseudo lfsr
146
     lfsr_last_byte = 0;
147
 
148
     eth_stim_waiting = 1;
149
     expected_rxbd = num_tx_bds; // init this here
150
 
151
     eth_stim_do_rx_reponse_to_tx = 0;
152
     eth_stim_do_overflow_test = 0;
153
 
154
     while (eth_stim_waiting) // Loop, waiting for enabling of MAC by software
155
       begin
156
          #100;
157
          // If RX enable and not TX enable...
158
          if(ethmac_rxen === 1'b1 & !(ethmac_txen===1'b1))
159
            begin
160
               if (eth_inject_errors)
161
                 begin
162
                    do_rx_only_stim(16, 64, 0, 0);
163
                    do_rx_only_stim(128, 64, 1'b1, 8);
164
                    do_rx_only_stim(256, 64, 1'b1, 4);
165
                    eth_stim_waiting = 0;
166
                 end
167
               else
168
                 begin
169
                    //do_rx_only_stim(eth_stim_num_rx_only_num_packets, 
170
                    //eth_stim_num_rx_only_packet_size, 0, 0);
171
 
172
                    // Call packet send loop directly. No error injection.
173
                    send_packet_loop(eth_stim_num_rx_only_num_packets,
174
                                     eth_stim_num_rx_only_packet_size,
175
                                     eth_stim_num_rx_only_packet_size_change,
176
                                     eth_stim_num_rx_only_packet_size_change_amount,
177
                                     eth_phy0.eth_speed,     // Speed
178
                                     eth_stim_num_rx_only_IPG, // IPG
179
                               48'h0012_3456_789a, 48'h0708_090A_0B0C, 1,
180
                               0, 0, 0);
181
 
182
                    eth_stim_waiting = 0;
183
                 end
184
            end // if (ethmac_rxen === 1'b1 & !(ethmac_txen===1'b1))
185
          // If both RX and TX enabled
186
          else if (ethmac_rxen === 1'b1 & ethmac_txen===1'b1)
187
            begin
188
               // Both enabled - let's wait for the first packet transmitted
189
               // to see what stimulus we should provide
190
               while (num_tx_packets==1)
191
                 #1000;
192
 
193
               $display("* ethmac RX/TX test request: %x", eth_phy0.tx_mem[0]);
194
 
195
               // Check the first received byte's value
196
                 case (eth_phy0.tx_mem[0])
197
                   0:
198
                     begin
199
                        // kickoff call/response here
200
                        eth_stim_do_rx_reponse_to_tx = 1;
201
                     end
202
                   1:
203
                     begin
204
                        // kickoff overflow test here
205
                        eth_stim_do_overflow_test = 1;
206
                     end
207
                   default:
208
                     begin
209
                        do_rx_while_tx_stim(1400);
210
                     end
211
                 endcase // case (eth_phy0.tx_mem[0])
212
 
213
               eth_stim_waiting = 0;
214
            end
215
       end // while (eth_stim_waiting)     
216
 
217
  end // initial begin
218
 
219
   // Main Ethernet RX testing stimulus task.
220
   // Sends a set of packets at both speeds
221
   task do_rx_only_stim;
222
      input [31:0] num_packets;
223
      input [31:0] start_packet_size;
224
      input        inject_errors;
225
      input [31:0] inject_errors_mod;
226
 
227
      begin
228
 
229
         for(speed_loop=1;speed_loop<3;speed_loop=speed_loop+1)
230
           begin
231
 
232
              send_packet_loop(num_packets, start_packet_size, 2'b01, 1,
233
                               speed_loop[0], 10000,
234
                               48'h0012_3456_789a, 48'h0708_090A_0B0C, 1,
235
                               inject_errors, inject_errors_mod, 0);
236
 
237
           end
238
 
239
      end
240
   endtask // do_rx_stim
241
 
242
   // Generate RX packets while there's TX going on
243
   // Sends a set of packets at both speeds
244
   task do_rx_while_tx_stim;
245
      input [31:0] num_packets;
246
      reg [31:0] IPG; // Inter-packet gap
247
      reg [31:0] packet_size;
248
 
249
      integer    j;
250
      begin
251
 
252
         for(j=0;j<num_packets;j=j+1)
253
           begin
254
              // Determine delay between RX packets:
255
 
256
              if (eth_stim_use_min_IPG)
257
                begin
258
                   // Assign based on whether we're in 100mbit or 10mbit mode
259
                   IPG = eth_phy0.eth_speed ? eth_stim_IPG_min_100mb :
260
                         eth_stim_IPG_min_10mb;
261
                   // Add a little bit of variability
262
                   // Add up to 15
263
                   IPG = IPG + ($random & 32'h000000f);
264
                end
265
              else
266
                begin
267
                   IPG = $random;
268
 
269
                   while (IPG > eth_stim_IPG_delay_max)
270
                     IPG = IPG / 2;
271
 
272
 
273
                end
274
              $display("do_rx_while_tx IPG = %0d", IPG);
275
              // Determine size of next packet:
276
              if (rx_while_tx_min_packet_size == max_eth_packet_size)
277
                // We want to transmit biggest packets possible, easy case
278
                packet_size = max_eth_packet_size - 4;
279
              else
280
                begin
281
                   // Constrained random sized packets
282
                   packet_size = $random;
283
 
284
                   while (packet_size > (max_eth_packet_size-4))
285
                     packet_size = packet_size / 2;
286
 
287
                   // Now divide by least significant bits of j
288
                   packet_size = packet_size / {29'd0,j[1:0],1'b1};
289
                   if (packet_size < 60)
290
                     packet_size = packet_size + 60;
291
                end
292
 
293
              $display("do_rx_while_tx packet_size = %0d", packet_size);
294
              send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
295
                               IPG, 48'h0012_3456_789a,
296
                               48'h0708_090A_0B0C, 1, 1'b0, 0, 0);
297
 
298
              // If RX enable went low, wait for it go high again
299
              if (ethmac_rxen===1'b0)
300
                begin
301
 
302
                   while (ethmac_rxen===1'b0)
303
                     begin
304
                        @(posedge ethmac_rxen);
305
                        #10000;
306
                     end
307
 
308
                   // RX disabled and when re-enabled we reset the buffer descriptor number
309
                   expected_rxbd = num_tx_bds;
310
 
311
                end
312
 
313
           end // for (j=0;j<num_packets;j=j+1)
314
      end
315
   endtask // do_rx_stim
316
 
317
   // Registers used in detecting transmitted packets
318
   reg eth_stim_tx_loop_keep_polling;
319
   reg [31:0] ethmac_txbd_lenstat, ethmac_last_txbd_lenstat;
320
   reg        eth_stim_detected_packet_tx;
321
 
322
   // If in call-response mode, whenever we receive a TX packet, we generate
323
   // one and send it back
324
   always @(negedge eth_stim_detected_packet_tx)
325
     begin
326
        if (eth_stim_do_rx_reponse_to_tx & ethmac_rxen)
327
          // Continue if we are enabled
328
          do_rx_response_to_tx();
329
     end
330
 
331
 
332
   // If in call-response mode, whenever we receive a TX packet, we generate
333
   // one and send it back
334
   always @(posedge eth_stim_do_overflow_test)
335
     begin
336
          // Continue if we are enabled
337
          do_overflow_stimulus();
338
     end
339
 
340
   // Generate RX packet in rsponse to TX packet
341
   task do_rx_response_to_tx;
342
      //input unused;
343
 
344
     reg [31:0] IPG; // Inter-packet gap
345
      reg [31:0] packet_size;
346
 
347
      integer    j;
348
      begin
349
 
350
         // Get packet size test wants us to send
351
         packet_size = {eth_phy0.tx_mem[0],eth_phy0.tx_mem[1],
352
                        eth_phy0.tx_mem[2],eth_phy0.tx_mem[3]};
353
 
354
 
355
         IPG = {eth_phy0.tx_mem[4],eth_phy0.tx_mem[5],
356
                eth_phy0.tx_mem[6],eth_phy0.tx_mem[7]};
357
 
358
 
359
         $display("do_rx_response_to_tx IPG = %0d", IPG);
360
         if (packet_size == 0)
361
           begin
362
              // Constrained random sized packets
363
              packet_size = $random;
364
 
365
              while (packet_size > (max_eth_packet_size-4))
366
                packet_size = packet_size / 2;
367
 
368
              if (packet_size < 60)
369
                packet_size = packet_size + 60;
370
           end
371
 
372
         $display("do_rx_response_to_tx packet_size = %0d", packet_size);
373
         send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
374
                          IPG, 48'h0012_3456_789a,
375
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 0);
376
 
377
         // If RX enable went low, wait for it go high again
378
         if (ethmac_rxen===1'b0)
379
           begin
380
 
381
              while (ethmac_rxen===1'b0)
382
                begin
383
                   @(posedge ethmac_rxen);
384
                   #10000;
385
                end
386
 
387
              // RX disabled and when re-enabled we reset the buffer 
388
              // descriptor number
389
              expected_rxbd = num_tx_bds;
390
 
391
           end
392
 
393
      end
394
   endtask // do_rx_response_to_tx
395
 
396
   // Generate RX packet in rsponse to TX packet
397
   task do_overflow_stimulus;
398
      //input unused;
399
      reg [31:0] IPG; // Inter-packet gap
400
      reg [31:0] packet_size;
401
 
402
      integer    j;
403
 
404
      begin
405
 
406
         // Maximum packet size
407
         packet_size = 1500;
408
 
409
         // Minimum IPG
410
         IPG = eth_stim_IPG_min_100mb;
411
 
412
         $display("do_overflow_stimulus IPG = %0d", IPG);
413
 
414
 
415
         $display("do_overflow_stimulus packetsize = %0d", packet_size);
416
 
417
         send_packet_loop(num_rx_bds, packet_size, 2'b01, 1,
418
                          eth_phy0.eth_speed,
419
                          IPG, 48'h0012_3456_789a,
420
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 0);
421
 
422
         // This one should cause overflow, don't check it gets there OK
423
         send_packet_loop(1, packet_size, 2'b01, 1,
424
                          eth_phy0.eth_speed,
425
                          IPG, 48'h0012_3456_789a,
426
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 1);
427
 
428
         // Wind back expected RXBD number
429
         if (expected_rxbd == num_tx_bds)
430
           expected_rxbd = num_tx_bds + num_rx_bds - 1;
431
         else
432
           expected_rxbd = expected_rxbd - 1;
433
 
434
         // This one should cause overflow, don't check it gets there OK
435
         send_packet_loop(1, packet_size, 2'b01, 1,
436
                          eth_phy0.eth_speed,
437
                          IPG, 48'h0012_3456_789a,
438
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 1);
439
 
440
         // Wind back expected RXBD number
441
         if (expected_rxbd == num_tx_bds)
442
           expected_rxbd = num_tx_bds + num_rx_bds - 1;
443
         else
444
           expected_rxbd = expected_rxbd - 1;
445
 
446
 
447
         // This one should cause overflow, don't check it gets there OK
448
         send_packet_loop(1, packet_size, 2'b01, 1,
449
                          eth_phy0.eth_speed,
450
                          IPG, 48'h0012_3456_789a,
451
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 1);
452
 
453
         // Wind back expected RXBD number
454
         if (expected_rxbd == num_tx_bds)
455
           expected_rxbd = num_tx_bds + num_rx_bds - 1;
456
         else
457
           expected_rxbd = expected_rxbd - 1;
458
 
459
 
460
         // This one should cause overflow, don't check it gets there OK
461
         send_packet_loop(1, packet_size, 2'b01, 1,
462
                          eth_phy0.eth_speed,
463
                          IPG, 48'h0012_3456_789a,
464
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 1);
465
 
466
         // Wind back expected RXBD number
467
         if (expected_rxbd == num_tx_bds)
468
           expected_rxbd = num_tx_bds + num_rx_bds - 1;
469
         else
470
           expected_rxbd = expected_rxbd - 1;
471
 
472
 
473
         // Wait until a buffer descriptor becomes available
474
         while(`ETH_TOP.wishbone.RxBDRead==1'b1)
475
           #1000;
476
 
477
         $display("%t: RxBDRead gone low",$time);
478
         #10000;
479
 
480
 
481
 
482
         send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
483
                          IPG, 48'h0012_3456_789a,
484
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 0);
485
 
486
 
487
         // If RX enable went low, wait for it go high again
488
         if (ethmac_rxen===1'b0)
489
           begin
490
 
491
              while (ethmac_rxen===1'b0)
492
                begin
493
                   @(posedge ethmac_rxen);
494
                   #10000;
495
                end
496
 
497
              // RX disabled and when re-enabled we reset the buffer 
498
              // descriptor number
499
              expected_rxbd = num_tx_bds;
500
 
501
           end
502
 
503
      end
504
   endtask // do_overflow_stimulus
505
 
506
 
507
   //
508
   // always@() to check the TX buffer descriptors
509
   //
510
   always @(posedge ethmac_txen)
511
     begin
512
         ethmac_last_txbd_lenstat = 0;
513
         eth_stim_tx_loop_keep_polling=1;
514
         // Wait on the TxBD Ready bit
515
         while(eth_stim_tx_loop_keep_polling)
516
           begin
517
              #10;
518
              get_bd_lenstat(expected_txbd, ethmac_txbd_lenstat);
519
              // Check if we've finished transmitting this BD
520
              if (!ethmac_txbd_lenstat[15] & ethmac_last_txbd_lenstat[15])
521
                // Falling edge of TX BD Ready
522
                eth_stim_detected_packet_tx = 1;
523
 
524
              ethmac_last_txbd_lenstat = ethmac_txbd_lenstat;
525
 
526
              // If TX en goes low then exit
527
              if (!ethmac_txen)
528
                eth_stim_tx_loop_keep_polling = 0;
529
              else if (eth_stim_detected_packet_tx)
530
                begin
531
                   // Wait until the eth_phy has finished receiving it
532
                   while (eth_phy0.mtxen_i === 1'b1)
533
                     #10;
534
 
535
                   $display("(%t) Check TX packet: bd %d: 0x%h",$time,
536
                            expected_txbd, ethmac_txbd_lenstat);
537
 
538
                   // Check the TXBD, see if the packet transmitted OK
539
                   if (ethmac_txbd_lenstat[8] | ethmac_txbd_lenstat[3])
540
                     begin
541
                        // Error occured
542
                        `TIME;
543
                        $display("*E TX Error of packet %0d detected.",
544
                                 num_tx_packets);
545
                        $display(" TX BD %0d = 0x%h", expected_txbd,
546
                                 ethmac_txbd_lenstat);
547
                        if (ethmac_txbd_lenstat[8])
548
                          $display(" Underrun in MAC during TX");
549
                        if (ethmac_txbd_lenstat[3])
550
                          $display(" Retransmission limit hit");
551
 
552
                        $finish;
553
                     end
554
                   else
555
                     begin
556
                        // Packet was OK, let's compare the contents we 
557
                        // received with those that were meant to be transmitted
558
                        if (eth_stim_check_tx_packet_contents)
559
                          begin
560
                             check_tx_packet(expected_txbd);
561
                             expected_txbd = (expected_txbd + 1) &
562
                                             num_tx_bds_mask;
563
                             num_tx_packets = num_tx_packets + 1;
564
                             eth_stim_detected_packet_tx = 0;
565
                          end
566
                     end
567
                end
568
           end // while (eth_stim_tx_loop_keep_polling)
569
     end // always @ (posedge ethmac_txen)
570
 
571
 
572
 
573
 
574
`ifdef XILINX_DDR2
575
   // Gets word from correct bank
576
   task get_32bitword_from_xilinx_ddr2;
577
      input [31:0] addr;
578
      output [31:0] insn;
579
      reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,
580
                     ddr2_array_line3;
581
      integer        word_in_line_num;
582
      begin
583
         u_mem0.memory_read(addr[28:27],addr[26:13],
584
                                             {addr[12:6],3'd0},
585
                                             ddr2_array_line0);
586
         insn[31:0] = ddr2_array_line0[31:0];
587
 
588
      end
589
   endtask
590
 
591
   task get_byte_from_xilinx_ddr2;
592
      input [31:0] addr;
593
      output [7:0] data_byte;
594
      reg [31:0]   word;
595
      begin
596
         get_32bitword_from_xilinx_ddr2(addr, word);
597
         case (addr[1:0])
598
           2'b00:
599
             data_byte = word[31:24];
600
           2'b01:
601
             data_byte = word[23:16];
602
           2'b10:
603
             data_byte = word[15:8];
604
           2'b11:
605
             data_byte = word[7:0];
606
         endcase // case (addr[1:0])
607
      end
608
   endtask // get_byte_from_xilinx_ddr2
609
 
610
`endif
611
 
612
`ifdef XILINX_DDR2
613
   task sync_controller_cache_xilinx_ddr;
614
      begin
615
         // Sync cache (writeback dirty lines) with external memory
616
         dut.xilinx_ddr2_0.xilinx_ddr2_if0.do_sync;
617
         // Wait for it to occur.
618
         while (dut.xilinx_ddr2_0.xilinx_ddr2_if0.sync)
619
           #100;
620
 
621
         // Wait just incase writeback of all data hasn't fully occurred.
622
         // 4uS, in case RAM needs to refresh while writing back.
623
         #4_000_000;
624
 
625
 
626
      end
627
   endtask // sync_controller_cache_xilinx_ddr
628
`endif
629
 
630
 
631
   //
632
   // Check packet TX'd by MAC was good
633
   // 
634
   task check_tx_packet;
635
      input [31:0] tx_bd_num;
636
 
637
      reg [31:0]   tx_bd_addr;
638
      reg [7:0]    phy_byte;
639
 
640
      reg [31:0]   txpnt_wb; // Pointer in array to where data should be
641
      reg [24:0]   txpnt_sdram; // Index in array of shorts for data in SDRAM 
642
                                // part
643
      reg [21:0]   buffer;
644
      reg [7:0]    sdram_byte;
645
      reg [31:0]   tx_len_bd;
646
 
647
      integer      i;
648
      integer      failure;
649
      begin
650
         failure = 0;
651
 
652
         get_bd_lenstat(tx_bd_num, tx_len_bd);
653
 
654
         tx_len_bd = {15'd0,tx_len_bd[31:16]};
655
 
656
         // Check, if length didn't have to be padded, that
657
         // amount transmitted was correct
658
         if ((tx_len_bd > 60)&(tx_len_bd != (eth_phy0.tx_len-4)))
659
           begin
660
              $display("*E TX packet sent length, %0d != length in TX BD, %0d",
661
                       eth_phy0.tx_len-4, tx_len_bd);
662
              #100;
663
              $finish;
664
           end
665
 
666
`ifdef XILINX_DDR2
667
         sync_controller_cache_xilinx_ddr;
668
`endif
669
 
670
         get_bd_addr(tx_bd_num, tx_bd_addr);
671
 
672
         // We're never going to be using more than about 256K of receive buffer
673
         // so let's lop off the top bit of the address pointer - we only want
674
         // the offset from the base of the memory bank
675
         txpnt_wb = {14'd0,tx_bd_addr[17:0]};
676
         txpnt_sdram = tx_bd_addr[24:0];
677
 
678
         // Variable we'll use for index in the PHY's TX buffer
679
         buffer = 0; // Start of TX data
680
 
681
         for (i=0;i<tx_len_bd;i=i+1)
682
           begin
683
              //$display("Checking address in tx bd 0x%0h",txpnt_sdram);
684
              sdram_byte = 8'hx;
685
`ifdef RAM_WB
686
              sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_mem8(txpnt_sdram);
687
`else
688
 `ifdef VERSATILE_SDRAM
689
              sdram0.get_byte(txpnt_sdram,sdram_byte);
690
 `else
691
  `ifdef XILINX_DDR2
692
              get_byte_from_xilinx_ddr2(txpnt_sdram, sdram_byte);
693
  `else
694
              $display(" * Error: sdram_byte was %x", sdram_byte);
695
 
696
              $display(" * eth_stim needs to be able to access the main memory to check packet rx/tx");
697
              $finish;
698
 
699
  `endif
700
 `endif
701
`endif
702
 
703
              phy_byte = eth_phy0.tx_mem[buffer];
704
              // Debugging output
705
              //$display("txpnt_sdram = 0x%h, sdram_byte = 0x%h, buffer = 0x%h, phy_byte = 0x%h", txpnt_sdram,  sdram_byte, buffer, phy_byte);
706
 
707
              if (phy_byte !== sdram_byte)
708
                begin
709
                   `TIME;
710
                   $display("*E Wrong byte (%d) of TX packet! ram = %h, phy = %h",buffer, sdram_byte, phy_byte);
711
                   failure = 1;
712
                end
713
 
714
              buffer = buffer + 1;
715
 
716
              txpnt_sdram = txpnt_sdram+1;
717
 
718
           end // for (i=0;i<tx_len_bd;i=i+1)
719
 
720
         if (failure)
721
           begin
722
              #100
723
                `TIME;
724
              $display("*E Error transmitting packet %0d (%0d bytes). Finishing simulation", num_tx_packets, tx_len_bd);
725
              get_bd_lenstat(tx_bd_num, tx_len_bd);
726
              $display("   TXBD lenstat: 0x%0h",tx_len_bd);
727
              $display("   TXBD address: 0x%0h",tx_bd_addr);
728
              $finish;
729
           end
730
         else
731
           begin
732
              #1 $display( "(%0t)(%m) TX packet %0d: %0d bytes in memory OK!",$time,num_tx_packets, tx_len_bd);
733
 
734
           end
735
 
736
 
737
      end
738
   endtask // check_tx_packet
739
 
740
 
741
   // Local buffer of "sent" data to the ethernet MAC, we will check against
742
   // Size of our local buffer in bytes
743
   parameter eth_rx_sent_circbuf_size = (16*1024);
744
   parameter eth_rx_sent_circbuf_size_mask = eth_rx_sent_circbuf_size - 1;
745
   integer eth_rx_sent_circbuf_fill_ptr = 0;
746
   integer eth_rx_sent_circbuf_read_ptr = 0;
747
   // The actual buffer
748
   reg [7:0] eth_rx_sent_circbuf [0:eth_rx_sent_circbuf_size-1];
749
 
750
 
751
   //
752
   // Task to send a set of packets
753
   //
754
   task send_packet_loop;
755
      input [31:0] num_packets;
756
      input [31:0] length;
757
      input [1:0]  length_change; // 0 = none, 1 = incr, 2 = decrement
758
      input [31:0] length_change_size; // Size to change by
759
      input        speed;
760
      input [31:0] back_to_back_delay; // #delay setting between packets
761
      input [47:0] dst_mac;
762
      input [47:0] src_mac;
763
      input        random_fill;
764
      input        random_errors;
765
      input [31:0] random_error_mod;
766
      input        dont_confirm_rx;
767
      integer      j, k;
768
      reg          error_this_time;
769
      integer      error_type; // 0 = rxerr, 1=bad preamble 2=bad crc 3=TODO
770
      reg [31:0]   rx_bd_lenstat;
771
      begin
772
         error_type = 0;
773
         error_this_time = 0;
774
 
775
         if (num_packets == 0)
776
           // Loop forever when num_packets is 0
777
           num_packets = 32'h7fffffff;
778
 
779
 
780
         if (speed & !(eth_phy0.control_bit14_10[13] === 1'b1))
781
           begin
782
              // write to phy's control register for 100Mbps
783
              eth_phy0.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
784
              // Swapping speeds, give some delay
785
              #10000;
786
           end
787
         else if (!speed & !(eth_phy0.control_bit14_10[13] === 1'b0))
788
           begin
789
              eth_phy0.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
790
              // Swapping speeds, give some delay
791
              #10000;
792
           end
793
 
794
         eth_phy0.control_bit8_0   = 9'h1_00;
795
 
796
         for(j=0;j<num_packets | length <32;j=j+1)
797
           begin
798
              eth_stim_rx_packet_length = length[15:0]; // Bytes
799
              st_data = 8'h0F;
800
 
801
              // setup RX packet in buffer - length is without CRC
802
              set_rx_packet(0, eth_stim_rx_packet_length, 1'b0, dst_mac,
803
                            src_mac, 16'h0D0E, st_data, random_fill);
804
 
805
              set_rx_addr_type(0, dst_mac, src_mac, 16'h0D0E);
806
 
807
              // Error type 2 is cause CRC error
808
              append_rx_crc(0, eth_stim_rx_packet_length, 1'b0,
809
                            (error_type==2));
810
 
811
              if (error_this_time)
812
                begin
813
                   if (error_type == 0)
814
                     // RX ERR assert during transmit
815
                     eth_phy0.send_rx_packet(64'h0055_5555_5555_5555, 4'h7,
816
                                             8'hD5, 0,
817
                                             eth_stim_rx_packet_length+4,
818
                                             1'b0, 1'b1);
819
                   else if (error_type == 1)
820
                     // Incorrect preamble
821
                     eth_phy0.send_rx_packet(64'h0055_5f55_5555_5555, 4'h7,
822
                                             8'hD5, 0,
823
                                             eth_stim_rx_packet_length+4,
824
                                             1'b0, 1'b0);
825
                   else
826
                     // Normal datapacket
827
                     eth_phy0.send_rx_packet(64'h0055_5555_5555_5555, 4'h7,
828
                                             8'hD5, 0,
829
                                             eth_stim_rx_packet_length+4,
830
                                             1'b0, 1'b0);
831
                end
832
              else
833
                eth_phy0.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5,
834
                                        0, eth_stim_rx_packet_length+4, 1'b0,
835
                                        1'b0);
836
 
837
 
838
              // if RX enable still set (might have gone low during this packet
839
              if (ethmac_rxen)
840
                begin
841
                   if (error_this_time || dont_confirm_rx) begin
842
                     // Put in dummy length, checking function will skip...
843
                     rx_packet_lengths[(eth_rx_num_packets_sent& 12'h3ff)]=32'heeeeeeee;
844
 
845
                      for(k=0;k<length;k=k+1)
846
                      // skip data  in verify buffer
847
                        eth_rx_sent_circbuf_read_ptr = (eth_rx_sent_circbuf_read_ptr+1)&
848
                                                       eth_rx_sent_circbuf_size_mask;
849
 
850
                   end
851
                   else
852
                     rx_packet_lengths[(eth_rx_num_packets_sent & 12'h3ff)] = length;
853
 
854
                   eth_rx_num_packets_sent = eth_rx_num_packets_sent + 1;
855
 
856
                end // if (ethmac_rxen)
857
              else
858
                begin
859
                   // Force the loop to finish up                  
860
                   j = num_packets;
861
                end
862
 
863
 
864
              // Inter-packet gap
865
              #back_to_back_delay;
866
 
867
              // Update length
868
              if (length_change == 2'b01)
869
                length = length + length_change_size;
870
 
871
              if ((length_change == 2'b10) &&
872
                  ((length - length_change_size) > 32))
873
                length = length - length_change_size;
874
 
875
              // Increment error type
876
              if (error_this_time)
877
                error_type = error_type + 1;
878
              if (error_type > 3)
879
                error_type = 0;
880
 
881
 
882
              // Check if we should put in an error this time
883
              if (j%random_error_mod == 0)
884
                error_this_time = 1;
885
              else
886
                error_this_time = 0;
887
 
888
              eth_phy0.rx_err(0);
889
 
890
              // Now wait to check if we have filled up all the RX BDs and
891
              // the this packet would start writing over them. Only really an
892
              // issue when doing minimum IPG tests.
893
              while(((eth_rx_num_packets_sent+1) - eth_rx_num_packets_checked)
894
                    == num_rx_bds)
895
                #100;
896
 
897
 
898
           end // for (j=0;j<num_packets | length <32;j=j+1)
899
      end
900
   endtask // send_packet_loop
901
 
902
   /*
903
    TASKS for set and check RX packets:
904
    -----------------------------------
905
    set_rx_packet
906
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
907
    check_rx_packet
908
    (rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
909
    */
910
   task set_rx_packet;
911
      input  [31:0] rxpnt; // pointer to place in in the phy rx buffer we'll start at
912
      input [15:0]  len;
913
      input         plus_dribble_nibble; // if length is longer for one nibble
914
      input [47:0]  eth_dest_addr;
915
      input [47:0]  eth_source_addr;
916
      input [15:0]  eth_type_len;
917
      input [7:0]   eth_start_data;
918
      input         random_fill;
919
      integer       i, sd;
920
      reg [47:0]    dest_addr;
921
      reg [47:0]    source_addr;
922
      reg [15:0]    type_len;
923
      reg [21:0]    buffer;
924
      reg           delta_t;
925
 
926
      begin
927
         buffer = rxpnt[21:0];
928
         dest_addr = eth_dest_addr;
929
         source_addr = eth_source_addr;
930
         type_len = eth_type_len;
931
         sd = eth_start_data;
932
         delta_t = 0;
933
         for(i = 0; i < len; i = i + 1)
934
           begin
935
              if (i < 6)
936
                begin
937
                   eth_phy0.rx_mem[buffer] = dest_addr[47:40];
938
                   dest_addr = dest_addr << 8;
939
                end
940
              else if (i < 12)
941
                begin
942
                   eth_phy0.rx_mem[buffer] = source_addr[47:40];
943
                   source_addr = source_addr << 8;
944
                end
945
              else if (i < 14)
946
                begin
947
                   eth_phy0.rx_mem[buffer] = type_len[15:8];
948
                   type_len = type_len << 8;
949
                end
950
              else
951
                begin
952
                   if (random_fill)
953
                     begin
954
                        if (lfsr_last_byte == 0)
955
                          eth_phy0.rx_mem[buffer] = lfsr[15:8];
956
                        if (lfsr_last_byte == 1)
957
                          eth_phy0.rx_mem[buffer] = lfsr[23:16];
958
                        if (lfsr_last_byte == 2)
959
                          eth_phy0.rx_mem[buffer] = lfsr[31:24];
960
                        if (lfsr_last_byte == 3)
961
                          begin
962
                             eth_phy0.rx_mem[buffer] = lfsr[7:0];
963
                             lfsr = {lfsr[30:0],(((lfsr[31] ^ lfsr[6]) ^
964
                                                  lfsr[5]) ^ lfsr[1])};
965
                             lfsr_last_byte =  0;
966
                          end
967
                        else
968
                          lfsr_last_byte = lfsr_last_byte + 1;
969
 
970
                     end // if (random_fill)               
971
                   else
972
                     eth_phy0.rx_mem[buffer] = sd[7:0];
973
                   sd = sd + 1;
974
                end // else: !if(i < 14)
975
 
976
              // Update our local buffer
977
              eth_rx_sent_circbuf[eth_rx_sent_circbuf_fill_ptr]
978
                = eth_phy0.rx_mem[buffer];
979
              eth_rx_sent_circbuf_fill_ptr = (eth_rx_sent_circbuf_fill_ptr+1)&
980
                                             eth_rx_sent_circbuf_size_mask;
981
 
982
              buffer = buffer + 1;
983
           end // for (i = 0; i < len; i = i + 1)
984
 
985
         delta_t = !delta_t;
986
         if (plus_dribble_nibble)
987
           eth_phy0.rx_mem[buffer] = {4'h0, 4'hD /*sd[3:0]*/};
988
         delta_t = !delta_t;
989
      end
990
   endtask // set_rx_packet
991
 
992
 
993
 
994
 
995
   task set_rx_addr_type;
996
      input  [31:0] rxpnt;
997
      input [47:0]  eth_dest_addr;
998
      input [47:0]  eth_source_addr;
999
      input [15:0]  eth_type_len;
1000
      integer       i;
1001
      reg [47:0]    dest_addr;
1002
      reg [47:0]    source_addr;
1003
      reg [15:0]    type_len;
1004
      reg [21:0]    buffer;
1005
      reg           delta_t;
1006
      begin
1007
         buffer = rxpnt[21:0];
1008
         dest_addr = eth_dest_addr;
1009
         source_addr = eth_source_addr;
1010
         type_len = eth_type_len;
1011
         delta_t = 0;
1012
         for(i = 0; i < 14; i = i + 1)
1013
           begin
1014
              if (i < 6)
1015
                begin
1016
                   eth_phy0.rx_mem[buffer] = dest_addr[47:40];
1017
                   dest_addr = dest_addr << 8;
1018
                end
1019
              else if (i < 12)
1020
                begin
1021
                   eth_phy0.rx_mem[buffer] = source_addr[47:40];
1022
                   source_addr = source_addr << 8;
1023
                end
1024
              else // if (i < 14)
1025
                begin
1026
                   eth_phy0.rx_mem[buffer] = type_len[15:8];
1027
                   type_len = type_len << 8;
1028
                end
1029
              buffer = buffer + 1;
1030
           end
1031
         delta_t = !delta_t;
1032
      end
1033
   endtask // set_rx_addr_type
1034
 
1035
 
1036
   // Check if we're using a synthesized version of eth module
1037
`ifdef ethmac_IS_GATELEVEL
1038
 
1039
   // Get the length/status register of the ethernet buffer descriptor
1040
   task get_bd_lenstat;
1041
      input [31:0] bd_num;// Number of ethernet BD to check
1042
      output [31:0] bd_lenstat;
1043
 `ifdef ACTEL
1044
      reg [8:0]    tmp;
1045
      integer      raddr;
1046
 `endif
1047
      begin
1048
 `ifdef ACTEL
1049
 
1050
         // Pull from the Actel memory model
1051
         raddr = `ETH_BD_RAM_PATH.\mem_tile.I_1 .get_address((bd_num*2));
1052
 
1053
         tmp = `ETH_BD_RAM_PATH.\mem_tile.I_1 .MEM_512_9[(raddr*2)];
1054
         bd_lenstat[8:0] = tmp[8:0];
1055
 
1056
         tmp = `ETH_BD_RAM_PATH.\mem_tile.I_1 .MEM_512_9[(raddr*2)+1];
1057
         bd_lenstat[17:9] = tmp[8:0];
1058
 
1059
         raddr = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .get_address((bd_num*2));
1060
 
1061
         tmp = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .MEM_512_9[(raddr*2)];
1062
         bd_lenstat[26:18] = tmp[8:0];
1063
 
1064
         tmp = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .MEM_512_9[(raddr*2)+1];
1065
         bd_lenstat[31:27] = tmp[4:0];
1066
 
1067
         //$display("(%t) read eth bd lenstat %h",$time, bd_lenstat);
1068
 `endif
1069
      end
1070
   endtask // get_bd_lenstat
1071
 
1072
   // Get the length/status register of the ethernet buffer descriptor
1073
   task get_bd_addr;
1074
      input [31:0] bd_num;// Number of the ethernet BD to check
1075
      output [31:0] bd_addr;
1076
 `ifdef ACTEL
1077
      reg [8:0]    tmp;
1078
      integer       raddr;
1079
 `endif
1080
      begin
1081
 `ifdef ACTEL
1082
         // Pull from the Actel memory model
1083
         raddr = `ETH_BD_RAM_PATH.\mem_tile.I_1 .get_address((bd_num*2)+1);
1084
 
1085
         tmp = `ETH_BD_RAM_PATH.\mem_tile.I_1 .MEM_512_9[(raddr*2)];
1086
         bd_addr[8:0] = tmp[8:0];
1087
 
1088
         tmp = `ETH_BD_RAM_PATH.\mem_tile.I_1 .MEM_512_9[(raddr*2)+1];
1089
         bd_addr[17:9] = tmp[8:0];
1090
 
1091
         raddr = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .get_address((bd_num*2)+1);
1092
 
1093
         tmp = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .MEM_512_9[(raddr*2)];
1094
         bd_addr[26:18] = tmp[8:0];
1095
 
1096
         tmp = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .MEM_512_9[(raddr*2)+1];
1097
         bd_addr[31:27] = tmp[4:0];
1098
 
1099
         //$display("(%t) read eth bd%d addr %h",$time,bd_num, bd_addr);
1100
 `endif
1101
      end
1102
   endtask // get_bd_addr
1103
 
1104
`else // !`ifdef ethmac_IS_GATELEVEL
1105
 
1106
   // Get the length/status register of the ethernet buffer descriptor
1107
   task get_bd_lenstat;
1108
      input [31:0] bd_num;// Number of ethernet BD to check
1109
      output [31:0] bd_lenstat;
1110
      begin
1111
         bd_lenstat = `ETH_BD_RAM_PATH.mem[(bd_num*2)];
1112
      end
1113
   endtask // get_bd_lenstat
1114
 
1115
   // Get the length/status register of the ethernet buffer descriptor
1116
   task get_bd_addr;
1117
      input [31:0] bd_num;// Number of the ethernet BD to check
1118
      output [31:0] bd_addr;
1119
      begin
1120
         bd_addr = `ETH_BD_RAM_PATH.mem[((bd_num*2)+1)];
1121
         //$display("(%t) read eth bd%d addr %h",$time,bd_num, bd_addr);
1122
      end
1123
   endtask // get_bd_addr
1124
`endif
1125
 
1126
   // Always block triggered by finishing of transmission of new packet from 
1127
   // send_packet_loop
1128
   integer eth_rx_packet_length_to_check;
1129
 
1130
   always @*
1131
     begin
1132
        // Loop here until:
1133
        // 1 - packets sent is not equal to packets checked (ie. some to check)
1134
        // 2 - we're explicitly disabled for some reason
1135
        // 3 - Receive has been disabled in the MAC
1136
        while((eth_rx_num_packets_sent == eth_rx_num_packets_checked) ||
1137
              !eth_stim_check_rx_packet_contents || !(ethmac_rxen===1'b1))
1138
          #1000;
1139
 
1140
        eth_rx_packet_length_to_check
1141
          = rx_packet_lengths[(eth_rx_num_packets_checked & 12'h3ff)];
1142
 
1143
        if ( eth_rx_packet_length_to_check !==  32'heeeeeeee)
1144
          check_rx_packet(expected_rxbd, 0, eth_rx_packet_length_to_check);
1145
 
1146
        eth_rx_num_packets_checked = eth_rx_num_packets_checked + 1;
1147
 
1148
        expected_rxbd = expected_rxbd + 1;
1149
 
1150
        // Wrap
1151
        if (expected_rxbd == (num_tx_bds + num_rx_bds))
1152
          expected_rxbd = num_tx_bds;
1153
     end
1154
 
1155
   task check_rx_packet;
1156
 
1157
      input [31:0] rx_bd_num;
1158
      input [31:0] rxpnt_phy; // Pointer in array of data in PHY
1159
      input [31:0] len;
1160
 
1161
      reg [31:0]   rx_bd_lenstat;
1162
      reg [31:0]   rx_bd_addr;
1163
      reg [7:0]    phy_byte;
1164
 
1165
      reg [31:0]   rxpnt_wb; // Pointer in array to where data should be
1166
      reg [24:0]   rxpnt_sdram; // byte address from CPU in RAM
1167
      reg [15:0]   sdram_short;
1168
      reg [7:0]    sdram_byte;
1169
 
1170
      integer      i;
1171
      integer      failure;
1172
 
1173
      begin
1174
 
1175
         failure = 0;
1176
 
1177
         // Wait until the buffer descriptor indicates the packet has been 
1178
         // received...
1179
         get_bd_lenstat(rx_bd_num, rx_bd_lenstat);
1180
         while (rx_bd_lenstat & 32'h00008000)// Check Empty bit
1181
           begin
1182
              #10;
1183
              get_bd_lenstat(rx_bd_num, rx_bd_lenstat);
1184
              //$display("(%t) check_rx_packet: poll bd %d: 0x%h",$time,
1185
                //        rx_bd_num, rx_bd_lenstat);
1186
           end
1187
 
1188
 
1189
         // Delay some time - takes a bit for the Wishbone FSM to pipe out the
1190
         // packet over Wishbone and into whatever memory it's going into
1191
         #Td_rx_packet_check;
1192
 
1193
`ifdef XILINX_DDR2
1194
         sync_controller_cache_xilinx_ddr;
1195
`endif
1196
 
1197
         // Ok, buffer filled, let's get its offset in memory
1198
         get_bd_addr(rx_bd_num, rx_bd_addr);
1199
 
1200
         $display("(%t) Check RX packet: bd %d: 0x%h, addr 0x%h",$time,
1201
                  rx_bd_num, rx_bd_lenstat, rx_bd_addr);
1202
 
1203
 
1204
         // We're never going to be using more than about 256KB of receive buffer
1205
         // so let's lop off the top bit of the address pointer - we only want
1206
         // the offset from the base of the memory bank
1207
 
1208
         rxpnt_wb = {14'd0,rx_bd_addr[17:0]};
1209
         rxpnt_sdram = rx_bd_addr[24:0];
1210
 
1211
 
1212
         //$display("RAM pointer for BD is 0x%h, SDRAM addr is 0x%h", rx_bd_addr, rxpnt_sdram);
1213
 
1214
 
1215
         for (i=0;i<len;i=i+1)
1216
           begin
1217
 
1218
              sdram_byte = 8'hx;
1219
 
1220
`ifdef RAM_WB
1221
              sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_mem8(rxpnt_sdram);
1222
`else
1223
 `ifdef XILINX_DDR2
1224
              get_byte_from_xilinx_ddr2(rxpnt_sdram, sdram_byte);
1225
 `else
1226
              $display(" * Error:");
1227
 
1228
              $display(" * eth_stim needs to be able to access the main memory to check packet rx/tx");
1229
              $finish;
1230
 `endif
1231
`endif
1232
 
1233
              phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr];
1234
 
1235
              if (phy_byte !== sdram_byte)
1236
                begin
1237
//                 `TIME;                 
1238
                   $display("*E Wrong byte (%5d) of RX packet %5d. phy mem = %h, ram = %h",
1239
                            i, eth_rx_num_packets_checked, phy_byte, sdram_byte);
1240
                   failure = 1;
1241
                end
1242
 
1243
              eth_rx_sent_circbuf_read_ptr = (eth_rx_sent_circbuf_read_ptr+1)&
1244
                                             eth_rx_sent_circbuf_size_mask;
1245
 
1246
              rxpnt_sdram = rxpnt_sdram+1;
1247
 
1248
           end // for (i=0;i<len;i=i+2)
1249
 
1250
         if (failure)
1251
           begin
1252
              #100
1253
                `TIME;
1254
              $display("*E Recieved packet %0d, length %0d bytes, had an error. Finishing simulation.", eth_rx_num_packets_checked, len);
1255
              $finish;
1256
           end
1257
         else
1258
           begin
1259
              #1 $display( "(%0t)(%m) RX packet %0d: %0d bytes in memory OK!",$time,eth_rx_num_packets_checked, len);
1260
 
1261
           end
1262
      end
1263
   endtask // check_rx_packet
1264
 
1265
 
1266
   //////////////////////////////////////////////////////////////
1267
   // Ethernet CRC Basic tasks
1268
   //////////////////////////////////////////////////////////////
1269
 
1270
   task append_rx_crc;
1271
      input  [31:0] rxpnt_phy; // source
1272
      input [15:0]  len; // length in bytes without CRC
1273
      input         plus_dribble_nibble; // if length is longer for one nibble
1274
      input         negated_crc; // if appended CRC is correct or not
1275
      reg [31:0]    crc;
1276
      reg [7:0]     tmp;
1277
      reg [31:0]    addr_phy;
1278
      reg           delta_t;
1279
      begin
1280
         addr_phy = rxpnt_phy + len;
1281
         delta_t = 0;
1282
         // calculate CRC from prepared packet
1283
         paralel_crc_phy_rx(rxpnt_phy, {16'h0, len}, plus_dribble_nibble, crc);
1284
         if (negated_crc)
1285
           crc = ~crc;
1286
         delta_t = !delta_t;
1287
 
1288
         if (plus_dribble_nibble)
1289
           begin
1290
              tmp = eth_phy0.rx_mem[addr_phy];
1291
              eth_phy0.rx_mem[addr_phy]     = {crc[27:24], tmp[3:0]};
1292
              eth_phy0.rx_mem[addr_phy + 1] = {crc[19:16], crc[31:28]};
1293
              eth_phy0.rx_mem[addr_phy + 2] = {crc[11:8], crc[23:20]};
1294
              eth_phy0.rx_mem[addr_phy + 3] = {crc[3:0], crc[15:12]};
1295
              eth_phy0.rx_mem[addr_phy + 4] = {4'h0, crc[7:4]};
1296
           end
1297
         else
1298
           begin
1299
              eth_phy0.rx_mem[addr_phy]     = crc[31:24];
1300
              eth_phy0.rx_mem[addr_phy + 1] = crc[23:16];
1301
              eth_phy0.rx_mem[addr_phy + 2] = crc[15:8];
1302
              eth_phy0.rx_mem[addr_phy + 3] = crc[7:0];
1303
           end
1304
      end
1305
   endtask // append_rx_crc
1306
 
1307
   task append_rx_crc_delayed;
1308
      input  [31:0] rxpnt_phy; // source
1309
      input [15:0]  len; // length in bytes without CRC
1310
      input         plus_dribble_nibble; // if length is longer for one nibble
1311
      input         negated_crc; // if appended CRC is correct or not
1312
      reg [31:0]    crc;
1313
      reg [7:0]     tmp;
1314
      reg [31:0]    addr_phy;
1315
      reg           delta_t;
1316
      begin
1317
         addr_phy = rxpnt_phy + len;
1318
         delta_t = 0;
1319
         // calculate CRC from prepared packet
1320
         paralel_crc_phy_rx(rxpnt_phy+4, {16'h0, len}-4, plus_dribble_nibble, crc);
1321
         if (negated_crc)
1322
           crc = ~crc;
1323
         delta_t = !delta_t;
1324
 
1325
         if (plus_dribble_nibble)
1326
           begin
1327
              tmp = eth_phy0.rx_mem[addr_phy];
1328
              eth_phy0.rx_mem[addr_phy]     = {crc[27:24], tmp[3:0]};
1329
              eth_phy0.rx_mem[addr_phy + 1] = {crc[19:16], crc[31:28]};
1330
              eth_phy0.rx_mem[addr_phy + 2] = {crc[11:8], crc[23:20]};
1331
              eth_phy0.rx_mem[addr_phy + 3] = {crc[3:0], crc[15:12]};
1332
              eth_phy0.rx_mem[addr_phy + 4] = {4'h0, crc[7:4]};
1333
           end
1334
         else
1335
           begin
1336
              eth_phy0.rx_mem[addr_phy]     = crc[31:24];
1337
              eth_phy0.rx_mem[addr_phy + 1] = crc[23:16];
1338
              eth_phy0.rx_mem[addr_phy + 2] = crc[15:8];
1339
              eth_phy0.rx_mem[addr_phy + 3] = crc[7:0];
1340
           end
1341
      end
1342
   endtask // append_rx_crc_delayed
1343
 
1344
 
1345
   // paralel CRC calculating for PHY RX
1346
   task paralel_crc_phy_rx;
1347
      input  [31:0] start_addr; // start address
1348
      input [31:0]  len; // length of frame in Bytes without CRC length
1349
      input         plus_dribble_nibble; // if length is longer for one nibble
1350
      output [31:0] crc_out;
1351
      reg [21:0]    addr_cnt; // only 22 address lines
1352
      integer       word_cnt;
1353
      integer       nibble_cnt;
1354
      reg [31:0]    load_reg;
1355
      reg           delta_t;
1356
      reg [31:0]    crc_next;
1357
      reg [31:0]    crc;
1358
      reg           crc_error;
1359
      reg [3:0]     data_in;
1360
      integer       i;
1361
      begin
1362
         #1 addr_cnt = start_addr[21:0];
1363
         word_cnt = 24; // 27; // start of the frame - nibble granularity (MSbit first)
1364
         crc = 32'hFFFF_FFFF; // INITIAL value
1365
         delta_t = 0;
1366
         // length must include 4 bytes of ZEROs, to generate CRC
1367
         // get number of nibbles from Byte length (2^1 = 2)
1368
         if (plus_dribble_nibble)
1369
           nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
1370
         else
1371
           nibble_cnt = ((len + 4) << 1);
1372
         // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
1373
         load_reg[31:24] = eth_phy0.rx_mem[addr_cnt];
1374
         addr_cnt = addr_cnt + 1;
1375
         load_reg[23:16] = eth_phy0.rx_mem[addr_cnt];
1376
         addr_cnt = addr_cnt + 1;
1377
         load_reg[15: 8] = eth_phy0.rx_mem[addr_cnt];
1378
         addr_cnt = addr_cnt + 1;
1379
         load_reg[ 7: 0] = eth_phy0.rx_mem[addr_cnt];
1380
         addr_cnt = addr_cnt + 1;
1381
         while (nibble_cnt > 0)
1382
           begin
1383
              // wait for delta time
1384
              delta_t = !delta_t;
1385
              // shift data in
1386
 
1387
              if(nibble_cnt <= 8) // for additional 8 nibbles shift ZEROs in!
1388
                data_in[3:0] = 4'h0;
1389
              else
1390
 
1391
                data_in[3:0] = {load_reg[word_cnt], load_reg[word_cnt+1], load_reg[word_cnt+2], load_reg[word_cnt+3]};
1392
              crc_next[0]  = (data_in[0] ^ crc[28]);
1393
              crc_next[1]  = (data_in[1] ^ data_in[0] ^ crc[28]    ^ crc[29]);
1394
              crc_next[2]  = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]);
1395
              crc_next[3]  = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]);
1396
              crc_next[4]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[0];
1397
              crc_next[5]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[1];
1398
              crc_next[6]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[ 2];
1399
              crc_next[7]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[3];
1400
              crc_next[8]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[4];
1401
              crc_next[9]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[5];
1402
              crc_next[10] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[6];
1403
              crc_next[11] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[7];
1404
              crc_next[12] = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]) ^ crc[8];
1405
              crc_next[13] = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]) ^ crc[9];
1406
              crc_next[14] = (data_in[3] ^ data_in[2] ^ crc[30]    ^ crc[31]) ^ crc[10];
1407
              crc_next[15] = (data_in[3] ^ crc[31])   ^ crc[11];
1408
              crc_next[16] = (data_in[0] ^ crc[28])   ^ crc[12];
1409
              crc_next[17] = (data_in[1] ^ crc[29])   ^ crc[13];
1410
              crc_next[18] = (data_in[2] ^ crc[30])   ^ crc[14];
1411
              crc_next[19] = (data_in[3] ^ crc[31])   ^ crc[15];
1412
              crc_next[20] =  crc[16];
1413
              crc_next[21] =  crc[17];
1414
              crc_next[22] = (data_in[0] ^ crc[28])   ^ crc[18];
1415
              crc_next[23] = (data_in[1] ^ data_in[0] ^ crc[29]    ^ crc[28]) ^ crc[19];
1416
              crc_next[24] = (data_in[2] ^ data_in[1] ^ crc[30]    ^ crc[29]) ^ crc[20];
1417
              crc_next[25] = (data_in[3] ^ data_in[2] ^ crc[31]    ^ crc[30]) ^ crc[21];
1418
              crc_next[26] = (data_in[3] ^ data_in[0] ^ crc[31]    ^ crc[28]) ^ crc[22];
1419
              crc_next[27] = (data_in[1] ^ crc[29])   ^ crc[23];
1420
              crc_next[28] = (data_in[2] ^ crc[30])   ^ crc[24];
1421
              crc_next[29] = (data_in[3] ^ crc[31])   ^ crc[25];
1422
              crc_next[30] =  crc[26];
1423
              crc_next[31] =  crc[27];
1424
 
1425
              crc = crc_next;
1426
              crc_error = crc[31:0] != 32'hc704dd7b;  // CRC not equal to magic number
1427
              case (nibble_cnt)
1428
                9: crc_out = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
1429
                              !crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
1430
                              !crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
1431
                              !crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
1432
                default: crc_out = crc_out;
1433
              endcase
1434
              // wait for delta time
1435
              delta_t = !delta_t;
1436
              // increment address and load new data
1437
              if ((word_cnt+3) == 7)//4)
1438
                begin
1439
                   // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
1440
                   load_reg[31:24] = eth_phy0.rx_mem[addr_cnt];
1441
                   addr_cnt = addr_cnt + 1;
1442
                   load_reg[23:16] = eth_phy0.rx_mem[addr_cnt];
1443
                   addr_cnt = addr_cnt + 1;
1444
                   load_reg[15: 8] = eth_phy0.rx_mem[addr_cnt];
1445
                   addr_cnt = addr_cnt + 1;
1446
                   load_reg[ 7: 0] = eth_phy0.rx_mem[addr_cnt];
1447
                   addr_cnt = addr_cnt + 1;
1448
                end
1449
              // set new load bit position
1450
              if((word_cnt+3) == 31)
1451
                word_cnt = 16;
1452
              else if ((word_cnt+3) == 23)
1453
                word_cnt = 8;
1454
              else if ((word_cnt+3) == 15)
1455
                word_cnt = 0;
1456
              else if ((word_cnt+3) == 7)
1457
                word_cnt = 24;
1458
              else
1459
                word_cnt = word_cnt + 4;// - 4;
1460
              // decrement nibble counter
1461
              nibble_cnt = nibble_cnt - 1;
1462
              // wait for delta time
1463
              delta_t = !delta_t;
1464
           end // while
1465
         #1;
1466
      end
1467
   endtask // paralel_crc_phy_rx
1468
 
1469
 
1470
 
1471
 

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