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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [bench/] [verilog/] [orpsoc_testbench.v] - Blame information for rev 631

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//////////////////////////////////////////////////////////////////////
///                                                               //// 
/// ORPSoC Atlys testbench                                        ////
///                                                               ////
/// Instantiate ORPSoC, monitors, provide stimulus                ////
///                                                               ////
/// Julius Baxter, julius@opencores.org                           ////
/// Contributor(s):                                               ////
///   Stefan Kristiansson, stefan.kristiansson@saunalahti.fi      ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "orpsoc-defines.v"
`include "orpsoc-testbench-defines.v"
`include "test-defines.v"
`include "timescale.v"
// Xilinx simulation:
`include "glbl.v"
 
module orpsoc_testbench;
 
   // Clock and reset signal registers
   reg clk = 0;
   reg rst_n = 1; // Active LOW
 
   always
     #((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
 
   wire clk_n, clk_p;
   assign clk_p = clk;
   assign clk_n = ~clk;
 
 
   // Reset, ACTIVE LOW
   initial
     begin
        #1;
        repeat (32) @(negedge clk)
          rst_n <= 1;
        repeat (32) @(negedge clk)
          rst_n <= 0;
        repeat (32) @(negedge clk)
          rst_n <= 1;
     end
 
   // Include design parameters file
`include "orpsoc-params.v"
 
   // Pullup bus for I2C
   tri1 i2c_scl, i2c_sda;
 
`ifdef JTAG_DEBUG
   wire tdo_pad_o;
   wire tck_pad_i;
   wire tms_pad_i;
   wire tdi_pad_i;
`endif
`ifdef UART0
   wire uart0_stx_pad_o;
   wire uart0_srx_pad_i;
`endif
`ifdef GPIO0
   wire [gpio0_io_width-1:0] gpio0_io;
`endif
`ifdef SPI0
   wire                      spi0_mosi_o;
   wire                      spi0_miso_i;
   wire                      spi0_sck_o;
   wire                      spi0_hold_n_o;
   wire                      spi0_w_n_o;
   wire [spi0_ss_width-1:0]  spi0_ss_o;
`endif
`ifdef ETH0
   wire                      mtx_clk_o;
   wire [3:0]                 ethphy_mii_tx_d;
   wire                      ethphy_mii_tx_en;
   wire                      ethphy_mii_tx_err;
   wire                      mrx_clk_o;
   wire [3:0]                 mrxd_o;
   wire                      mrxdv_o;
   wire                      mrxerr_o;
   wire                      mcoll_o;
   wire                      mcrs_o;
   wire                      ethphy_rst_n;
   wire                      eth0_mdc_pad_o;
   wire                      eth0_md_pad_io;
`endif
`ifdef XILINX_DDR2
 `include "xilinx_ddr2_params.v"
   localparam DEVICE_WIDTH    = 16;      // Memory device data width
   localparam real           CLK_PERIOD_NS   = C3_MEMCLK_PERIOD / 1000.0;
   localparam real           TCYC_200           = 5.0;
   localparam real           TPROP_DQS          = 0.00;  // Delay for DQS signal during Write Operation
   localparam real           TPROP_DQS_RD       = 0.00;  // Delay for DQS signal during Read Operation
   localparam real           TPROP_PCB_CTRL     = 0.00;  // Delay for Address and Ctrl signals
   localparam real           TPROP_PCB_DATA     = 0.00;  // Delay for data signal during Write operation
   localparam real           TPROP_PCB_DATA_RD  = 0.00;  // Delay for data signal during Read operation
 
   wire [DQ_WIDTH-1:0]        ddr2_dq_fpga;
   wire [DQS_WIDTH-1:0]      ddr2_dqs_fpga;
   wire [DQS_WIDTH-1:0]      ddr2_dqs_n_fpga;
   wire                      ddr2_udqs_fpga;
   wire                      ddr2_udqs_n_fpga;
   wire [DM_WIDTH-1:0]        ddr2_dm_fpga;
   wire                      ddr2_udm_fpga;
   wire [CLK_WIDTH-1:0]      ddr2_ck_fpga;
   wire [CLK_WIDTH-1:0]      ddr2_ck_n_fpga;
   wire [ROW_WIDTH-1:0]      ddr2_a_fpga;
   wire [BANK_WIDTH-1:0]     ddr2_ba_fpga;
   wire                      ddr2_ras_n_fpga;
   wire                      ddr2_cas_n_fpga;
   wire                      ddr2_we_n_fpga;
   wire [CKE_WIDTH-1:0]      ddr2_cke_fpga;
   wire [ODT_WIDTH-1:0]      ddr2_odt_fpga;
 
   wire                      ddr2_rzq;
   wire                      ddr2_zio;
`endif
 
   orpsoc_top dut
     (
`ifdef JTAG_DEBUG
      .tms_pad_i                        (tms_pad_i),
      .tck_pad_i                        (tck_pad_i),
      .tdi_pad_i                        (tdi_pad_i),
      .tdo_pad_o                        (tdo_pad_o),
`endif
`ifdef XILINX_DDR2
      .ddr2_a                           (ddr2_a_fpga),
      .ddr2_ba                          (ddr2_ba_fpga),
      .ddr2_ras_n                       (ddr2_ras_n_fpga),
      .ddr2_cas_n                       (ddr2_cas_n_fpga),
      .ddr2_we_n                        (ddr2_we_n_fpga),
      .ddr2_rzq                         (ddr2_rzq),
      .ddr2_zio                         (ddr2_zio),
      .ddr2_odt                         (ddr2_odt_fpga),
      .ddr2_cke                         (ddr2_cke_fpga),
      .ddr2_dm                          (ddr2_dm_fpga),
      .ddr2_udm                         (ddr2_udm_fpga),
      .ddr2_ck                          (ddr2_ck_fpga),
      .ddr2_ck_n                        (ddr2_ck_n_fpga),
      .ddr2_dq                          (ddr2_dq_fpga),
      .ddr2_dqs                         (ddr2_dqs_fpga),
      .ddr2_dqs_n                       (ddr2_dqs_n_fpga),
      .ddr2_udqs                        (ddr2_udqs_fpga),
      .ddr2_udqs_n                      (ddr2_udqs_n_fpga),
`endif
`ifdef UART0
      .uart0_stx_pad_o                  (uart0_stx_pad_o),
      .uart0_srx_pad_i                  (uart0_srx_pad_i),
`ifdef UART0_EXPHEADER
      .uart0_stx_expheader_pad_o        (uart0_stx_pad_o),
      .uart0_srx_expheader_pad_i        (uart0_srx_pad_i),
`endif
`endif
`ifdef SPI0
       .spi0_sck_o                      (spi0_sck_o),
       .spi0_miso_i                     (spi0_miso_i),
       .spi0_mosi_o                     (spi0_mosi_o),
       .spi0_ss_o                       (spi0_ss_o),
`endif
`ifdef I2C0
      .i2c0_sda_io                      (i2c_sda),
      .i2c0_scl_io                      (i2c_scl),
`endif
`ifdef I2C1
      .i2c1_sda_io                      (i2c_sda),
      .i2c1_scl_io                      (i2c_scl),
`endif
`ifdef GPIO0
      .gpio0_io                         (gpio0_io),
`endif
`ifdef ETH0
      .eth0_tx_clk                      (mtx_clk_o),
      .eth0_tx_data                     (ethphy_mii_tx_d),
      .eth0_tx_en                       (ethphy_mii_tx_en),
      .eth0_tx_er                       (ethphy_mii_tx_err),
      .eth0_rx_clk                      (mrx_clk_o),
      .eth0_rx_data                     (mrxd_o),
      .eth0_dv                          (mrxdv_o),
      .eth0_rx_er                       (mrxerr_o),
      .eth0_col                         (mcoll_o),
      .eth0_crs                         (mcrs_o),
      .eth0_rst_n_o                     (ethphy_rst_n),
      .eth0_mdc_pad_o                   (eth0_mdc_pad_o),
      .eth0_md_pad_io                   (eth0_md_pad_io),
`endif //  `ifdef ETH0
 
      .sys_clk_in                       (clk),
 
      .rst_n_pad_i                      (rst_n)
      );
 
   //
   // Instantiate OR1200 monitor
   //
   or1200_monitor monitor();
 
`ifndef SIM_QUIET
 `define CPU_ic_top or1200_ic_top
 `define CPU_dc_top or1200_dc_top
   wire                      ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;
   always @(posedge ic_en)
     $display("Or1200 IC enabled at %t", $time);
 
   wire                      dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;
   always @(posedge dc_en)
     $display("Or1200 DC enabled at %t", $time);
`endif
 
 
`ifdef JTAG_DEBUG
 `ifdef VPI_DEBUG
   // Debugging interface
   vpi_debug_module vpi_dbg
     (
      .tms(tms_pad_i),
      .tck(tck_pad_i),
      .tdi(tdi_pad_i),
      .tdo(tdo_pad_o)
      );
 `else
   // If no VPI debugging, tie off JTAG inputs
   assign tdi_pad_i = 1;
   assign tck_pad_i = 0;
   assign tms_pad_i = 1;
 `endif // !`ifdef VPI_DEBUG_ENABLE
`endif //  `ifdef JTAG_DEBUG
 
`ifdef SPI0
 
   // SPI flash memory - M25P16 compatible SPI protocol
   AT26DFxxx
     #(.MEMSIZE(16384*1024)) // 16MB flash on Atlys
     spi0_flash
     (// Outputs
      .SO                                       (spi0_miso_i),
      // Inputs
      .CSB                                      (spi0_ss_o),
      .SCK                                      (spi0_sck_o),
      .SI                                       (spi0_mosi_o),
      .WPB                                      (1'b1)
      );
 
 
`endif //  `ifdef SPI0
 
`ifdef ETH0
 
   /* TX/RXes packets and checks them, enabled when ethernet MAC is */
 `include "eth_stim.v"
 
   eth_phy eth_phy0
     (
      // Outputs
      .mtx_clk_o                        (mtx_clk_o),
      .mrx_clk_o                        (mrx_clk_o),
      .mrxd_o                           (mrxd_o[3:0]),
      .mrxdv_o                          (mrxdv_o),
      .mrxerr_o                         (mrxerr_o),
      .mcoll_o                          (mcoll_o),
      .mcrs_o                           (mcrs_o),
      .link_o                           (),
      .speed_o                          (),
      .duplex_o                         (),
      .smii_clk_i                       (1'b0),
      .smii_sync_i                      (1'b0),
      .smii_rx_o                        (),
      // Inouts
      .md_io                            (eth0_md_pad_io),
      // Inputs
 `ifndef ETH0_PHY_RST
      // If no reset out from the design, hook up to the board's active low rst
      .m_rst_n_i                        (rst_n),
 `else
      .m_rst_n_i                        (ethphy_rst_n),
 `endif
      .mtxd_i                           (ethphy_mii_tx_d[3:0]),
      .mtxen_i                          (ethphy_mii_tx_en),
      .mtxerr_i                         (ethphy_mii_tx_err),
      .mdc_i                            (eth0_mdc_pad_o));
 
`endif //  `ifdef ETH0
 
`ifdef XILINX_DDR2
 `ifndef GATE_SIM
   defparam dut.xilinx_ddr2_0.xilinx_ddr2_if0.ddr2_mig.C3_SIMULATION = "TRUE";
 `endif
 
   PULLDOWN ddr2_zio_pulldown (.O(ddr2_zio));   PULLDOWN ddr2_rzq_pulldown (.O(ddr2_rzq));
 
   parameter NUM_PROGRAM_WORDS=1048576;
   integer ram_ptr, program_word_ptr, k;
   reg [31:0] tmp_program_word;
   reg [31:0] program_array [0:NUM_PROGRAM_WORDS-1]; // 1M words = 4MB
   reg [8*16-1:0] ddr2_ram_mem_line; //8*16-bits= 8 shorts (half-words)
            initial
              begin
 
 `ifdef PRELOAD_RAM
  `include "ddr2_model_preload.v"
 `endif
              end
 
            ddr2_model u_mem0
              (
               .ck        (ddr2_ck_fpga),
               .ck_n      (ddr2_ck_n_fpga),
               .cke       (ddr2_cke_fpga),
               .cs_n      (1'b0),
               .ras_n     (ddr2_ras_n_fpga),
               .cas_n     (ddr2_cas_n_fpga),
               .we_n      (ddr2_we_n_fpga),
               .dm_rdqs   ({ddr2_udm_fpga,ddr2_dm_fpga}),
               .ba        (ddr2_ba_fpga),
               .addr      (ddr2_a_fpga),
               .dq        (ddr2_dq_fpga),
               .dqs       ({ddr2_udqs_fpga,ddr2_dqs_fpga}),
               .dqs_n     ({ddr2_udqs_n_fpga,ddr2_dqs_n_fpga}),
               .rdqs_n    (),
               .odt       (ddr2_odt_fpga)
               );
`endif
 
 
`ifdef VCD
   reg vcd_go = 0;
   always @(vcd_go)
     begin
 
 `ifdef VCD_DELAY
        #(`VCD_DELAY);
 `endif
 
        // Delay by x insns
 `ifdef VCD_DELAY_INSNS
        #10; // Delay until after the value becomes valid
        while (monitor.insns < `VCD_DELAY_INSNS)
          @(posedge clk);
 `endif
 
 `ifdef SIMULATOR_MODELSIM
        // Modelsim can GZip VCDs on the fly if given in the suffix
  `define VCD_SUFFIX   ".vcd.gz"
 `else
  `define VCD_SUFFIX   ".vcd"
 `endif
 
 `ifndef SIM_QUIET
        $display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
 `endif
        $dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
 `ifndef VCD_DEPTH
  `define VCD_DEPTH 0
 `endif
        $dumpvars(`VCD_DEPTH);
 
     end
`endif //  `ifdef VCD
 
   initial
     begin
`ifndef SIM_QUIET
        $display("\n* Starting simulation of design RTL.\n* Test: %s\n",
                 `TEST_NAME_STRING );
`endif
 
`ifdef VCD
        vcd_go = 1;
`endif
 
     end // initial begin
 
`ifdef END_TIME
   initial begin
      #(`END_TIME);
 `ifndef SIM_QUIET
      $display("* Finish simulation due to END_TIME being set at %t", $time);
 `endif
      $finish;
   end
`endif
 
`ifdef END_INSNS
   initial begin
      #10
        while (monitor.insns < `END_INSNS)
          @(posedge clk);
 `ifndef SIM_QUIET
      $display("* Finish simulation due to END_INSNS count (%d) reached at %t",
               `END_INSNS, $time);
 `endif
      $finish;
   end
`endif
 
`ifdef UART0
   //   
   // UART0 decoder
   //   
   uart_decoder
     #(
        .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
        )
   uart0_decoder
     (
      .clk(clk),
      .uart_tx(uart0_stx_pad_o)
      );
 
   // Loopback UART lines
   assign uart0_srx_pad_i = uart0_stx_pad_o;
 
`endif //  `ifdef UART0
 
endmodule // orpsoc_testbench
 
// Local Variables:
// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")
// verilog-library-files:()
// verilog-library-extensions:(".v" ".h")
// End:
 

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [bench/] [verilog/] [orpsoc_testbench.v] - Blame information for rev 631

Line No.	Rev	Author	Line
1	631	stekern	`//////////////////////////////////////////////////////////////////////`
2			`/// ////`
3			`/// ORPSoC Atlys testbench ////`
4			`/// ////`
5			`/// Instantiate ORPSoC, monitors, provide stimulus ////`
6			`/// ////`
7			`/// Julius Baxter, julius@opencores.org ////`
8			`/// Contributor(s): ////`
9			`/// Stefan Kristiansson, stefan.kristiansson@saunalahti.fi ////`
10			`//////////////////////////////////////////////////////////////////////`
11			`//// ////`
12			`//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////`
13			`//// ////`
14			`//// This source file may be used and distributed without ////`
15			`//// restriction provided that this copyright statement is not ////`
16			`//// removed from the file and that any derivative work contains ////`
17			`//// the original copyright notice and the associated disclaimer. ////`
18			`//// ////`
19			`//// This source file is free software; you can redistribute it ////`
20			`//// and/or modify it under the terms of the GNU Lesser General ////`
21			`//// Public License as published by the Free Software Foundation; ////`
22			`//// either version 2.1 of the License, or (at your option) any ////`
23			`//// later version. ////`
24			`//// ////`
25			`//// This source is distributed in the hope that it will be ////`
26			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
27			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
28			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
29			`//// details. ////`
30			`//// ////`
31			`//// You should have received a copy of the GNU Lesser General ////`
32			`//// Public License along with this source; if not, download it ////`
33			`//// from http://www.opencores.org/lgpl.shtml ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36
37			`include "orpsoc-defines.v"
38			`include "orpsoc-testbench-defines.v"
39			`include "test-defines.v"
40			`include "timescale.v"
41			`// Xilinx simulation:`
42			`include "glbl.v"
43
44			`module orpsoc_testbench;`
45
46			`// Clock and reset signal registers`
47			`reg clk = 0;`
48			`reg rst_n = 1; // Active LOW`
49
50			`always`
51			#((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
52
53			`wire clk_n, clk_p;`
54			`assign clk_p = clk;`
55			`assign clk_n = ~clk;`
56
57
58			`// Reset, ACTIVE LOW`
59			`initial`
60			`begin`
61			`#1;`
62			`repeat (32) @(negedge clk)`
63			`rst_n <= 1;`
64			`repeat (32) @(negedge clk)`
65			`rst_n <= 0;`
66			`repeat (32) @(negedge clk)`
67			`rst_n <= 1;`
68			`end`
69
70			`// Include design parameters file`
71			`include "orpsoc-params.v"
72
73			`// Pullup bus for I2C`
74			`tri1 i2c_scl, i2c_sda;`
75
76			`ifdef JTAG_DEBUG
77			`wire tdo_pad_o;`
78			`wire tck_pad_i;`
79			`wire tms_pad_i;`
80			`wire tdi_pad_i;`
81			`endif
82			`ifdef UART0
83			`wire uart0_stx_pad_o;`
84			`wire uart0_srx_pad_i;`
85			`endif
86			`ifdef GPIO0
87			`wire [gpio0_io_width-1:0] gpio0_io;`
88			`endif
89			`ifdef SPI0
90			`wire spi0_mosi_o;`
91			`wire spi0_miso_i;`
92			`wire spi0_sck_o;`
93			`wire spi0_hold_n_o;`
94			`wire spi0_w_n_o;`
95			`wire [spi0_ss_width-1:0] spi0_ss_o;`
96			`endif
97			`ifdef ETH0
98			`wire mtx_clk_o;`
99			`wire [3:0] ethphy_mii_tx_d;`
100			`wire ethphy_mii_tx_en;`
101			`wire ethphy_mii_tx_err;`
102			`wire mrx_clk_o;`
103			`wire [3:0] mrxd_o;`
104			`wire mrxdv_o;`
105			`wire mrxerr_o;`
106			`wire mcoll_o;`
107			`wire mcrs_o;`
108			`wire ethphy_rst_n;`
109			`wire eth0_mdc_pad_o;`
110			`wire eth0_md_pad_io;`
111			`endif
112			`ifdef XILINX_DDR2
113			`include "xilinx_ddr2_params.v"
114			`localparam DEVICE_WIDTH = 16; // Memory device data width`
115			`localparam real CLK_PERIOD_NS = C3_MEMCLK_PERIOD / 1000.0;`
116			`localparam real TCYC_200 = 5.0;`
117			`localparam real TPROP_DQS = 0.00; // Delay for DQS signal during Write Operation`
118			`localparam real TPROP_DQS_RD = 0.00; // Delay for DQS signal during Read Operation`
119			`localparam real TPROP_PCB_CTRL = 0.00; // Delay for Address and Ctrl signals`
120			`localparam real TPROP_PCB_DATA = 0.00; // Delay for data signal during Write operation`
121			`localparam real TPROP_PCB_DATA_RD = 0.00; // Delay for data signal during Read operation`
122
123			`wire [DQ_WIDTH-1:0] ddr2_dq_fpga;`
124			`wire [DQS_WIDTH-1:0] ddr2_dqs_fpga;`
125			`wire [DQS_WIDTH-1:0] ddr2_dqs_n_fpga;`
126			`wire ddr2_udqs_fpga;`
127			`wire ddr2_udqs_n_fpga;`
128			`wire [DM_WIDTH-1:0] ddr2_dm_fpga;`
129			`wire ddr2_udm_fpga;`
130			`wire [CLK_WIDTH-1:0] ddr2_ck_fpga;`
131			`wire [CLK_WIDTH-1:0] ddr2_ck_n_fpga;`
132			`wire [ROW_WIDTH-1:0] ddr2_a_fpga;`
133			`wire [BANK_WIDTH-1:0] ddr2_ba_fpga;`
134			`wire ddr2_ras_n_fpga;`
135			`wire ddr2_cas_n_fpga;`
136			`wire ddr2_we_n_fpga;`
137			`wire [CKE_WIDTH-1:0] ddr2_cke_fpga;`
138			`wire [ODT_WIDTH-1:0] ddr2_odt_fpga;`
139
140			`wire ddr2_rzq;`
141			`wire ddr2_zio;`
142			`endif
143
144			`orpsoc_top dut`
145			`(`
146			`ifdef JTAG_DEBUG
147			`.tms_pad_i (tms_pad_i),`
148			`.tck_pad_i (tck_pad_i),`
149			`.tdi_pad_i (tdi_pad_i),`
150			`.tdo_pad_o (tdo_pad_o),`
151			`endif
152			`ifdef XILINX_DDR2
153			`.ddr2_a (ddr2_a_fpga),`
154			`.ddr2_ba (ddr2_ba_fpga),`
155			`.ddr2_ras_n (ddr2_ras_n_fpga),`
156			`.ddr2_cas_n (ddr2_cas_n_fpga),`
157			`.ddr2_we_n (ddr2_we_n_fpga),`
158			`.ddr2_rzq (ddr2_rzq),`
159			`.ddr2_zio (ddr2_zio),`
160			`.ddr2_odt (ddr2_odt_fpga),`
161			`.ddr2_cke (ddr2_cke_fpga),`
162			`.ddr2_dm (ddr2_dm_fpga),`
163			`.ddr2_udm (ddr2_udm_fpga),`
164			`.ddr2_ck (ddr2_ck_fpga),`
165			`.ddr2_ck_n (ddr2_ck_n_fpga),`
166			`.ddr2_dq (ddr2_dq_fpga),`
167			`.ddr2_dqs (ddr2_dqs_fpga),`
168			`.ddr2_dqs_n (ddr2_dqs_n_fpga),`
169			`.ddr2_udqs (ddr2_udqs_fpga),`
170			`.ddr2_udqs_n (ddr2_udqs_n_fpga),`
171			`endif
172			`ifdef UART0
173			`.uart0_stx_pad_o (uart0_stx_pad_o),`
174			`.uart0_srx_pad_i (uart0_srx_pad_i),`
175			`ifdef UART0_EXPHEADER
176			`.uart0_stx_expheader_pad_o (uart0_stx_pad_o),`
177			`.uart0_srx_expheader_pad_i (uart0_srx_pad_i),`
178			`endif
179			`endif
180			`ifdef SPI0
181			`.spi0_sck_o (spi0_sck_o),`
182			`.spi0_miso_i (spi0_miso_i),`
183			`.spi0_mosi_o (spi0_mosi_o),`
184			`.spi0_ss_o (spi0_ss_o),`
185			`endif
186			`ifdef I2C0
187			`.i2c0_sda_io (i2c_sda),`
188			`.i2c0_scl_io (i2c_scl),`
189			`endif
190			`ifdef I2C1
191			`.i2c1_sda_io (i2c_sda),`
192			`.i2c1_scl_io (i2c_scl),`
193			`endif
194			`ifdef GPIO0
195			`.gpio0_io (gpio0_io),`
196			`endif
197			`ifdef ETH0
198			`.eth0_tx_clk (mtx_clk_o),`
199			`.eth0_tx_data (ethphy_mii_tx_d),`
200			`.eth0_tx_en (ethphy_mii_tx_en),`
201			`.eth0_tx_er (ethphy_mii_tx_err),`
202			`.eth0_rx_clk (mrx_clk_o),`
203			`.eth0_rx_data (mrxd_o),`
204			`.eth0_dv (mrxdv_o),`
205			`.eth0_rx_er (mrxerr_o),`
206			`.eth0_col (mcoll_o),`
207			`.eth0_crs (mcrs_o),`
208			`.eth0_rst_n_o (ethphy_rst_n),`
209			`.eth0_mdc_pad_o (eth0_mdc_pad_o),`
210			`.eth0_md_pad_io (eth0_md_pad_io),`
211			`endif // `ifdef ETH0
212
213			`.sys_clk_in (clk),`
214
215			`.rst_n_pad_i (rst_n)`
216			`);`
217
218			`//`
219			`// Instantiate OR1200 monitor`
220			`//`
221			`or1200_monitor monitor();`
222
223			`ifndef SIM_QUIET
224			`define CPU_ic_top or1200_ic_top
225			`define CPU_dc_top or1200_dc_top
226			`wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;`
227			`always @(posedge ic_en)`
228			`$display("Or1200 IC enabled at %t", $time);`
229
230			`wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;`
231			`always @(posedge dc_en)`
232			`$display("Or1200 DC enabled at %t", $time);`
233			`endif
234
235
236			`ifdef JTAG_DEBUG
237			`ifdef VPI_DEBUG
238			`// Debugging interface`
239			`vpi_debug_module vpi_dbg`
240			`(`
241			`.tms(tms_pad_i),`
242			`.tck(tck_pad_i),`
243			`.tdi(tdi_pad_i),`
244			`.tdo(tdo_pad_o)`
245			`);`
246			`else
247			`// If no VPI debugging, tie off JTAG inputs`
248			`assign tdi_pad_i = 1;`
249			`assign tck_pad_i = 0;`
250			`assign tms_pad_i = 1;`
251			`endif // !`ifdef VPI_DEBUG_ENABLE
252			`endif // `ifdef JTAG_DEBUG
253
254			`ifdef SPI0
255
256			`// SPI flash memory - M25P16 compatible SPI protocol`
257			`AT26DFxxx`
258			`#(.MEMSIZE(16384*1024)) // 16MB flash on Atlys`
259			`spi0_flash`
260			`(// Outputs`
261			`.SO (spi0_miso_i),`
262			`// Inputs`
263			`.CSB (spi0_ss_o),`
264			`.SCK (spi0_sck_o),`
265			`.SI (spi0_mosi_o),`
266			`.WPB (1'b1)`
267			`);`
268
269
270			`endif // `ifdef SPI0
271
272			`ifdef ETH0
273
274			`/* TX/RXes packets and checks them, enabled when ethernet MAC is */`
275			`include "eth_stim.v"
276
277			`eth_phy eth_phy0`
278			`(`
279			`// Outputs`
280			`.mtx_clk_o (mtx_clk_o),`
281			`.mrx_clk_o (mrx_clk_o),`
282			`.mrxd_o (mrxd_o[3:0]),`
283			`.mrxdv_o (mrxdv_o),`
284			`.mrxerr_o (mrxerr_o),`
285			`.mcoll_o (mcoll_o),`
286			`.mcrs_o (mcrs_o),`
287			`.link_o (),`
288			`.speed_o (),`
289			`.duplex_o (),`
290			`.smii_clk_i (1'b0),`
291			`.smii_sync_i (1'b0),`
292			`.smii_rx_o (),`
293			`// Inouts`
294			`.md_io (eth0_md_pad_io),`
295			`// Inputs`
296			`ifndef ETH0_PHY_RST
297			`// If no reset out from the design, hook up to the board's active low rst`
298			`.m_rst_n_i (rst_n),`
299			`else
300			`.m_rst_n_i (ethphy_rst_n),`
301			`endif
302			`.mtxd_i (ethphy_mii_tx_d[3:0]),`
303			`.mtxen_i (ethphy_mii_tx_en),`
304			`.mtxerr_i (ethphy_mii_tx_err),`
305			`.mdc_i (eth0_mdc_pad_o));`
306
307			`endif // `ifdef ETH0
308
309			`ifdef XILINX_DDR2
310			`ifndef GATE_SIM
311			`defparam dut.xilinx_ddr2_0.xilinx_ddr2_if0.ddr2_mig.C3_SIMULATION = "TRUE";`
312			`endif
313
314			`PULLDOWN ddr2_zio_pulldown (.O(ddr2_zio)); PULLDOWN ddr2_rzq_pulldown (.O(ddr2_rzq));`
315
316			`parameter NUM_PROGRAM_WORDS=1048576;`
317			`integer ram_ptr, program_word_ptr, k;`
318			`reg [31:0] tmp_program_word;`
319			`reg [31:0] program_array [0:NUM_PROGRAM_WORDS-1]; // 1M words = 4MB`
320			`reg [816-1:0] ddr2_ram_mem_line; //816-bits= 8 shorts (half-words)`
321			`initial`
322			`begin`
323
324			`ifdef PRELOAD_RAM
325			`include "ddr2_model_preload.v"
326			`endif
327			`end`
328
329			`ddr2_model u_mem0`
330			`(`
331			`.ck (ddr2_ck_fpga),`
332			`.ck_n (ddr2_ck_n_fpga),`
333			`.cke (ddr2_cke_fpga),`
334			`.cs_n (1'b0),`
335			`.ras_n (ddr2_ras_n_fpga),`
336			`.cas_n (ddr2_cas_n_fpga),`
337			`.we_n (ddr2_we_n_fpga),`
338			`.dm_rdqs ({ddr2_udm_fpga,ddr2_dm_fpga}),`
339			`.ba (ddr2_ba_fpga),`
340			`.addr (ddr2_a_fpga),`
341			`.dq (ddr2_dq_fpga),`
342			`.dqs ({ddr2_udqs_fpga,ddr2_dqs_fpga}),`
343			`.dqs_n ({ddr2_udqs_n_fpga,ddr2_dqs_n_fpga}),`
344			`.rdqs_n (),`
345			`.odt (ddr2_odt_fpga)`
346			`);`
347			`endif
348
349
350			`ifdef VCD
351			`reg vcd_go = 0;`
352			`always @(vcd_go)`
353			`begin`
354
355			`ifdef VCD_DELAY
356			#(`VCD_DELAY);
357			`endif
358
359			`// Delay by x insns`
360			`ifdef VCD_DELAY_INSNS
361			`#10; // Delay until after the value becomes valid`
362			while (monitor.insns < `VCD_DELAY_INSNS)
363			`@(posedge clk);`
364			`endif
365
366			`ifdef SIMULATOR_MODELSIM
367			`// Modelsim can GZip VCDs on the fly if given in the suffix`
368			`define VCD_SUFFIX ".vcd.gz"
369			`else
370			`define VCD_SUFFIX ".vcd"
371			`endif
372
373			`ifndef SIM_QUIET
374			$display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
375			`endif
376			$dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
377			`ifndef VCD_DEPTH
378			`define VCD_DEPTH 0
379			`endif
380			$dumpvars(`VCD_DEPTH);
381
382			`end`
383			`endif // `ifdef VCD
384
385			`initial`
386			`begin`
387			`ifndef SIM_QUIET
388			`$display("\n* Starting simulation of design RTL.\n* Test: %s\n",`
389			`TEST_NAME_STRING );
390			`endif
391
392			`ifdef VCD
393			`vcd_go = 1;`
394			`endif
395
396			`end // initial begin`
397
398			`ifdef END_TIME
399			`initial begin`
400			#(`END_TIME);
401			`ifndef SIM_QUIET
402			`$display("* Finish simulation due to END_TIME being set at %t", $time);`
403			`endif
404			`$finish;`
405			`end`
406			`endif
407
408			`ifdef END_INSNS
409			`initial begin`
410			`#10`
411			while (monitor.insns < `END_INSNS)
412			`@(posedge clk);`
413			`ifndef SIM_QUIET
414			`$display("* Finish simulation due to END_INSNS count (%d) reached at %t",`
415			`END_INSNS, $time);
416			`endif
417			`$finish;`
418			`end`
419			`endif
420
421			`ifdef UART0
422			`//`
423			`// UART0 decoder`
424			`//`
425			`uart_decoder`
426			`#(`
427			`.uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS`
428			`)`
429			`uart0_decoder`
430			`(`
431			`.clk(clk),`
432			`.uart_tx(uart0_stx_pad_o)`
433			`);`
434
435			`// Loopback UART lines`
436			`assign uart0_srx_pad_i = uart0_stx_pad_o;`
437
438			`endif // `ifdef UART0
439
440			`endmodule // orpsoc_testbench`
441
442			`// Local Variables:`
443			`// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")`
444			`// verilog-library-files:()`
445			`// verilog-library-extensions:(".v" ".h")`
446			`// End:`
447