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//////////////////////////////////////////////////////////////////////
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//// ////
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//// dbg_defines.v ////
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//// ////
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//// ////
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//// This file is part of the SoC Debug Interface. ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 - 2004 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: dbg_defines.v,v $
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// Revision 1.20 2004/04/01 11:56:59 igorm
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// Port names and defines for the supported CPUs changed.
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//
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// Revision 1.19 2004/03/28 20:27:02 igorm
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// New release of the debug interface (3rd. release).
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//
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// Revision 1.18 2004/03/22 16:35:46 igorm
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// Temp version before changing dbg interface.
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//
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// Revision 1.17 2004/01/30 10:24:30 mohor
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// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
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// turned on.
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//
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// Revision 1.16 2004/01/20 14:23:45 mohor
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// Define name changed.
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//
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// Revision 1.15 2003/12/23 15:07:34 mohor
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// New directory structure. New version of the debug interface.
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// Files that are not needed removed.
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//
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// Revision 1.14 2003/10/23 16:17:00 mohor
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// CRC logic changed.
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//
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// Revision 1.13 2003/10/21 09:48:31 simons
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// Mbist support added.
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//
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// Revision 1.12 2003/09/17 14:38:57 simons
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// WB_CNTL register added, some syncronization fixes.
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//
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// Revision 1.11 2003/08/28 13:55:21 simons
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// Three more chains added for cpu debug access.
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//
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// Revision 1.10 2003/07/31 12:19:49 simons
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// Multiple cpu support added.
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//
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// Revision 1.9 2002/05/07 14:43:59 mohor
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// mon_cntl_o signals that controls monitor mux added.
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//
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// Revision 1.8 2002/01/25 07:58:34 mohor
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// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
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// not filled-in. Tested in hw.
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//
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// Revision 1.7 2001/12/06 10:08:06 mohor
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// Warnings from synthesys tools fixed.
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//
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// Revision 1.6 2001/11/28 09:38:30 mohor
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// Trace disabled by default.
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//
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// Revision 1.5 2001/10/15 09:55:47 mohor
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// Wishbone interface added, few fixes for better performance,
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// hooks for boundary scan testing added.
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//
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// Revision 1.4 2001/09/24 14:06:42 mohor
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// Changes connected to the OpenRISC access (SPR read, SPR write).
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//
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// Revision 1.3 2001/09/20 10:11:25 mohor
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// Working version. Few bugs fixed, comments added.
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//
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// Revision 1.2 2001/09/18 14:13:47 mohor
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// Trace fixed. Some registers changed, trace simplified.
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//
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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//
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// Revision 1.3 2001/06/01 22:22:35 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
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//
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// Revision 1.2 2001/05/18 13:10:00 mohor
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// Headers changed. All additional information is now avaliable in the README.txt file.
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//
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// Revision 1.1.1.1 2001/05/18 06:35:08 mohor
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// Initial release
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//
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//
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// Length of the MODULE ID register
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`define DBG_TOP_MODULE_ID_LENGTH 4
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// Length of data
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`define DBG_TOP_MODULE_DATA_LEN `DBG_TOP_MODULE_ID_LENGTH + 1
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`define DBG_TOP_DATA_CNT 3
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// Length of status
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`define DBG_TOP_STATUS_LEN 3'd4
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`define DBG_TOP_STATUS_CNT_WIDTH 3
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// Length of the CRC
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`define DBG_TOP_CRC_LEN 32
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`define DBG_TOP_CRC_CNT 6
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// Chains
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`define DBG_TOP_WISHBONE_DEBUG_MODULE 4'h0
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`define DBG_TOP_CPU0_DEBUG_MODULE 4'h1
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`define DBG_TOP_CPU1_DEBUG_MODULE 4'h2
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// If WISHBONE sub-module is supported uncomment the folowing line
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`define DBG_WISHBONE_SUPPORTED
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// If CPU_0 sub-module is supported uncomment the folowing line
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`define DBG_CPU0_SUPPORTED
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// If CPU_1 sub-module is supported uncomment the folowing line
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//`define DBG_CPU1_SUPPORTED
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// If more debug info is needed, uncomment the follofing line
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//`define DBG_MORE_INFO
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