OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [rtl/] [verilog/] [xilinx_ddr2/] [iodrp_controller.v] - Blame information for rev 627

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 627 stekern
//*****************************************************************************
2
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
3
//
4
// This file contains confidential and proprietary information
5
// of Xilinx, Inc. and is protected under U.S. and
6
// international copyright and other intellectual property
7
// laws.
8
//
9
// DISCLAIMER
10
// This disclaimer is not a license and does not grant any
11
// rights to the materials distributed herewith. Except as
12
// otherwise provided in a valid license issued to you by
13
// Xilinx, and to the maximum extent permitted by applicable
14
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
15
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
16
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
17
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
18
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
19
// (2) Xilinx shall not be liable (whether in contract or tort,
20
// including negligence, or under any other theory of
21
// liability) for any loss or damage of any kind or nature
22
// related to, arising under or in connection with these
23
// materials, including for any direct, or any indirect,
24
// special, incidental, or consequential loss or damage
25
// (including loss of data, profits, goodwill, or any type of
26
// loss or damage suffered as a result of any action brought
27
// by a third party) even if such damage or loss was
28
// reasonably foreseeable or Xilinx had been advised of the
29
// possibility of the same.
30
//
31
// CRITICAL APPLICATIONS
32
// Xilinx products are not designed or intended to be fail-
33
// safe, or for use in any application requiring fail-safe
34
// performance, such as life-support or safety devices or
35
// systems, Class III medical devices, nuclear facilities,
36
// applications related to the deployment of airbags, or any
37
// other applications that could lead to death, personal
38
// injury, or severe property or environmental damage
39
// (individually and collectively, "Critical
40
// Applications"). Customer assumes the sole risk and
41
// liability of any use of Xilinx products in Critical
42
// Applications, subject only to applicable laws and
43
// regulations governing limitations on product liability.
44
//
45
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
46
// PART OF THIS FILE AT ALL TIMES.
47
//
48
//*****************************************************************************
49
//   ____  ____
50
//  /   /\/   /
51
// /___/  \  /    Vendor: Xilinx
52
// \   \   \/     Version: %version
53
//  \   \         Application: MIG
54
//  /   /         Filename: iodrp_controller.v
55
// /___/   /\     Date Last Modified: $Date: 2010/10/27 17:40:12 $
56
// \   \  /  \    Date Created: Mon Feb 9 2009
57
//  \___\/\___\
58
//
59
//Device: Spartan6
60
//Design Name: DDR/DDR2/DDR3/LPDDR
61
//Purpose:  Xilinx reference design for IODRP controller for v0.9 device
62
//
63
//Reference:
64
//
65
//    Revision: Date:       Comment
66
//    1.0:      02/06/09:   Initial version for MIG wrapper.
67
//    1.1:      02/01/09:   updates to indentations.
68
//    1.2:      02/12/09:   changed non-blocking assignments to blocking ones
69
//                          for state machine always block.  Also, assigned
70
//                          intial value to load_shift_n to avoid latch
71
// End Revision
72
//*******************************************************************************
73
 
74
`timescale 1ps/1ps
75
 
76
module iodrp_controller(
77
  input   wire  [7:0] memcell_address,
78
  input   wire  [7:0] write_data,
79
  output  reg   [7:0] read_data,
80
  input   wire        rd_not_write,
81
  input   wire        cmd_valid,
82
  output  wire        rdy_busy_n,
83
  input   wire        use_broadcast,
84
  input   wire        sync_rst,
85
  input   wire        DRP_CLK,
86
  output  reg         DRP_CS,
87
  output  wire        DRP_SDI,  //output to IODRP SDI pin
88
  output  reg         DRP_ADD,
89
  output  reg         DRP_BKST,
90
  input   wire        DRP_SDO   //input from IODRP SDO pin
91
  );
92
 
93
  reg   [7:0]   memcell_addr_reg;     // Register where memcell_address is captured during the READY state
94
  reg   [7:0]   data_reg;             // Register which stores the write data until it is ready to be shifted out
95
  reg   [7:0]   shift_through_reg;    // The shift register which shifts out SDO and shifts in SDI.
96
                                      // This register is loaded before the address or data phase, but continues
97
                                      // to shift for a writeback of read data
98
  reg           load_shift_n;         // The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
99
  reg           addr_data_sel_n;      // The signal which indicates where the shift_through_reg should load from.  0 -> data_reg  1 -> memcell_addr_reg
100
  reg   [2:0]   bit_cnt;              // The counter for which bit is being shifted during address or data phase
101
  reg           rd_not_write_reg;
102
  reg           AddressPhase;         // This is set after the first address phase has executed
103
  reg           capture_read_data;
104
 
105
  (* FSM_ENCODING="one-hot" *) reg [2:0] state, nextstate;
106
 
107
  wire  [7:0]   data_out_mux;         // The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
108
  wire          DRP_SDI_pre;          // added so that DRP_SDI output is only active when DRP_CS is active
109
 
110
  localparam  READY             = 3'h0;
111
  localparam  DECIDE            = 3'h1;
112
  localparam  ADDR_PHASE        = 3'h2;
113
  localparam  ADDR_TO_DATA_GAP  = 3'h3;
114
  localparam  ADDR_TO_DATA_GAP2 = 3'h4;
115
  localparam  ADDR_TO_DATA_GAP3 = 3'h5;
116
  localparam  DATA_PHASE        = 3'h6;
117
  localparam  ALMOST_READY      = 3'h7;
118
 
119
  localparam  IOI_DQ0           = 5'h01;
120
  localparam  IOI_DQ1           = 5'h00;
121
  localparam  IOI_DQ2           = 5'h03;
122
  localparam  IOI_DQ3           = 5'h02;
123
  localparam  IOI_DQ4           = 5'h05;
124
  localparam  IOI_DQ5           = 5'h04;
125
  localparam  IOI_DQ6           = 5'h07;
126
  localparam  IOI_DQ7           = 5'h06;
127
  localparam  IOI_DQ8           = 5'h09;
128
  localparam  IOI_DQ9           = 5'h08;
129
  localparam  IOI_DQ10          = 5'h0B;
130
  localparam  IOI_DQ11          = 5'h0A;
131
  localparam  IOI_DQ12          = 5'h0D;
132
  localparam  IOI_DQ13          = 5'h0C;
133
  localparam  IOI_DQ14          = 5'h0F;
134
  localparam  IOI_DQ15          = 5'h0E;
135
  localparam  IOI_UDQS_CLK      = 5'h1D;
136
  localparam  IOI_UDQS_PIN      = 5'h1C;
137
  localparam  IOI_LDQS_CLK      = 5'h1F;
138
  localparam  IOI_LDQS_PIN      = 5'h1E;
139
  //synthesis translate_off
140
  reg   [32*8-1:0]  state_ascii;
141
  always @ (state) begin
142
    case (state)
143
      READY             :state_ascii  <= "READY";
144
      DECIDE            :state_ascii  <= "DECIDE";
145
      ADDR_PHASE        :state_ascii  <= "ADDR_PHASE";
146
      ADDR_TO_DATA_GAP  :state_ascii  <= "ADDR_TO_DATA_GAP";
147
      ADDR_TO_DATA_GAP2 :state_ascii  <= "ADDR_TO_DATA_GAP2";
148
      ADDR_TO_DATA_GAP3 :state_ascii  <= "ADDR_TO_DATA_GAP3";
149
      DATA_PHASE        :state_ascii  <= "DATA_PHASE";
150
      ALMOST_READY      :state_ascii  <= "ALMOST_READY";
151
    endcase // case(state)
152
  end
153
  //synthesis translate_on
154
  /*********************************************
155
   *   Input Registers
156
   *********************************************/
157
  always @ (posedge DRP_CLK) begin
158
     if(state == READY) begin
159
       memcell_addr_reg <= memcell_address;
160
       data_reg <= write_data;
161
       rd_not_write_reg <= rd_not_write;
162
     end
163
  end
164
 
165
  assign rdy_busy_n = (state == READY);
166
 
167
 
168
  /*********************************************
169
   *   Shift Registers / Bit Counter
170
   *********************************************/
171
  assign data_out_mux = addr_data_sel_n ? memcell_addr_reg : data_reg;
172
 
173
  always @ (posedge DRP_CLK) begin
174
    if(sync_rst)
175
      shift_through_reg <= 8'b0;
176
    else begin
177
      if (load_shift_n)     //Assume the shifter is either loading or shifting, bit 0 is shifted out first
178
        shift_through_reg <= data_out_mux;
179
      else
180
        shift_through_reg <= {DRP_SDO, shift_through_reg[7:1]};
181
    end
182
  end
183
 
184
  always @ (posedge DRP_CLK) begin
185
    if (((state == ADDR_PHASE) | (state == DATA_PHASE)) & !sync_rst)
186
      bit_cnt <= bit_cnt + 1;
187
    else
188
      bit_cnt <= 3'b000;
189
  end
190
 
191
  always @ (posedge DRP_CLK) begin
192
    if(sync_rst) begin
193
      read_data   <= 8'h00;
194
//     capture_read_data <= 1'b0;
195
    end
196
    else begin
197
//       capture_read_data <= (state == DATA_PHASE);
198
//       if(capture_read_data)
199
      if(state == ALMOST_READY)
200
        read_data <= shift_through_reg;
201
//      else
202
//        read_data <= read_data;
203
    end
204
  end
205
 
206
  always @ (posedge DRP_CLK) begin
207
    if(sync_rst) begin
208
      AddressPhase  <= 1'b0;
209
    end
210
    else begin
211
      if (AddressPhase) begin
212
        // Keep it set until we finish the cycle
213
        AddressPhase <= AddressPhase && ~(state == ALMOST_READY);
214
      end
215
      else begin
216
        // set the address phase when ever we finish the address phase
217
        AddressPhase <= (state == ADDR_PHASE) && (bit_cnt == 3'b111);
218
      end
219
    end
220
  end
221
 
222
  /*********************************************
223
   *   DRP Signals
224
   *********************************************/
225
  always @ (posedge DRP_CLK) begin
226
    DRP_ADD     <= (nextstate == ADDR_PHASE);
227
    DRP_CS      <= (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
228
    if (state == READY)
229
      DRP_BKST  <= use_broadcast;
230
  end
231
 
232
//  assign DRP_SDI_pre  = (DRP_CS)? shift_through_reg[0] : 1'b0;  //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
233
//  assign DRP_SDI      = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
234
  assign DRP_SDI = shift_through_reg[0]; // The new read method only requires that we shift out the address and the write data
235
 
236
  /*********************************************
237
   *   State Machine
238
   *********************************************/
239
  always @ (*) begin
240
    addr_data_sel_n = 1'b0;
241
    load_shift_n    = 1'b0;
242
    case (state)
243
      READY:  begin
244
        if(cmd_valid)
245
          nextstate   = DECIDE;
246
        else
247
          nextstate   = READY;
248
      end
249
      DECIDE: begin
250
        load_shift_n    = 1;
251
        addr_data_sel_n = 1;
252
        nextstate       = ADDR_PHASE;
253
      end
254
      ADDR_PHASE: begin
255
        if(&bit_cnt)
256
          if (rd_not_write_reg)
257
            if (AddressPhase)
258
              // After the second pass go to end of statemachine
259
              nextstate = ALMOST_READY;
260
            else
261
              // execute a second address phase for the read access.
262
              nextstate = DECIDE;
263
          else
264
            nextstate = ADDR_TO_DATA_GAP;
265
        else
266
          nextstate   = ADDR_PHASE;
267
      end
268
      ADDR_TO_DATA_GAP: begin
269
        load_shift_n  = 1;
270
        nextstate     = ADDR_TO_DATA_GAP2;
271
      end
272
      ADDR_TO_DATA_GAP2: begin
273
        load_shift_n  = 1;
274
        nextstate     = ADDR_TO_DATA_GAP3;
275
      end
276
      ADDR_TO_DATA_GAP3: begin
277
        load_shift_n  = 1;
278
        nextstate     = DATA_PHASE;
279
      end
280
      DATA_PHASE: begin
281
        if(&bit_cnt)
282
          nextstate   = ALMOST_READY;
283
        else
284
          nextstate   = DATA_PHASE;
285
      end
286
      ALMOST_READY: begin
287
        nextstate     = READY;
288
      end
289
      default: begin
290
        nextstate     = READY;
291
      end
292
    endcase
293
  end
294
 
295
  always @ (posedge DRP_CLK) begin
296
    if(sync_rst)
297
      state <= READY;
298
    else
299
      state <= nextstate;
300
  end
301
 
302
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.