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//*****************************************************************************
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// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: iodrp_controller.v
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// /___/ /\ Date Last Modified: $Date: 2010/10/27 17:40:12 $
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// \ \ / \ Date Created: Mon Feb 9 2009
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// \___\/\___\
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//
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//Device: Spartan6
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//Design Name: DDR/DDR2/DDR3/LPDDR
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//Purpose: Xilinx reference design for IODRP controller for v0.9 device
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//
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//Reference:
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//
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// Revision: Date: Comment
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// 1.0: 02/06/09: Initial version for MIG wrapper.
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// 1.1: 02/01/09: updates to indentations.
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// 1.2: 02/12/09: changed non-blocking assignments to blocking ones
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// for state machine always block. Also, assigned
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// intial value to load_shift_n to avoid latch
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// End Revision
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//*******************************************************************************
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`timescale 1ps/1ps
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module iodrp_controller(
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input wire [7:0] memcell_address,
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input wire [7:0] write_data,
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output reg [7:0] read_data,
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input wire rd_not_write,
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input wire cmd_valid,
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output wire rdy_busy_n,
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input wire use_broadcast,
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input wire sync_rst,
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input wire DRP_CLK,
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output reg DRP_CS,
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output wire DRP_SDI, //output to IODRP SDI pin
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output reg DRP_ADD,
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output reg DRP_BKST,
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input wire DRP_SDO //input from IODRP SDO pin
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);
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reg [7:0] memcell_addr_reg; // Register where memcell_address is captured during the READY state
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reg [7:0] data_reg; // Register which stores the write data until it is ready to be shifted out
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reg [7:0] shift_through_reg; // The shift register which shifts out SDO and shifts in SDI.
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// This register is loaded before the address or data phase, but continues
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// to shift for a writeback of read data
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reg load_shift_n; // The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
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reg addr_data_sel_n; // The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
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reg [2:0] bit_cnt; // The counter for which bit is being shifted during address or data phase
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reg rd_not_write_reg;
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reg AddressPhase; // This is set after the first address phase has executed
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reg capture_read_data;
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(* FSM_ENCODING="one-hot" *) reg [2:0] state, nextstate;
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wire [7:0] data_out_mux; // The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
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wire DRP_SDI_pre; // added so that DRP_SDI output is only active when DRP_CS is active
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localparam READY = 3'h0;
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localparam DECIDE = 3'h1;
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localparam ADDR_PHASE = 3'h2;
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localparam ADDR_TO_DATA_GAP = 3'h3;
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localparam ADDR_TO_DATA_GAP2 = 3'h4;
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localparam ADDR_TO_DATA_GAP3 = 3'h5;
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localparam DATA_PHASE = 3'h6;
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localparam ALMOST_READY = 3'h7;
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localparam IOI_DQ0 = 5'h01;
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localparam IOI_DQ1 = 5'h00;
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localparam IOI_DQ2 = 5'h03;
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localparam IOI_DQ3 = 5'h02;
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localparam IOI_DQ4 = 5'h05;
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localparam IOI_DQ5 = 5'h04;
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localparam IOI_DQ6 = 5'h07;
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localparam IOI_DQ7 = 5'h06;
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localparam IOI_DQ8 = 5'h09;
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localparam IOI_DQ9 = 5'h08;
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localparam IOI_DQ10 = 5'h0B;
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localparam IOI_DQ11 = 5'h0A;
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localparam IOI_DQ12 = 5'h0D;
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localparam IOI_DQ13 = 5'h0C;
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localparam IOI_DQ14 = 5'h0F;
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localparam IOI_DQ15 = 5'h0E;
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localparam IOI_UDQS_CLK = 5'h1D;
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localparam IOI_UDQS_PIN = 5'h1C;
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localparam IOI_LDQS_CLK = 5'h1F;
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localparam IOI_LDQS_PIN = 5'h1E;
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//synthesis translate_off
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reg [32*8-1:0] state_ascii;
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always @ (state) begin
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case (state)
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READY :state_ascii <= "READY";
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DECIDE :state_ascii <= "DECIDE";
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ADDR_PHASE :state_ascii <= "ADDR_PHASE";
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ADDR_TO_DATA_GAP :state_ascii <= "ADDR_TO_DATA_GAP";
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ADDR_TO_DATA_GAP2 :state_ascii <= "ADDR_TO_DATA_GAP2";
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ADDR_TO_DATA_GAP3 :state_ascii <= "ADDR_TO_DATA_GAP3";
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DATA_PHASE :state_ascii <= "DATA_PHASE";
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ALMOST_READY :state_ascii <= "ALMOST_READY";
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endcase // case(state)
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end
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//synthesis translate_on
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/*********************************************
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* Input Registers
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*********************************************/
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always @ (posedge DRP_CLK) begin
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if(state == READY) begin
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memcell_addr_reg <= memcell_address;
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data_reg <= write_data;
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rd_not_write_reg <= rd_not_write;
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end
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end
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assign rdy_busy_n = (state == READY);
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/*********************************************
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* Shift Registers / Bit Counter
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*********************************************/
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assign data_out_mux = addr_data_sel_n ? memcell_addr_reg : data_reg;
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always @ (posedge DRP_CLK) begin
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if(sync_rst)
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shift_through_reg <= 8'b0;
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else begin
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if (load_shift_n) //Assume the shifter is either loading or shifting, bit 0 is shifted out first
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shift_through_reg <= data_out_mux;
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else
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shift_through_reg <= {DRP_SDO, shift_through_reg[7:1]};
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end
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end
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always @ (posedge DRP_CLK) begin
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if (((state == ADDR_PHASE) | (state == DATA_PHASE)) & !sync_rst)
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bit_cnt <= bit_cnt + 1;
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else
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bit_cnt <= 3'b000;
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end
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always @ (posedge DRP_CLK) begin
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if(sync_rst) begin
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read_data <= 8'h00;
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// capture_read_data <= 1'b0;
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end
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else begin
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// capture_read_data <= (state == DATA_PHASE);
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// if(capture_read_data)
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if(state == ALMOST_READY)
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read_data <= shift_through_reg;
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// else
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// read_data <= read_data;
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end
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end
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always @ (posedge DRP_CLK) begin
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if(sync_rst) begin
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AddressPhase <= 1'b0;
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end
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else begin
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if (AddressPhase) begin
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// Keep it set until we finish the cycle
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AddressPhase <= AddressPhase && ~(state == ALMOST_READY);
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end
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else begin
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// set the address phase when ever we finish the address phase
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AddressPhase <= (state == ADDR_PHASE) && (bit_cnt == 3'b111);
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end
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end
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end
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/*********************************************
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* DRP Signals
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*********************************************/
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always @ (posedge DRP_CLK) begin
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DRP_ADD <= (nextstate == ADDR_PHASE);
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DRP_CS <= (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
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if (state == READY)
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DRP_BKST <= use_broadcast;
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end
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// assign DRP_SDI_pre = (DRP_CS)? shift_through_reg[0] : 1'b0; //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
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// assign DRP_SDI = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
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assign DRP_SDI = shift_through_reg[0]; // The new read method only requires that we shift out the address and the write data
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/*********************************************
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* State Machine
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*********************************************/
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always @ (*) begin
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addr_data_sel_n = 1'b0;
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load_shift_n = 1'b0;
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case (state)
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READY: begin
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if(cmd_valid)
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nextstate = DECIDE;
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else
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nextstate = READY;
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end
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DECIDE: begin
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load_shift_n = 1;
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addr_data_sel_n = 1;
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nextstate = ADDR_PHASE;
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end
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ADDR_PHASE: begin
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if(&bit_cnt)
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if (rd_not_write_reg)
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if (AddressPhase)
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// After the second pass go to end of statemachine
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nextstate = ALMOST_READY;
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else
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// execute a second address phase for the read access.
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nextstate = DECIDE;
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else
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nextstate = ADDR_TO_DATA_GAP;
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else
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nextstate = ADDR_PHASE;
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end
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ADDR_TO_DATA_GAP: begin
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load_shift_n = 1;
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nextstate = ADDR_TO_DATA_GAP2;
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end
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ADDR_TO_DATA_GAP2: begin
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load_shift_n = 1;
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nextstate = ADDR_TO_DATA_GAP3;
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end
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ADDR_TO_DATA_GAP3: begin
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load_shift_n = 1;
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nextstate = DATA_PHASE;
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end
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DATA_PHASE: begin
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if(&bit_cnt)
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nextstate = ALMOST_READY;
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else
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nextstate = DATA_PHASE;
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end
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ALMOST_READY: begin
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nextstate = READY;
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end
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default: begin
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nextstate = READY;
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end
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endcase
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end
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always @ (posedge DRP_CLK) begin
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if(sync_rst)
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state <= READY;
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else
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state <= nextstate;
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end
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endmodule
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