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//*****************************************************************************
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// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: mcb_raw_wrapper.v
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// /___/ /\ Date Last Modified: $Date: 2010/10/27 17:40:12 $
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// \ \ / \ Date Created: Thu June 24 2008
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// \___\/\___\
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//
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//Device: Spartan6
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//Design Name: DDR/DDR2/DDR3/LPDDR
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//Purpose:
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//Reference:
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// This module is the intialization control logic of the memory interface.
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// All commands are issued from here acoording to the burst, CAS Latency and
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// the user commands.
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//
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// Revised History:
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// Rev 1.1 - added port_enable assignment for all configurations and rearrange
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// assignment siganls according to port number
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// - added timescale directive -SN 7-28-08
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// - added C_ARB_NUM_TIME_SLOTS and removed the slot 12 through
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// 15 -SN 7-28-08
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// - changed C_MEM_DDR2_WRT_RECOVERY = (C_MEM_TWR /C_MEMCLK_PERIOD) -SN 7-28-08
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// - removed ghighb, gpwrdnb, gsr, gwe in port declaration.
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// For now tb need to force the signals inside the MCB and Wrapper
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// until a glbl.v is ready. Not sure how to do this in NCVerilog
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// flow. -SN 7-28-08
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//
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// Rev 1.2 -- removed p*_cmd_error signals -SN 8-05-08
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// Rev 1.3 -- Added gate logic for data port rd_en and wr_en in Config 3,4,5 - SN 8-8-08
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// Rev 1.4 -- update changes that required by MCB core. - SN 9-11-09
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// Rev 1.5 -- update. CMD delays has been removed in Sept 26 database. -- SN 9-28-08
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// delay_cas_90,delay_ras_90,delay_cke_90,delay_odt_90,delay_rst_90
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// delay_we_90 ,delay_address,delay_ba_90 =
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// --removed :assign #50 delay_dqnum = dqnum;
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// --removed :assign #50 delay_dqpum = dqpum;
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// --removed :assign #50 delay_dqnlm = dqnlm;
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// --removed :assign #50 delay_dqplm = dqplm;
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// --removed : delay_dqsIO_w_en_90_n
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// --removed : delay_dqsIO_w_en_90_p
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// --removed : delay_dqsIO_w_en_0
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// -- corrected spelling error: C_MEM_RTRAS
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// Rev 1.6 -- update IODRP2 and OSERDES connection and was updated by Chip. 1-12-09
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// -- rename the memc_wrapper.v to mcb_raw_wrapper.v
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// Rev 1.7 -- .READEN is removed in IODRP2_MCB 1-28-09
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// -- connection has been updated
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// Rev 1.8 -- update memory parameter equations. 1-30_2009
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// -- added portion of Soft IP
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// -- CAL_CLK_DIV is not used but MCB still has it
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// Rev 1.9 -- added Error checking for Invalid command to unidirectional port
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// Rev 1.10 -- changed the backend connection so that Simulation will work while
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// sw tools try to fix the model issues. 2-3-2009
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// sysclk_2x_90 name is changed to sysclk_2x_180 . It created confusions.
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// It is acutally 180 degree difference.
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// Rev 1.11 -- Added soft_calibration_top.
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// Rev 1.12 -- fixed ui_clk connection to MCB when soft_calib_ip is on. 5-14-2009
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// Rev 1.13 -- Added PULLUP/PULLDN for DQS/DQSN, UDQS/UDQSN lines.
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// Rev 1.14 -- Added minium condition for tRTP valud/
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// REv 1.15 -- Bring the SKIP_IN_TERM_CAL and SKIP_DYNAMIC_CAL from calib_ip to top. 6-16-2009
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// Rev 1.16 -- Fixed the WTR for DDR. 6-23-2009
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// Rev 1.17 -- Fixed width mismatch for px_cmd_ra,px_cmd_ca,px_cmd_ba 7-02-2009
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// Rev 1.18 -- Added lumpdelay parameters for 1.0 silicon support to bypass Calibration 7-10-2010
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// Rev 1.19 -- Added soft fix to support refresh command. 7-15-2009.
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// Rev 1.20 -- Turned on the CALIB_SOFT_IP and C_MC_CALIBRATION_MODE is used to enable/disable
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// Dynamic DQS calibration in Soft Calibration module.
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// Rev 1.21 -- Added extra generate mcbx_dram_odt pin condition. It will not be generated if
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// RTT value is set to "disabled"
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// -- Corrected the UIUDQSDEC connection between soft_calib and MCB.
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// -- PLL_LOCK pin to MCB tie high. Soft Calib module asserts MCB_RST when pll_lock is deasserted. 1-19-2010
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// Rev 1.22 -- Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
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// Rev 1.23 -- Added DDR2 Initialization fix when C_CALIB_SOFT_IP set to "FALSE"
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//*************************************************************************************************************************
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`define DEBUG
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`timescale 1ps / 1ps
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module mcb_raw_wrapper #
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(
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parameter C_MEMCLK_PERIOD = 2500, // /Mem clk period (in ps)
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parameter C_PORT_ENABLE = 6'b111111, // config1 : 6b'111111, config2: 4'b1111. config3 : 3'b111, config4: 2'b11, config5 1'b1
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// C_PORT_ENABLE[5] => User port 5, ...,C_PORT_ENABLE[0] => User port 0
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// Should the C_MEM_ADDR_ORDER made available to user ??
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parameter C_MEM_ADDR_ORDER = "BANK_ROW_COLUMN" , //RowBankCol//ADDR_ORDER_MC : 0: Bank Row Col 1: Row Bank Col. User Address mapping oreder
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////////////////////////////////////////////////////////////////////////////////////////////////
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// The parameter belows are not exposed to non-embedded users.
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// for now this arb_time_slot_x attributes will not exposed to user and will be generated from MIG tool
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// to translate the logical port to physical port. For advance user, translate the logical port
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// to physical port before passing them to this wrapper.
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// MIG need to save the user setting in project file.
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parameter C_ARB_NUM_TIME_SLOTS = 12, // For advance mode, allow user to either choose 10 or 12
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parameter C_ARB_TIME_SLOT_0 = 18'o012345, // Config 1: "B32_B32_X32_X32_X32_X32"
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parameter C_ARB_TIME_SLOT_1 = 18'o123450, // User port 0 --->MCB port 0,User port 1 --->MCB port 1
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parameter C_ARB_TIME_SLOT_2 = 18'o234501, // User port 2 --->MCB port 2,User port 3 --->MCB port 3
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parameter C_ARB_TIME_SLOT_3 = 18'o345012, // User port 4 --->MCB port 4,User port 5 --->MCB port 5
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parameter C_ARB_TIME_SLOT_4 = 18'o450123, // Config 2: "B32_B32_B32_B32"
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parameter C_ARB_TIME_SLOT_5 = 18'o501234, // User port 0 ---> MCB port 0
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parameter C_ARB_TIME_SLOT_6 = 18'o012345, // User port 1 ---> MCB port 1
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parameter C_ARB_TIME_SLOT_7 = 18'o123450, // User port 2 ---> MCB port 2
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parameter C_ARB_TIME_SLOT_8 = 18'o234501, // User port 3 ---> MCB port 4
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parameter C_ARB_TIME_SLOT_9 = 18'o345012, // Config 3: "B64_B32_B3"
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parameter C_ARB_TIME_SLOT_10 = 18'o450123, // User port 0 ---> MCB port 0
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parameter C_ARB_TIME_SLOT_11 = 18'o501234, // User port 1 ---> MCB port 2
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// User port 2 ---> MCB port 4
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// Config 4: "B64_B64"
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// User port 0 ---> MCB port 0
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// User port 1 ---> MCB port 2
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// Config 5 "B128"
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// User port 0 ---> MCB port 0
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parameter C_PORT_CONFIG = "B128",
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// Memory Timings
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parameter C_MEM_TRAS = 45000, //CEIL (tRAS/tCK)
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parameter C_MEM_TRCD = 12500, //CEIL (tRCD/tCK)
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parameter C_MEM_TREFI = 7800, //CEIL (tREFI/tCK) number of clocks
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parameter C_MEM_TRFC = 127500, //CEIL (tRFC/tCK)
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parameter C_MEM_TRP = 12500, //CEIL (tRP/tCK)
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parameter C_MEM_TWR = 15000, //CEIL (tWR/tCK)
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parameter C_MEM_TRTP = 7500, //CEIL (tRTP/tCK)
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parameter C_MEM_TWTR = 7500,
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parameter C_NUM_DQ_PINS = 8,
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parameter C_MEM_TYPE = "DDR3",
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parameter C_MEM_DENSITY = "512M",
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parameter C_MEM_BURST_LEN = 8, // MIG Rules for setting this parameter
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// For DDR3 this one always set to 8;
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// For DDR2 Config 1 : MemWidth x8,x16:=> 4; MemWidth x4 => 8
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// Config 2 : MemWidth x8,x16:=> 4; MemWidth x4 => 8
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// Config 3 : Data Port Width: 32 MemWidth x8,x16:=> 4; MemWidth x4 => 8
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// Data Port Width: 64 MemWidth x16 :=> 4; MemWidth x8,x4 => 8
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// Config 4 : Data Port Width: 64 MemWidth x16 :=> 4; MemWidth x4,x8, => 8
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// Config 5 : Data Port Width: 128 MemWidth x4, x8,x16: => 8
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parameter C_MEM_CAS_LATENCY = 4,
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parameter C_MEM_ADDR_WIDTH = 13, // extracted from selected Memory part
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parameter C_MEM_BANKADDR_WIDTH = 3, // extracted from selected Memory part
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parameter C_MEM_NUM_COL_BITS = 11, // extracted from selected Memory part
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parameter C_MEM_DDR3_CAS_LATENCY = 7,
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parameter C_MEM_MOBILE_PA_SR = "FULL", //"FULL", "HALF" Mobile DDR Partial Array Self-Refresh
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parameter C_MEM_DDR1_2_ODS = "FULL", //"FULL" :REDUCED"
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parameter C_MEM_DDR3_ODS = "DIV6",
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parameter C_MEM_DDR2_RTT = "50OHMS",
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parameter C_MEM_DDR3_RTT = "DIV2",
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parameter C_MEM_MDDR_ODS = "FULL",
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parameter C_MEM_DDR2_DIFF_DQS_EN = "YES",
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parameter C_MEM_DDR2_3_PA_SR = "OFF",
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parameter C_MEM_DDR3_CAS_WR_LATENCY = 5, // this parameter is hardcoded by MIG tool which depends on the memory clock frequency
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//C_MEMCLK_PERIOD ave = 2.5ns to < 3.3 ns, CWL = 5
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//C_MEMCLK_PERIOD ave = 1.875ns to < 2.5 ns, CWL = 6
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//C_MEMCLK_PERIOD ave = 1.5ns to <1.875ns, CSL = 7
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//C_MEMCLK_PERIOD avg = 1.25ns to < 1.5ns , CWL = 8
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parameter C_MEM_DDR3_AUTO_SR = "ENABLED",
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parameter C_MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL",
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parameter C_MEM_DDR3_DYN_WRT_ODT = "OFF",
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parameter C_MEM_TZQINIT_MAXCNT = 10'd512, // DDR3 Minimum delay between resets
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//Calibration
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parameter C_MC_CALIB_BYPASS = "NO",
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parameter C_MC_CALIBRATION_RA = 15'h0000,
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parameter C_MC_CALIBRATION_BA = 3'h0,
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parameter C_CALIB_SOFT_IP = "TRUE",
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parameter C_SKIP_IN_TERM_CAL = 1'b0, //provides option to skip the input termination calibration
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parameter C_SKIP_DYNAMIC_CAL = 1'b0, //provides option to skip the dynamic delay calibration
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parameter C_SKIP_DYN_IN_TERM = 1'b1, // provides option to skip the input termination calibration
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parameter C_SIMULATION = "FALSE", // Tells us whether the design is being simulated or implemented
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////////////////LUMP DELAY Params ////////////////////////////
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/// ADDED for 1.0 silicon support to bypass Calibration //////
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/// 07-10-09 chipl
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//////////////////////////////////////////////////////////////
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parameter LDQSP_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter UDQSP_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter LDQSN_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter UDQSN_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter DQ0_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter DQ1_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter DQ2_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter DQ3_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter DQ4_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter DQ5_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter DQ6_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter DQ7_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter DQ8_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter DQ9_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter DQ10_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter DQ11_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter DQ12_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter DQ13_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter DQ14_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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parameter DQ15_TAP_DELAY_VAL = 0, // 0 to 255 inclusive
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//*************
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// MIG tool need to do DRC on this parameter to make sure this is valid Column address to avoid boundary crossing for the current Burst Size setting.
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parameter C_MC_CALIBRATION_CA = 12'h000,
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parameter C_MC_CALIBRATION_CLK_DIV = 1,
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parameter C_MC_CALIBRATION_MODE = "CALIBRATION" , // "CALIBRATION", "NOCALIBRATION"
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parameter C_MC_CALIBRATION_DELAY = "HALF", // "QUARTER", "HALF","THREEQUARTER", "FULL"
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parameter C_P0_MASK_SIZE = 4,
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parameter C_P0_DATA_PORT_SIZE = 32,
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parameter C_P1_MASK_SIZE = 4,
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parameter C_P1_DATA_PORT_SIZE = 32
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)
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(
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// high-speed PLL clock interface
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input sysclk_2x,
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|
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input sysclk_2x_180,
|
272 |
|
|
input pll_ce_0,
|
273 |
|
|
input pll_ce_90,
|
274 |
|
|
input pll_lock,
|
275 |
|
|
input sys_rst,
|
276 |
|
|
// Not needed as ioi netlist are not used
|
277 |
|
|
//***********************************************************************************
|
278 |
|
|
// Below User Port siganls needs to be customized when generating codes from MIG tool
|
279 |
|
|
// The corresponding internal codes that directly use the commented out port signals
|
280 |
|
|
// needs to be removed when gernerating wrapper outputs.
|
281 |
|
|
//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
282 |
|
|
|
283 |
|
|
//User Port0 Interface Signals
|
284 |
|
|
// p0_xxxx signals shows up in Config 1 , Config 2 , Config 3, Config4 and Config 5
|
285 |
|
|
// cmd port 0 signals
|
286 |
|
|
|
287 |
|
|
input p0_arb_en,
|
288 |
|
|
input p0_cmd_clk,
|
289 |
|
|
input p0_cmd_en,
|
290 |
|
|
input [2:0] p0_cmd_instr,
|
291 |
|
|
input [5:0] p0_cmd_bl,
|
292 |
|
|
input [29:0] p0_cmd_byte_addr,
|
293 |
|
|
output p0_cmd_empty,
|
294 |
|
|
output p0_cmd_full,
|
295 |
|
|
|
296 |
|
|
// Data Wr Port signals
|
297 |
|
|
// p0_wr_xx signals shows up in Config 1
|
298 |
|
|
// p0_wr_xx signals shows up in Config 2
|
299 |
|
|
// p0_wr_xx signals shows up in Config 3
|
300 |
|
|
// p0_wr_xx signals shows up in Config 4
|
301 |
|
|
// p0_wr_xx signals shows up in Config 5
|
302 |
|
|
|
303 |
|
|
input p0_wr_clk,
|
304 |
|
|
input p0_wr_en,
|
305 |
|
|
input [C_P0_MASK_SIZE - 1:0] p0_wr_mask,
|
306 |
|
|
input [C_P0_DATA_PORT_SIZE - 1:0] p0_wr_data,
|
307 |
|
|
output p0_wr_full, //
|
308 |
|
|
output p0_wr_empty,//
|
309 |
|
|
output [6:0] p0_wr_count,//
|
310 |
|
|
output p0_wr_underrun,//
|
311 |
|
|
output p0_wr_error,//
|
312 |
|
|
|
313 |
|
|
//Data Rd Port signals
|
314 |
|
|
// p0_rd_xx signals shows up in Config 1
|
315 |
|
|
// p0_rd_xx signals shows up in Config 2
|
316 |
|
|
// p0_rd_xx signals shows up in Config 3
|
317 |
|
|
// p0_rd_xx signals shows up in Config 4
|
318 |
|
|
// p0_rd_xx signals shows up in Config 5
|
319 |
|
|
|
320 |
|
|
input p0_rd_clk,
|
321 |
|
|
input p0_rd_en,
|
322 |
|
|
output [C_P0_DATA_PORT_SIZE - 1:0] p0_rd_data,
|
323 |
|
|
output p0_rd_full,//
|
324 |
|
|
output p0_rd_empty,//
|
325 |
|
|
output [6:0] p0_rd_count,
|
326 |
|
|
output p0_rd_overflow,//
|
327 |
|
|
output p0_rd_error,//
|
328 |
|
|
|
329 |
|
|
|
330 |
|
|
//****************************
|
331 |
|
|
//User Port1 Interface Signals
|
332 |
|
|
// This group of signals only appear on Config 1,2,3,4 when generated from MIG tool
|
333 |
|
|
|
334 |
|
|
input p1_arb_en,
|
335 |
|
|
input p1_cmd_clk,
|
336 |
|
|
input p1_cmd_en,
|
337 |
|
|
input [2:0] p1_cmd_instr,
|
338 |
|
|
input [5:0] p1_cmd_bl,
|
339 |
|
|
input [29:0] p1_cmd_byte_addr,
|
340 |
|
|
output p1_cmd_empty,
|
341 |
|
|
output p1_cmd_full,
|
342 |
|
|
|
343 |
|
|
// Data Wr Port signals
|
344 |
|
|
input p1_wr_clk,
|
345 |
|
|
input p1_wr_en,
|
346 |
|
|
input [C_P1_MASK_SIZE - 1:0] p1_wr_mask,
|
347 |
|
|
input [C_P1_DATA_PORT_SIZE - 1:0] p1_wr_data,
|
348 |
|
|
output p1_wr_full,
|
349 |
|
|
output p1_wr_empty,
|
350 |
|
|
output [6:0] p1_wr_count,
|
351 |
|
|
output p1_wr_underrun,
|
352 |
|
|
output p1_wr_error,
|
353 |
|
|
|
354 |
|
|
//Data Rd Port signals
|
355 |
|
|
input p1_rd_clk,
|
356 |
|
|
input p1_rd_en,
|
357 |
|
|
output [C_P1_DATA_PORT_SIZE - 1:0] p1_rd_data,
|
358 |
|
|
output p1_rd_full,
|
359 |
|
|
output p1_rd_empty,
|
360 |
|
|
output [6:0] p1_rd_count,
|
361 |
|
|
output p1_rd_overflow,
|
362 |
|
|
output p1_rd_error,
|
363 |
|
|
|
364 |
|
|
|
365 |
|
|
//****************************
|
366 |
|
|
//User Port2 Interface Signals
|
367 |
|
|
// This group of signals only appear on Config 1,2,3 when generated from MIG tool
|
368 |
|
|
// p2_xxxx signals shows up in Config 1 , Config 2 and Config 3
|
369 |
|
|
// p_cmd port 2 signals
|
370 |
|
|
|
371 |
|
|
input p2_arb_en,
|
372 |
|
|
input p2_cmd_clk,
|
373 |
|
|
input p2_cmd_en,
|
374 |
|
|
input [2:0] p2_cmd_instr,
|
375 |
|
|
input [5:0] p2_cmd_bl,
|
376 |
|
|
input [29:0] p2_cmd_byte_addr,
|
377 |
|
|
output p2_cmd_empty,
|
378 |
|
|
output p2_cmd_full,
|
379 |
|
|
|
380 |
|
|
// Data Wr Port signals
|
381 |
|
|
// p2_wr_xx signals shows up in Config 1 and Wr Dir
|
382 |
|
|
// p2_wr_xx signals shows up in Config 2
|
383 |
|
|
// p2_wr_xx signals shows up in Config 3
|
384 |
|
|
|
385 |
|
|
input p2_wr_clk,
|
386 |
|
|
input p2_wr_en,
|
387 |
|
|
input [3:0] p2_wr_mask,
|
388 |
|
|
input [31:0] p2_wr_data,
|
389 |
|
|
output p2_wr_full,
|
390 |
|
|
output p2_wr_empty,
|
391 |
|
|
output [6:0] p2_wr_count,
|
392 |
|
|
output p2_wr_underrun,
|
393 |
|
|
output p2_wr_error,
|
394 |
|
|
|
395 |
|
|
//Data Rd Port signals
|
396 |
|
|
// p2_rd_xx signals shows up in Config 1 and Rd Dir
|
397 |
|
|
// p2_rd_xx signals shows up in Config 2
|
398 |
|
|
// p2_rd_xx signals shows up in Config 3
|
399 |
|
|
|
400 |
|
|
input p2_rd_clk,
|
401 |
|
|
input p2_rd_en,
|
402 |
|
|
output [31:0] p2_rd_data,
|
403 |
|
|
output p2_rd_full,
|
404 |
|
|
output p2_rd_empty,
|
405 |
|
|
output [6:0] p2_rd_count,
|
406 |
|
|
output p2_rd_overflow,
|
407 |
|
|
output p2_rd_error,
|
408 |
|
|
|
409 |
|
|
|
410 |
|
|
//****************************
|
411 |
|
|
//User Port3 Interface Signals
|
412 |
|
|
// This group of signals only appear on Config 1,2 when generated from MIG tool
|
413 |
|
|
|
414 |
|
|
input p3_arb_en,
|
415 |
|
|
input p3_cmd_clk,
|
416 |
|
|
input p3_cmd_en,
|
417 |
|
|
input [2:0] p3_cmd_instr,
|
418 |
|
|
input [5:0] p3_cmd_bl,
|
419 |
|
|
input [29:0] p3_cmd_byte_addr,
|
420 |
|
|
output p3_cmd_empty,
|
421 |
|
|
output p3_cmd_full,
|
422 |
|
|
|
423 |
|
|
// Data Wr Port signals
|
424 |
|
|
// p3_wr_xx signals shows up in Config 1 and Wr Dir
|
425 |
|
|
// p3_wr_xx signals shows up in Config 2
|
426 |
|
|
|
427 |
|
|
input p3_wr_clk,
|
428 |
|
|
input p3_wr_en,
|
429 |
|
|
input [3:0] p3_wr_mask,
|
430 |
|
|
input [31:0] p3_wr_data,
|
431 |
|
|
output p3_wr_full,
|
432 |
|
|
output p3_wr_empty,
|
433 |
|
|
output [6:0] p3_wr_count,
|
434 |
|
|
output p3_wr_underrun,
|
435 |
|
|
output p3_wr_error,
|
436 |
|
|
|
437 |
|
|
//Data Rd Port signals
|
438 |
|
|
// p3_rd_xx signals shows up in Config 1 and Rd Dir when generated from MIG ttols
|
439 |
|
|
// p3_rd_xx signals shows up in Config 2
|
440 |
|
|
|
441 |
|
|
input p3_rd_clk,
|
442 |
|
|
input p3_rd_en,
|
443 |
|
|
output [31:0] p3_rd_data,
|
444 |
|
|
output p3_rd_full,
|
445 |
|
|
output p3_rd_empty,
|
446 |
|
|
output [6:0] p3_rd_count,
|
447 |
|
|
output p3_rd_overflow,
|
448 |
|
|
output p3_rd_error,
|
449 |
|
|
//****************************
|
450 |
|
|
//User Port4 Interface Signals
|
451 |
|
|
// This group of signals only appear on Config 1,2,3,4 when generated from MIG tool
|
452 |
|
|
// p4_xxxx signals only shows up in Config 1
|
453 |
|
|
|
454 |
|
|
input p4_arb_en,
|
455 |
|
|
input p4_cmd_clk,
|
456 |
|
|
input p4_cmd_en,
|
457 |
|
|
input [2:0] p4_cmd_instr,
|
458 |
|
|
input [5:0] p4_cmd_bl,
|
459 |
|
|
input [29:0] p4_cmd_byte_addr,
|
460 |
|
|
output p4_cmd_empty,
|
461 |
|
|
output p4_cmd_full,
|
462 |
|
|
|
463 |
|
|
// Data Wr Port signals
|
464 |
|
|
// p4_wr_xx signals only shows up in Config 1 and Wr Dir
|
465 |
|
|
|
466 |
|
|
input p4_wr_clk,
|
467 |
|
|
input p4_wr_en,
|
468 |
|
|
input [3:0] p4_wr_mask,
|
469 |
|
|
input [31:0] p4_wr_data,
|
470 |
|
|
output p4_wr_full,
|
471 |
|
|
output p4_wr_empty,
|
472 |
|
|
output [6:0] p4_wr_count,
|
473 |
|
|
output p4_wr_underrun,
|
474 |
|
|
output p4_wr_error,
|
475 |
|
|
|
476 |
|
|
//Data Rd Port signals
|
477 |
|
|
// p4_rd_xx signals only shows up in Config 1 and Rd Dir
|
478 |
|
|
|
479 |
|
|
input p4_rd_clk,
|
480 |
|
|
input p4_rd_en,
|
481 |
|
|
output [31:0] p4_rd_data,
|
482 |
|
|
output p4_rd_full,
|
483 |
|
|
output p4_rd_empty,
|
484 |
|
|
output [6:0] p4_rd_count,
|
485 |
|
|
output p4_rd_overflow,
|
486 |
|
|
output p4_rd_error,
|
487 |
|
|
|
488 |
|
|
|
489 |
|
|
//****************************
|
490 |
|
|
//User Port5 Interface Signals
|
491 |
|
|
// p5_xxxx signals only shows up in Config 1; p5_wr_xx or p5_rd_xx depends on the user port settings
|
492 |
|
|
|
493 |
|
|
input p5_arb_en,
|
494 |
|
|
input p5_cmd_clk,
|
495 |
|
|
input p5_cmd_en,
|
496 |
|
|
input [2:0] p5_cmd_instr,
|
497 |
|
|
input [5:0] p5_cmd_bl,
|
498 |
|
|
input [29:0] p5_cmd_byte_addr,
|
499 |
|
|
output p5_cmd_empty,
|
500 |
|
|
output p5_cmd_full,
|
501 |
|
|
|
502 |
|
|
// Data Wr Port signals
|
503 |
|
|
input p5_wr_clk,
|
504 |
|
|
input p5_wr_en,
|
505 |
|
|
input [3:0] p5_wr_mask,
|
506 |
|
|
input [31:0] p5_wr_data,
|
507 |
|
|
output p5_wr_full,
|
508 |
|
|
output p5_wr_empty,
|
509 |
|
|
output [6:0] p5_wr_count,
|
510 |
|
|
output p5_wr_underrun,
|
511 |
|
|
output p5_wr_error,
|
512 |
|
|
|
513 |
|
|
//Data Rd Port signals
|
514 |
|
|
input p5_rd_clk,
|
515 |
|
|
input p5_rd_en,
|
516 |
|
|
output [31:0] p5_rd_data,
|
517 |
|
|
output p5_rd_full,
|
518 |
|
|
output p5_rd_empty,
|
519 |
|
|
output [6:0] p5_rd_count,
|
520 |
|
|
output p5_rd_overflow,
|
521 |
|
|
output p5_rd_error,
|
522 |
|
|
|
523 |
|
|
//*****************************************************
|
524 |
|
|
// memory interface signals
|
525 |
|
|
output [C_MEM_ADDR_WIDTH-1:0] mcbx_dram_addr,
|
526 |
|
|
output [C_MEM_BANKADDR_WIDTH-1:0] mcbx_dram_ba,
|
527 |
|
|
output mcbx_dram_ras_n,
|
528 |
|
|
output mcbx_dram_cas_n,
|
529 |
|
|
output mcbx_dram_we_n,
|
530 |
|
|
|
531 |
|
|
output mcbx_dram_cke,
|
532 |
|
|
output mcbx_dram_clk,
|
533 |
|
|
output mcbx_dram_clk_n,
|
534 |
|
|
inout [C_NUM_DQ_PINS-1:0] mcbx_dram_dq,
|
535 |
|
|
inout mcbx_dram_dqs,
|
536 |
|
|
inout mcbx_dram_dqs_n,
|
537 |
|
|
inout mcbx_dram_udqs,
|
538 |
|
|
inout mcbx_dram_udqs_n,
|
539 |
|
|
|
540 |
|
|
output mcbx_dram_udm,
|
541 |
|
|
output mcbx_dram_ldm,
|
542 |
|
|
output mcbx_dram_odt,
|
543 |
|
|
output mcbx_dram_ddr3_rst,
|
544 |
|
|
// Calibration signals
|
545 |
|
|
input calib_recal, // Input signal to trigger calibration
|
546 |
|
|
// output calib_done, // 0=calibration not done or is in progress.
|
547 |
|
|
// 1=calibration is complete. Also a MEM_READY indicator
|
548 |
|
|
|
549 |
|
|
//Input - RZQ pin from board - expected to have a 2*R resistor to ground
|
550 |
|
|
//Input - Z-stated IO pin - either unbonded IO, or IO garanteed not to be driven externally
|
551 |
|
|
|
552 |
|
|
inout rzq, // RZQ pin from board - expected to have a 2*R resistor to ground
|
553 |
|
|
inout zio, // Z-stated IO pin - either unbonded IO, or IO garanteed not to be driven externally
|
554 |
|
|
// new added signals *********************************
|
555 |
|
|
// these signals are for dynamic Calibration IP
|
556 |
|
|
input ui_read,
|
557 |
|
|
input ui_add,
|
558 |
|
|
input ui_cs,
|
559 |
|
|
input ui_clk,
|
560 |
|
|
input ui_sdi,
|
561 |
|
|
input [4:0] ui_addr,
|
562 |
|
|
input ui_broadcast,
|
563 |
|
|
input ui_drp_update,
|
564 |
|
|
input ui_done_cal,
|
565 |
|
|
input ui_cmd,
|
566 |
|
|
input ui_cmd_in,
|
567 |
|
|
input ui_cmd_en,
|
568 |
|
|
input [3:0] ui_dqcount,
|
569 |
|
|
input ui_dq_lower_dec,
|
570 |
|
|
input ui_dq_lower_inc,
|
571 |
|
|
input ui_dq_upper_dec,
|
572 |
|
|
input ui_dq_upper_inc,
|
573 |
|
|
input ui_udqs_inc,
|
574 |
|
|
input ui_udqs_dec,
|
575 |
|
|
input ui_ldqs_inc,
|
576 |
|
|
input ui_ldqs_dec,
|
577 |
|
|
output [7:0] uo_data,
|
578 |
|
|
output uo_data_valid,
|
579 |
|
|
output uo_done_cal,
|
580 |
|
|
output uo_cmd_ready_in,
|
581 |
|
|
output uo_refrsh_flag,
|
582 |
|
|
output uo_cal_start,
|
583 |
|
|
output uo_sdo,
|
584 |
|
|
output [31:0] status,
|
585 |
|
|
input selfrefresh_enter,
|
586 |
|
|
output selfrefresh_mode
|
587 |
|
|
);
|
588 |
|
|
function integer cdiv (input integer num,
|
589 |
|
|
input integer div); // ceiling divide
|
590 |
|
|
begin
|
591 |
|
|
cdiv = (num/div) + (((num%div)>0) ? 1 : 0);
|
592 |
|
|
end
|
593 |
|
|
endfunction // cdiv
|
594 |
|
|
|
595 |
|
|
// parameters added by AM for OSERDES2 12/09/2008, these parameters may not have to change
|
596 |
|
|
localparam C_OSERDES2_DATA_RATE_OQ = "SDR"; //SDR, DDR
|
597 |
|
|
localparam C_OSERDES2_DATA_RATE_OT = "SDR"; //SDR, DDR
|
598 |
|
|
localparam C_OSERDES2_SERDES_MODE_MASTER = "MASTER"; //MASTER, SLAVE
|
599 |
|
|
localparam C_OSERDES2_SERDES_MODE_SLAVE = "SLAVE"; //MASTER, SLAVE
|
600 |
|
|
localparam C_OSERDES2_OUTPUT_MODE_SE = "SINGLE_ENDED"; //SINGLE_ENDED, DIFFERENTIAL
|
601 |
|
|
localparam C_OSERDES2_OUTPUT_MODE_DIFF = "DIFFERENTIAL";
|
602 |
|
|
|
603 |
|
|
localparam C_BUFPLL_0_LOCK_SRC = "LOCK_TO_0";
|
604 |
|
|
|
605 |
|
|
localparam C_DQ_IODRP2_DATA_RATE = "SDR";
|
606 |
|
|
localparam C_DQ_IODRP2_SERDES_MODE_MASTER = "MASTER";
|
607 |
|
|
localparam C_DQ_IODRP2_SERDES_MODE_SLAVE = "SLAVE";
|
608 |
|
|
|
609 |
|
|
localparam C_DQS_IODRP2_DATA_RATE = "SDR";
|
610 |
|
|
localparam C_DQS_IODRP2_SERDES_MODE_MASTER = "MASTER";
|
611 |
|
|
localparam C_DQS_IODRP2_SERDES_MODE_SLAVE = "SLAVE";
|
612 |
|
|
|
613 |
|
|
|
614 |
|
|
|
615 |
|
|
|
616 |
|
|
|
617 |
|
|
|
618 |
|
|
// MIG always set the below ADD_LATENCY to zero
|
619 |
|
|
localparam C_MEM_DDR3_ADD_LATENCY = "OFF";
|
620 |
|
|
localparam C_MEM_DDR2_ADD_LATENCY = 0;
|
621 |
|
|
localparam C_MEM_MOBILE_TC_SR = 0; // not supported
|
622 |
|
|
|
623 |
|
|
|
624 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
625 |
|
|
// Attribute Declarations
|
626 |
|
|
// Attributes set from GUI
|
627 |
|
|
//
|
628 |
|
|
//
|
629 |
|
|
// the local param for the time slot varis according to User Port Configuration
|
630 |
|
|
// This section also needs to be customized when gernerating wrapper outputs.
|
631 |
|
|
//*****************************************************************************
|
632 |
|
|
|
633 |
|
|
|
634 |
|
|
// For Configuration 1 and this section will be used in RAW file
|
635 |
|
|
localparam arbtimeslot0 = {C_ARB_TIME_SLOT_0 };
|
636 |
|
|
localparam arbtimeslot1 = {C_ARB_TIME_SLOT_1 };
|
637 |
|
|
localparam arbtimeslot2 = {C_ARB_TIME_SLOT_2 };
|
638 |
|
|
localparam arbtimeslot3 = {C_ARB_TIME_SLOT_3 };
|
639 |
|
|
localparam arbtimeslot4 = {C_ARB_TIME_SLOT_4 };
|
640 |
|
|
localparam arbtimeslot5 = {C_ARB_TIME_SLOT_5 };
|
641 |
|
|
localparam arbtimeslot6 = {C_ARB_TIME_SLOT_6 };
|
642 |
|
|
localparam arbtimeslot7 = {C_ARB_TIME_SLOT_7 };
|
643 |
|
|
localparam arbtimeslot8 = {C_ARB_TIME_SLOT_8 };
|
644 |
|
|
localparam arbtimeslot9 = {C_ARB_TIME_SLOT_9 };
|
645 |
|
|
localparam arbtimeslot10 = {C_ARB_TIME_SLOT_10 };
|
646 |
|
|
localparam arbtimeslot11 = {C_ARB_TIME_SLOT_11 };
|
647 |
|
|
|
648 |
|
|
|
649 |
|
|
// convert the memory timing to memory clock units. I
|
650 |
|
|
localparam MEM_RAS_VAL = ((C_MEM_TRAS + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
|
651 |
|
|
localparam MEM_RCD_VAL = ((C_MEM_TRCD + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
|
652 |
|
|
localparam MEM_REFI_VAL = ((C_MEM_TREFI + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) - 25;
|
653 |
|
|
localparam MEM_RFC_VAL = ((C_MEM_TRFC + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
|
654 |
|
|
localparam MEM_RP_VAL = ((C_MEM_TRP + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
|
655 |
|
|
localparam MEM_WR_VAL = ((C_MEM_TWR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
|
656 |
|
|
localparam MEM_RTP_CK = cdiv(C_MEM_TRTP,C_MEMCLK_PERIOD);
|
657 |
|
|
localparam MEM_RTP_VAL = (C_MEM_TYPE == "DDR3") ? (MEM_RTP_CK < 4) ? 4 : MEM_RTP_CK
|
658 |
|
|
: (MEM_RTP_CK < 2) ? 2 : MEM_RTP_CK;
|
659 |
|
|
localparam MEM_WTR_VAL = (C_MEM_TYPE == "DDR") ? 2 :
|
660 |
|
|
(C_MEM_TYPE == "DDR3") ? 4 :
|
661 |
|
|
(C_MEM_TYPE == "MDDR") ? C_MEM_TWTR :
|
662 |
|
|
(C_MEM_TYPE == "LPDDR") ? C_MEM_TWTR :
|
663 |
|
|
((C_MEM_TYPE == "DDR2") && (((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) > 2)) ? ((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) :
|
664 |
|
|
(C_MEM_TYPE == "DDR2") ? 2
|
665 |
|
|
: 3 ;
|
666 |
|
|
localparam C_MEM_DDR2_WRT_RECOVERY = (C_MEM_TYPE != "DDR2") ? 5: ((C_MEM_TWR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
|
667 |
|
|
localparam C_MEM_DDR3_WRT_RECOVERY = (C_MEM_TYPE != "DDR3") ? 5: ((C_MEM_TWR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
|
668 |
|
|
//localparam MEM_TYPE = (C_MEM_TYPE == "LPDDR") ? "MDDR": C_MEM_TYPE;
|
669 |
|
|
|
670 |
|
|
|
671 |
|
|
|
672 |
|
|
////////////////////////////////////////////////////////////////////////////
|
673 |
|
|
// wire Declarations
|
674 |
|
|
////////////////////////////////////////////////////////////////////////////
|
675 |
|
|
|
676 |
|
|
|
677 |
|
|
|
678 |
|
|
|
679 |
|
|
|
680 |
|
|
wire [31:0] addr_in0;
|
681 |
|
|
reg [127:0] allzero = 0;
|
682 |
|
|
|
683 |
|
|
|
684 |
|
|
// UNISIM Model <-> IOI
|
685 |
|
|
//dqs clock network interface
|
686 |
|
|
wire dqs_out_p;
|
687 |
|
|
wire dqs_out_n;
|
688 |
|
|
|
689 |
|
|
wire dqs_sys_p; //from dqs_gen to IOclk network
|
690 |
|
|
wire dqs_sys_n; //from dqs_gen to IOclk network
|
691 |
|
|
wire udqs_sys_p;
|
692 |
|
|
wire udqs_sys_n;
|
693 |
|
|
|
694 |
|
|
wire dqs_p; // open net now ?
|
695 |
|
|
wire dqs_n; // open net now ?
|
696 |
|
|
|
697 |
|
|
|
698 |
|
|
|
699 |
|
|
// IOI and IOB enable/tristate interface
|
700 |
|
|
wire dqIO_w_en_0; //enable DQ pads
|
701 |
|
|
wire dqsIO_w_en_90_p; //enable p side of DQS
|
702 |
|
|
wire dqsIO_w_en_90_n; //enable n side of DQS
|
703 |
|
|
|
704 |
|
|
|
705 |
|
|
//memory chip control interface
|
706 |
|
|
wire [14:0] address_90;
|
707 |
|
|
wire [2:0] ba_90;
|
708 |
|
|
wire ras_90;
|
709 |
|
|
wire cas_90;
|
710 |
|
|
wire we_90 ;
|
711 |
|
|
wire cke_90;
|
712 |
|
|
wire odt_90;
|
713 |
|
|
wire rst_90;
|
714 |
|
|
|
715 |
|
|
// calibration IDELAY control signals
|
716 |
|
|
wire ioi_drp_clk; //DRP interface - synchronous clock output
|
717 |
|
|
wire [4:0] ioi_drp_addr; //DRP interface - IOI selection
|
718 |
|
|
wire ioi_drp_sdo; //DRP interface - serial output for commmands
|
719 |
|
|
wire ioi_drp_sdi; //DRP interface - serial input for commands
|
720 |
|
|
wire ioi_drp_cs; //DRP interface - chip select doubles as DONE signal
|
721 |
|
|
wire ioi_drp_add; //DRP interface - serial address signal
|
722 |
|
|
wire ioi_drp_broadcast;
|
723 |
|
|
wire ioi_drp_train;
|
724 |
|
|
|
725 |
|
|
|
726 |
|
|
// Calibration datacapture siganls
|
727 |
|
|
|
728 |
|
|
wire [3:0]dqdonecount; //select signal for the datacapture 16 to 1 mux
|
729 |
|
|
wire dq_in_p; //positive signal sent to calibration logic
|
730 |
|
|
wire dq_in_n; //negative signal sent to calibration logic
|
731 |
|
|
wire cal_done;
|
732 |
|
|
|
733 |
|
|
|
734 |
|
|
//DQS calibration interface
|
735 |
|
|
wire udqs_n;
|
736 |
|
|
wire udqs_p;
|
737 |
|
|
|
738 |
|
|
|
739 |
|
|
wire udqs_dqocal_p;
|
740 |
|
|
wire udqs_dqocal_n;
|
741 |
|
|
|
742 |
|
|
|
743 |
|
|
// MUI enable interface
|
744 |
|
|
wire df_en_n90 ;
|
745 |
|
|
|
746 |
|
|
//INTERNAL SIGNAL FOR DRP chain
|
747 |
|
|
// IOI <-> MUI
|
748 |
|
|
wire ioi_int_tmp;
|
749 |
|
|
|
750 |
|
|
wire [15:0]dqo_n;
|
751 |
|
|
wire [15:0]dqo_p;
|
752 |
|
|
wire dqnlm;
|
753 |
|
|
wire dqplm;
|
754 |
|
|
wire dqnum;
|
755 |
|
|
wire dqpum;
|
756 |
|
|
|
757 |
|
|
|
758 |
|
|
// IOI <-> IOB routes
|
759 |
|
|
wire [C_MEM_ADDR_WIDTH-1:0]ioi_addr;
|
760 |
|
|
wire [C_MEM_BANKADDR_WIDTH-1:0]ioi_ba;
|
761 |
|
|
wire ioi_cas;
|
762 |
|
|
wire ioi_ck;
|
763 |
|
|
wire ioi_ckn;
|
764 |
|
|
wire ioi_cke;
|
765 |
|
|
wire [C_NUM_DQ_PINS-1:0]ioi_dq;
|
766 |
|
|
wire ioi_dqs;
|
767 |
|
|
wire ioi_dqsn;
|
768 |
|
|
wire ioi_udqs;
|
769 |
|
|
wire ioi_udqsn;
|
770 |
|
|
wire ioi_odt;
|
771 |
|
|
wire ioi_ras;
|
772 |
|
|
wire ioi_rst;
|
773 |
|
|
wire ioi_we;
|
774 |
|
|
wire ioi_udm;
|
775 |
|
|
wire ioi_ldm;
|
776 |
|
|
|
777 |
|
|
wire [15:0] in_dq;
|
778 |
|
|
wire [C_NUM_DQ_PINS-1:0] in_pre_dq;
|
779 |
|
|
|
780 |
|
|
|
781 |
|
|
|
782 |
|
|
wire in_dqs;
|
783 |
|
|
wire in_pre_dqsp;
|
784 |
|
|
wire in_pre_dqsn;
|
785 |
|
|
wire in_pre_udqsp;
|
786 |
|
|
wire in_pre_udqsn;
|
787 |
|
|
wire in_udqs;
|
788 |
|
|
// Memory tri-state control signals
|
789 |
|
|
wire [C_MEM_ADDR_WIDTH-1:0]t_addr;
|
790 |
|
|
wire [C_MEM_BANKADDR_WIDTH-1:0]t_ba;
|
791 |
|
|
wire t_cas;
|
792 |
|
|
wire t_ck ;
|
793 |
|
|
wire t_ckn;
|
794 |
|
|
wire t_cke;
|
795 |
|
|
wire [C_NUM_DQ_PINS-1:0]t_dq;
|
796 |
|
|
wire t_dqs;
|
797 |
|
|
wire t_dqsn;
|
798 |
|
|
wire t_udqs;
|
799 |
|
|
wire t_udqsn;
|
800 |
|
|
wire t_odt;
|
801 |
|
|
wire t_ras;
|
802 |
|
|
wire t_rst;
|
803 |
|
|
wire t_we ;
|
804 |
|
|
|
805 |
|
|
|
806 |
|
|
wire t_udm ;
|
807 |
|
|
wire t_ldm ;
|
808 |
|
|
|
809 |
|
|
|
810 |
|
|
|
811 |
|
|
wire idelay_dqs_ioi_s;
|
812 |
|
|
wire idelay_dqs_ioi_m;
|
813 |
|
|
wire idelay_udqs_ioi_s;
|
814 |
|
|
wire idelay_udqs_ioi_m;
|
815 |
|
|
|
816 |
|
|
|
817 |
|
|
wire dqs_pin;
|
818 |
|
|
wire udqs_pin;
|
819 |
|
|
|
820 |
|
|
// USER Interface signals
|
821 |
|
|
|
822 |
|
|
|
823 |
|
|
// translated memory addresses
|
824 |
|
|
wire [14:0]p0_cmd_ra;
|
825 |
|
|
wire [2:0]p0_cmd_ba;
|
826 |
|
|
wire [11:0]p0_cmd_ca;
|
827 |
|
|
wire [14:0]p1_cmd_ra;
|
828 |
|
|
wire [2:0]p1_cmd_ba;
|
829 |
|
|
wire [11:0]p1_cmd_ca;
|
830 |
|
|
wire [14:0]p2_cmd_ra;
|
831 |
|
|
wire [2:0]p2_cmd_ba;
|
832 |
|
|
wire [11:0]p2_cmd_ca;
|
833 |
|
|
wire [14:0]p3_cmd_ra;
|
834 |
|
|
wire [2:0]p3_cmd_ba;
|
835 |
|
|
wire [11:0]p3_cmd_ca;
|
836 |
|
|
wire [14:0]p4_cmd_ra;
|
837 |
|
|
wire [2:0]p4_cmd_ba;
|
838 |
|
|
wire [11:0]p4_cmd_ca;
|
839 |
|
|
wire [14:0]p5_cmd_ra;
|
840 |
|
|
wire [2:0]p5_cmd_ba;
|
841 |
|
|
wire [11:0]p5_cmd_ca;
|
842 |
|
|
|
843 |
|
|
// user command wires mapped from logical ports to physical ports
|
844 |
|
|
wire mig_p0_arb_en;
|
845 |
|
|
wire mig_p0_cmd_clk;
|
846 |
|
|
wire mig_p0_cmd_en;
|
847 |
|
|
wire [14:0] mig_p0_cmd_ra;
|
848 |
|
|
wire [2:0] mig_p0_cmd_ba;
|
849 |
|
|
wire [11:0] mig_p0_cmd_ca;
|
850 |
|
|
|
851 |
|
|
wire [2:0] mig_p0_cmd_instr;
|
852 |
|
|
wire [5:0] mig_p0_cmd_bl;
|
853 |
|
|
wire mig_p0_cmd_empty;
|
854 |
|
|
wire mig_p0_cmd_full;
|
855 |
|
|
|
856 |
|
|
|
857 |
|
|
wire mig_p1_arb_en;
|
858 |
|
|
wire mig_p1_cmd_clk;
|
859 |
|
|
wire mig_p1_cmd_en;
|
860 |
|
|
wire [14:0] mig_p1_cmd_ra;
|
861 |
|
|
wire [2:0] mig_p1_cmd_ba;
|
862 |
|
|
wire [11:0] mig_p1_cmd_ca;
|
863 |
|
|
|
864 |
|
|
wire [2:0] mig_p1_cmd_instr;
|
865 |
|
|
wire [5:0] mig_p1_cmd_bl;
|
866 |
|
|
wire mig_p1_cmd_empty;
|
867 |
|
|
wire mig_p1_cmd_full;
|
868 |
|
|
|
869 |
|
|
wire mig_p2_arb_en;
|
870 |
|
|
wire mig_p2_cmd_clk;
|
871 |
|
|
wire mig_p2_cmd_en;
|
872 |
|
|
wire [14:0] mig_p2_cmd_ra;
|
873 |
|
|
wire [2:0] mig_p2_cmd_ba;
|
874 |
|
|
wire [11:0] mig_p2_cmd_ca;
|
875 |
|
|
|
876 |
|
|
wire [2:0] mig_p2_cmd_instr;
|
877 |
|
|
wire [5:0] mig_p2_cmd_bl;
|
878 |
|
|
wire mig_p2_cmd_empty;
|
879 |
|
|
wire mig_p2_cmd_full;
|
880 |
|
|
|
881 |
|
|
wire mig_p3_arb_en;
|
882 |
|
|
wire mig_p3_cmd_clk;
|
883 |
|
|
wire mig_p3_cmd_en;
|
884 |
|
|
wire [14:0] mig_p3_cmd_ra;
|
885 |
|
|
wire [2:0] mig_p3_cmd_ba;
|
886 |
|
|
wire [11:0] mig_p3_cmd_ca;
|
887 |
|
|
|
888 |
|
|
wire [2:0] mig_p3_cmd_instr;
|
889 |
|
|
wire [5:0] mig_p3_cmd_bl;
|
890 |
|
|
wire mig_p3_cmd_empty;
|
891 |
|
|
wire mig_p3_cmd_full;
|
892 |
|
|
|
893 |
|
|
wire mig_p4_arb_en;
|
894 |
|
|
wire mig_p4_cmd_clk;
|
895 |
|
|
wire mig_p4_cmd_en;
|
896 |
|
|
wire [14:0] mig_p4_cmd_ra;
|
897 |
|
|
wire [2:0] mig_p4_cmd_ba;
|
898 |
|
|
wire [11:0] mig_p4_cmd_ca;
|
899 |
|
|
|
900 |
|
|
wire [2:0] mig_p4_cmd_instr;
|
901 |
|
|
wire [5:0] mig_p4_cmd_bl;
|
902 |
|
|
wire mig_p4_cmd_empty;
|
903 |
|
|
wire mig_p4_cmd_full;
|
904 |
|
|
|
905 |
|
|
wire mig_p5_arb_en;
|
906 |
|
|
wire mig_p5_cmd_clk;
|
907 |
|
|
wire mig_p5_cmd_en;
|
908 |
|
|
wire [14:0] mig_p5_cmd_ra;
|
909 |
|
|
wire [2:0] mig_p5_cmd_ba;
|
910 |
|
|
wire [11:0] mig_p5_cmd_ca;
|
911 |
|
|
|
912 |
|
|
wire [2:0] mig_p5_cmd_instr;
|
913 |
|
|
wire [5:0] mig_p5_cmd_bl;
|
914 |
|
|
wire mig_p5_cmd_empty;
|
915 |
|
|
wire mig_p5_cmd_full;
|
916 |
|
|
|
917 |
|
|
wire mig_p0_wr_clk;
|
918 |
|
|
wire mig_p0_rd_clk;
|
919 |
|
|
wire mig_p1_wr_clk;
|
920 |
|
|
wire mig_p1_rd_clk;
|
921 |
|
|
wire mig_p2_clk;
|
922 |
|
|
wire mig_p3_clk;
|
923 |
|
|
wire mig_p4_clk;
|
924 |
|
|
wire mig_p5_clk;
|
925 |
|
|
|
926 |
|
|
wire mig_p0_wr_en;
|
927 |
|
|
wire mig_p0_rd_en;
|
928 |
|
|
wire mig_p1_wr_en;
|
929 |
|
|
wire mig_p1_rd_en;
|
930 |
|
|
wire mig_p2_en;
|
931 |
|
|
wire mig_p3_en;
|
932 |
|
|
wire mig_p4_en;
|
933 |
|
|
wire mig_p5_en;
|
934 |
|
|
|
935 |
|
|
|
936 |
|
|
wire [31:0]mig_p0_wr_data;
|
937 |
|
|
wire [31:0]mig_p1_wr_data;
|
938 |
|
|
wire [31:0]mig_p2_wr_data;
|
939 |
|
|
wire [31:0]mig_p3_wr_data;
|
940 |
|
|
wire [31:0]mig_p4_wr_data;
|
941 |
|
|
wire [31:0]mig_p5_wr_data;
|
942 |
|
|
|
943 |
|
|
|
944 |
|
|
wire [C_P0_MASK_SIZE-1:0]mig_p0_wr_mask;
|
945 |
|
|
wire [C_P1_MASK_SIZE-1:0]mig_p1_wr_mask;
|
946 |
|
|
wire [3:0]mig_p2_wr_mask;
|
947 |
|
|
wire [3:0]mig_p3_wr_mask;
|
948 |
|
|
wire [3:0]mig_p4_wr_mask;
|
949 |
|
|
wire [3:0]mig_p5_wr_mask;
|
950 |
|
|
|
951 |
|
|
|
952 |
|
|
wire [31:0]mig_p0_rd_data;
|
953 |
|
|
wire [31:0]mig_p1_rd_data;
|
954 |
|
|
wire [31:0]mig_p2_rd_data;
|
955 |
|
|
wire [31:0]mig_p3_rd_data;
|
956 |
|
|
wire [31:0]mig_p4_rd_data;
|
957 |
|
|
wire [31:0]mig_p5_rd_data;
|
958 |
|
|
|
959 |
|
|
wire mig_p0_rd_overflow;
|
960 |
|
|
wire mig_p1_rd_overflow;
|
961 |
|
|
wire mig_p2_overflow;
|
962 |
|
|
wire mig_p3_overflow;
|
963 |
|
|
|
964 |
|
|
wire mig_p4_overflow;
|
965 |
|
|
wire mig_p5_overflow;
|
966 |
|
|
|
967 |
|
|
wire mig_p0_wr_underrun;
|
968 |
|
|
wire mig_p1_wr_underrun;
|
969 |
|
|
wire mig_p2_underrun;
|
970 |
|
|
wire mig_p3_underrun;
|
971 |
|
|
wire mig_p4_underrun;
|
972 |
|
|
wire mig_p5_underrun;
|
973 |
|
|
|
974 |
|
|
wire mig_p0_rd_error;
|
975 |
|
|
wire mig_p0_wr_error;
|
976 |
|
|
wire mig_p1_rd_error;
|
977 |
|
|
wire mig_p1_wr_error;
|
978 |
|
|
wire mig_p2_error;
|
979 |
|
|
wire mig_p3_error;
|
980 |
|
|
wire mig_p4_error;
|
981 |
|
|
wire mig_p5_error;
|
982 |
|
|
|
983 |
|
|
|
984 |
|
|
wire [6:0]mig_p0_wr_count;
|
985 |
|
|
wire [6:0]mig_p1_wr_count;
|
986 |
|
|
wire [6:0]mig_p0_rd_count;
|
987 |
|
|
wire [6:0]mig_p1_rd_count;
|
988 |
|
|
|
989 |
|
|
wire [6:0]mig_p2_count;
|
990 |
|
|
wire [6:0]mig_p3_count;
|
991 |
|
|
wire [6:0]mig_p4_count;
|
992 |
|
|
wire [6:0]mig_p5_count;
|
993 |
|
|
|
994 |
|
|
wire mig_p0_wr_full;
|
995 |
|
|
wire mig_p1_wr_full;
|
996 |
|
|
|
997 |
|
|
wire mig_p0_rd_empty;
|
998 |
|
|
wire mig_p1_rd_empty;
|
999 |
|
|
wire mig_p0_wr_empty;
|
1000 |
|
|
wire mig_p1_wr_empty;
|
1001 |
|
|
wire mig_p0_rd_full;
|
1002 |
|
|
wire mig_p1_rd_full;
|
1003 |
|
|
wire mig_p2_full;
|
1004 |
|
|
wire mig_p3_full;
|
1005 |
|
|
wire mig_p4_full;
|
1006 |
|
|
wire mig_p5_full;
|
1007 |
|
|
wire mig_p2_empty;
|
1008 |
|
|
wire mig_p3_empty;
|
1009 |
|
|
wire mig_p4_empty;
|
1010 |
|
|
wire mig_p5_empty;
|
1011 |
|
|
|
1012 |
|
|
// SELFREESH control signal for suspend feature
|
1013 |
|
|
wire selfrefresh_mcb_enter;
|
1014 |
|
|
wire selfrefresh_mcb_mode ;
|
1015 |
|
|
// Testing Interface signals
|
1016 |
|
|
wire tst_cmd_test_en;
|
1017 |
|
|
wire [7:0] tst_sel;
|
1018 |
|
|
wire [15:0] tst_in;
|
1019 |
|
|
wire tst_scan_clk;
|
1020 |
|
|
wire tst_scan_rst;
|
1021 |
|
|
wire tst_scan_set;
|
1022 |
|
|
wire tst_scan_en;
|
1023 |
|
|
wire tst_scan_in;
|
1024 |
|
|
wire tst_scan_mode;
|
1025 |
|
|
|
1026 |
|
|
wire p0w_tst_en;
|
1027 |
|
|
wire p0r_tst_en;
|
1028 |
|
|
wire p1w_tst_en;
|
1029 |
|
|
wire p1r_tst_en;
|
1030 |
|
|
wire p2_tst_en;
|
1031 |
|
|
wire p3_tst_en;
|
1032 |
|
|
wire p4_tst_en;
|
1033 |
|
|
wire p5_tst_en;
|
1034 |
|
|
|
1035 |
|
|
wire p0_tst_wr_clk_en;
|
1036 |
|
|
wire p0_tst_rd_clk_en;
|
1037 |
|
|
wire p1_tst_wr_clk_en;
|
1038 |
|
|
wire p1_tst_rd_clk_en;
|
1039 |
|
|
wire p2_tst_clk_en;
|
1040 |
|
|
wire p3_tst_clk_en;
|
1041 |
|
|
wire p4_tst_clk_en;
|
1042 |
|
|
wire p5_tst_clk_en;
|
1043 |
|
|
|
1044 |
|
|
wire [3:0] p0w_tst_wr_mode;
|
1045 |
|
|
wire [3:0] p0r_tst_mode;
|
1046 |
|
|
wire [3:0] p1w_tst_wr_mode;
|
1047 |
|
|
wire [3:0] p1r_tst_mode;
|
1048 |
|
|
wire [3:0] p2_tst_mode;
|
1049 |
|
|
wire [3:0] p3_tst_mode;
|
1050 |
|
|
wire [3:0] p4_tst_mode;
|
1051 |
|
|
wire [3:0] p5_tst_mode;
|
1052 |
|
|
|
1053 |
|
|
wire p0r_tst_pin_en;
|
1054 |
|
|
wire p0w_tst_pin_en;
|
1055 |
|
|
wire p1r_tst_pin_en;
|
1056 |
|
|
wire p1w_tst_pin_en;
|
1057 |
|
|
wire p2_tst_pin_en;
|
1058 |
|
|
wire p3_tst_pin_en;
|
1059 |
|
|
wire p4_tst_pin_en;
|
1060 |
|
|
wire p5_tst_pin_en;
|
1061 |
|
|
wire p0w_tst_overflow;
|
1062 |
|
|
wire p1w_tst_overflow;
|
1063 |
|
|
|
1064 |
|
|
wire [3:0] p0r_tst_mask_o;
|
1065 |
|
|
wire [3:0] p0w_tst_mask_o;
|
1066 |
|
|
wire [3:0] p1r_tst_mask_o;
|
1067 |
|
|
wire [3:0] p1w_tst_mask_o;
|
1068 |
|
|
wire [3:0] p2_tst_mask_o;
|
1069 |
|
|
wire [3:0] p3_tst_mask_o;
|
1070 |
|
|
wire [3:0] p4_tst_mask_o;
|
1071 |
|
|
wire [3:0] p5_tst_mask_o;
|
1072 |
|
|
wire [3:0] p0r_tst_wr_mask;
|
1073 |
|
|
|
1074 |
|
|
wire [3:0] p1r_tst_wr_mask;
|
1075 |
|
|
wire [31:0] p1r_tst_wr_data;
|
1076 |
|
|
wire [31:0] p0r_tst_wr_data;
|
1077 |
|
|
wire [31:0] p0w_tst_rd_data;
|
1078 |
|
|
wire [31:0] p1w_tst_rd_data;
|
1079 |
|
|
|
1080 |
|
|
wire [38:0] tst_cmd_out;
|
1081 |
|
|
wire MCB_SYSRST;
|
1082 |
|
|
wire ioclk0;
|
1083 |
|
|
wire ioclk90;
|
1084 |
|
|
wire mcb_ui_clk;
|
1085 |
|
|
wire hard_done_cal;
|
1086 |
|
|
wire cke_train;
|
1087 |
|
|
//testing
|
1088 |
|
|
wire ioi_drp_update;
|
1089 |
|
|
wire [7:0] aux_sdi_sdo;
|
1090 |
|
|
|
1091 |
|
|
wire [4:0] mcb_ui_addr;
|
1092 |
|
|
wire [3:0] mcb_ui_dqcount;
|
1093 |
|
|
reg syn_uiclk_pll_lock;
|
1094 |
|
|
|
1095 |
|
|
wire int_sys_rst /* synthesis syn_maxfan = 1 */;
|
1096 |
|
|
// synthesis attribute max_fanout of int_sys_rst is 1
|
1097 |
|
|
|
1098 |
|
|
|
1099 |
|
|
reg [15:0] wait_200us_counter;
|
1100 |
|
|
reg cke_train_reg;
|
1101 |
|
|
reg wait_200us_done_r1,wait_200us_done_r2;
|
1102 |
|
|
|
1103 |
|
|
assign ioclk0 = sysclk_2x;
|
1104 |
|
|
assign ioclk90 = sysclk_2x_180;
|
1105 |
|
|
|
1106 |
|
|
//Added 2/22 - Add flop to pll_lock status signal to improve timing
|
1107 |
|
|
always @ (posedge ui_clk)
|
1108 |
|
|
begin
|
1109 |
|
|
|
1110 |
|
|
syn_uiclk_pll_lock <= pll_lock;
|
1111 |
|
|
|
1112 |
|
|
end
|
1113 |
|
|
assign int_sys_rst = sys_rst | ~syn_uiclk_pll_lock;
|
1114 |
|
|
|
1115 |
|
|
//Address Remapping
|
1116 |
|
|
// Byte Address remapping
|
1117 |
|
|
//
|
1118 |
|
|
// Bank Address[x:0] & Row Address[x:0] & Column Address[x:0]
|
1119 |
|
|
// column address remap for port 0
|
1120 |
|
|
generate // port bus remapping sections for CONFIG 2 15,3,12
|
1121 |
|
|
|
1122 |
|
|
if(C_NUM_DQ_PINS == 16) begin : x16_Addr
|
1123 |
|
|
if (C_MEM_ADDR_ORDER == "ROW_BANK_COLUMN") begin // C_MEM_ADDR_ORDER = 0 : Bank Row Column
|
1124 |
|
|
// port 0 address remapping
|
1125 |
|
|
|
1126 |
|
|
|
1127 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1128 |
|
|
assign p0_cmd_ra = p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1];
|
1129 |
|
|
else
|
1130 |
|
|
assign p0_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS :C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]};
|
1131 |
|
|
|
1132 |
|
|
|
1133 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1134 |
|
|
assign p0_cmd_ba = p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1];
|
1135 |
|
|
else
|
1136 |
|
|
assign p0_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]};
|
1137 |
|
|
|
1138 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1139 |
|
|
assign p0_cmd_ca = p0_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1];
|
1140 |
|
|
else
|
1141 |
|
|
assign p0_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p0_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]};
|
1142 |
|
|
|
1143 |
|
|
|
1144 |
|
|
// port 1 address remapping
|
1145 |
|
|
|
1146 |
|
|
|
1147 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1148 |
|
|
assign p1_cmd_ra = p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1];
|
1149 |
|
|
else
|
1150 |
|
|
assign p1_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS :C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]};
|
1151 |
|
|
|
1152 |
|
|
|
1153 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1154 |
|
|
assign p1_cmd_ba = p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1];
|
1155 |
|
|
else
|
1156 |
|
|
assign p1_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]};
|
1157 |
|
|
|
1158 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1159 |
|
|
assign p1_cmd_ca = p1_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1];
|
1160 |
|
|
else
|
1161 |
|
|
assign p1_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p1_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]};
|
1162 |
|
|
|
1163 |
|
|
// port 2 address remapping
|
1164 |
|
|
|
1165 |
|
|
|
1166 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1167 |
|
|
assign p2_cmd_ra = p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1];
|
1168 |
|
|
else
|
1169 |
|
|
assign p2_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS :C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]};
|
1170 |
|
|
|
1171 |
|
|
|
1172 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1173 |
|
|
assign p2_cmd_ba = p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1];
|
1174 |
|
|
else
|
1175 |
|
|
assign p2_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]};
|
1176 |
|
|
|
1177 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1178 |
|
|
assign p2_cmd_ca = p2_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1];
|
1179 |
|
|
else
|
1180 |
|
|
assign p2_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p2_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]};
|
1181 |
|
|
|
1182 |
|
|
// port 3 address remapping
|
1183 |
|
|
|
1184 |
|
|
|
1185 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1186 |
|
|
assign p3_cmd_ra = p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1];
|
1187 |
|
|
else
|
1188 |
|
|
assign p3_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS :C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]};
|
1189 |
|
|
|
1190 |
|
|
|
1191 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1192 |
|
|
assign p3_cmd_ba = p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1];
|
1193 |
|
|
else
|
1194 |
|
|
assign p3_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]};
|
1195 |
|
|
|
1196 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1197 |
|
|
assign p3_cmd_ca = p3_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1];
|
1198 |
|
|
else
|
1199 |
|
|
assign p3_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p3_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]};
|
1200 |
|
|
|
1201 |
|
|
// port 4 address remapping
|
1202 |
|
|
|
1203 |
|
|
|
1204 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1205 |
|
|
assign p4_cmd_ra = p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1];
|
1206 |
|
|
else
|
1207 |
|
|
assign p4_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS :C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]};
|
1208 |
|
|
|
1209 |
|
|
|
1210 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1211 |
|
|
assign p4_cmd_ba = p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1];
|
1212 |
|
|
else
|
1213 |
|
|
assign p4_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]};
|
1214 |
|
|
|
1215 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1216 |
|
|
assign p4_cmd_ca = p4_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1];
|
1217 |
|
|
else
|
1218 |
|
|
assign p4_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p4_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]};
|
1219 |
|
|
|
1220 |
|
|
// port 5 address remapping
|
1221 |
|
|
|
1222 |
|
|
|
1223 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1224 |
|
|
assign p5_cmd_ra = p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1];
|
1225 |
|
|
else
|
1226 |
|
|
assign p5_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS :C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]};
|
1227 |
|
|
|
1228 |
|
|
|
1229 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1230 |
|
|
assign p5_cmd_ba = p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1];
|
1231 |
|
|
else
|
1232 |
|
|
assign p5_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]};
|
1233 |
|
|
|
1234 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1235 |
|
|
assign p5_cmd_ca = p5_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1];
|
1236 |
|
|
else
|
1237 |
|
|
assign p5_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p5_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]};
|
1238 |
|
|
|
1239 |
|
|
|
1240 |
|
|
|
1241 |
|
|
|
1242 |
|
|
end
|
1243 |
|
|
|
1244 |
|
|
else // ***************C_MEM_ADDR_ORDER = 1 : Row Bank Column
|
1245 |
|
|
begin
|
1246 |
|
|
// port 0 address remapping
|
1247 |
|
|
|
1248 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1249 |
|
|
assign p0_cmd_ba = p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1];
|
1250 |
|
|
else
|
1251 |
|
|
assign p0_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]};
|
1252 |
|
|
|
1253 |
|
|
|
1254 |
|
|
if (C_MEM_ADDR_WIDTH == 15)
|
1255 |
|
|
assign p0_cmd_ra = p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1];
|
1256 |
|
|
else
|
1257 |
|
|
assign p0_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]};
|
1258 |
|
|
|
1259 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1260 |
|
|
assign p0_cmd_ca = p0_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1];
|
1261 |
|
|
else
|
1262 |
|
|
assign p0_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p0_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]};
|
1263 |
|
|
|
1264 |
|
|
|
1265 |
|
|
// port 1 address remapping
|
1266 |
|
|
|
1267 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1268 |
|
|
assign p1_cmd_ba = p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1];
|
1269 |
|
|
else
|
1270 |
|
|
assign p1_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]};
|
1271 |
|
|
|
1272 |
|
|
|
1273 |
|
|
if (C_MEM_ADDR_WIDTH == 15)
|
1274 |
|
|
assign p1_cmd_ra = p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1];
|
1275 |
|
|
else
|
1276 |
|
|
assign p1_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]};
|
1277 |
|
|
|
1278 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1279 |
|
|
assign p1_cmd_ca = p1_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1];
|
1280 |
|
|
else
|
1281 |
|
|
assign p1_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p1_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]};
|
1282 |
|
|
|
1283 |
|
|
// port 2 address remapping
|
1284 |
|
|
|
1285 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1286 |
|
|
assign p2_cmd_ba = p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1];
|
1287 |
|
|
else
|
1288 |
|
|
assign p2_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]};
|
1289 |
|
|
|
1290 |
|
|
|
1291 |
|
|
if (C_MEM_ADDR_WIDTH == 15)
|
1292 |
|
|
assign p2_cmd_ra = p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1];
|
1293 |
|
|
else
|
1294 |
|
|
assign p2_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]};
|
1295 |
|
|
|
1296 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1297 |
|
|
assign p2_cmd_ca = p2_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1];
|
1298 |
|
|
else
|
1299 |
|
|
assign p2_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p2_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]};
|
1300 |
|
|
|
1301 |
|
|
// port 3 address remapping
|
1302 |
|
|
|
1303 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1304 |
|
|
assign p3_cmd_ba = p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1];
|
1305 |
|
|
else
|
1306 |
|
|
assign p3_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]};
|
1307 |
|
|
|
1308 |
|
|
|
1309 |
|
|
if (C_MEM_ADDR_WIDTH == 15)
|
1310 |
|
|
assign p3_cmd_ra = p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1];
|
1311 |
|
|
else
|
1312 |
|
|
assign p3_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]};
|
1313 |
|
|
|
1314 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1315 |
|
|
assign p3_cmd_ca = p3_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1];
|
1316 |
|
|
else
|
1317 |
|
|
assign p3_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p3_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]};
|
1318 |
|
|
|
1319 |
|
|
// port 4 address remapping
|
1320 |
|
|
|
1321 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1322 |
|
|
assign p4_cmd_ba = p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1];
|
1323 |
|
|
else
|
1324 |
|
|
assign p4_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]};
|
1325 |
|
|
|
1326 |
|
|
|
1327 |
|
|
if (C_MEM_ADDR_WIDTH == 15)
|
1328 |
|
|
assign p4_cmd_ra = p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1];
|
1329 |
|
|
else
|
1330 |
|
|
assign p4_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]};
|
1331 |
|
|
|
1332 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1333 |
|
|
assign p4_cmd_ca = p4_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1];
|
1334 |
|
|
else
|
1335 |
|
|
assign p4_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p4_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]};
|
1336 |
|
|
|
1337 |
|
|
// port 5 address remapping
|
1338 |
|
|
|
1339 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1340 |
|
|
assign p5_cmd_ba = p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1];
|
1341 |
|
|
else
|
1342 |
|
|
assign p5_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]};
|
1343 |
|
|
|
1344 |
|
|
|
1345 |
|
|
if (C_MEM_ADDR_WIDTH == 15)
|
1346 |
|
|
assign p5_cmd_ra = p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1];
|
1347 |
|
|
else
|
1348 |
|
|
assign p5_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]};
|
1349 |
|
|
|
1350 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1351 |
|
|
assign p5_cmd_ca = p5_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1];
|
1352 |
|
|
else
|
1353 |
|
|
assign p5_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p5_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]};
|
1354 |
|
|
|
1355 |
|
|
|
1356 |
|
|
end
|
1357 |
|
|
|
1358 |
|
|
end else if(C_NUM_DQ_PINS == 8) begin : x8_Addr
|
1359 |
|
|
if (C_MEM_ADDR_ORDER == "ROW_BANK_COLUMN") begin // C_MEM_ADDR_ORDER = 1 : Bank Row Column
|
1360 |
|
|
// port 0 address remapping
|
1361 |
|
|
|
1362 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1363 |
|
|
assign p0_cmd_ra = p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ];
|
1364 |
|
|
else
|
1365 |
|
|
assign p0_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]};
|
1366 |
|
|
|
1367 |
|
|
|
1368 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1369 |
|
|
assign p0_cmd_ba = p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; //14,3,10
|
1370 |
|
|
else
|
1371 |
|
|
assign p0_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH],
|
1372 |
|
|
p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; //14,3,10
|
1373 |
|
|
|
1374 |
|
|
|
1375 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1376 |
|
|
assign p0_cmd_ca[11:0] = p0_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0];
|
1377 |
|
|
else
|
1378 |
|
|
assign p0_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p0_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]};
|
1379 |
|
|
|
1380 |
|
|
|
1381 |
|
|
// port 1 address remapping
|
1382 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1383 |
|
|
assign p1_cmd_ra = p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ];
|
1384 |
|
|
else
|
1385 |
|
|
assign p1_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]};
|
1386 |
|
|
|
1387 |
|
|
|
1388 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1389 |
|
|
assign p1_cmd_ba = p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; //14,3,10
|
1390 |
|
|
else
|
1391 |
|
|
assign p1_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH],
|
1392 |
|
|
p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; //14,3,10
|
1393 |
|
|
|
1394 |
|
|
|
1395 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1396 |
|
|
assign p1_cmd_ca[11:0] = p1_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0];
|
1397 |
|
|
else
|
1398 |
|
|
assign p1_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p1_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]};
|
1399 |
|
|
|
1400 |
|
|
|
1401 |
|
|
// port 2 address remapping
|
1402 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1403 |
|
|
assign p2_cmd_ra = p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ];
|
1404 |
|
|
else
|
1405 |
|
|
assign p2_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]};
|
1406 |
|
|
|
1407 |
|
|
|
1408 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1409 |
|
|
assign p2_cmd_ba = p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; //14,3,10
|
1410 |
|
|
else
|
1411 |
|
|
assign p2_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH],
|
1412 |
|
|
p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; //14,2,10 ***
|
1413 |
|
|
|
1414 |
|
|
|
1415 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1416 |
|
|
assign p2_cmd_ca[11:0] = p2_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0];
|
1417 |
|
|
else
|
1418 |
|
|
assign p2_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p2_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]};
|
1419 |
|
|
|
1420 |
|
|
|
1421 |
|
|
|
1422 |
|
|
// port 3 address remapping
|
1423 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1424 |
|
|
assign p3_cmd_ra = p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ];
|
1425 |
|
|
else
|
1426 |
|
|
assign p3_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]};
|
1427 |
|
|
|
1428 |
|
|
|
1429 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1430 |
|
|
assign p3_cmd_ba = p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; //14,3,10
|
1431 |
|
|
else
|
1432 |
|
|
assign p3_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH],
|
1433 |
|
|
p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; //14,3,10
|
1434 |
|
|
|
1435 |
|
|
|
1436 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1437 |
|
|
assign p3_cmd_ca[11:0] = p3_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0];
|
1438 |
|
|
else
|
1439 |
|
|
assign p3_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p3_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]};
|
1440 |
|
|
|
1441 |
|
|
|
1442 |
|
|
// port 4 address remapping
|
1443 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1444 |
|
|
assign p4_cmd_ra = p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ];
|
1445 |
|
|
else
|
1446 |
|
|
assign p4_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]};
|
1447 |
|
|
|
1448 |
|
|
|
1449 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1450 |
|
|
assign p4_cmd_ba = p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; //14,3,10
|
1451 |
|
|
else
|
1452 |
|
|
assign p4_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH],
|
1453 |
|
|
p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; //14,3,10
|
1454 |
|
|
|
1455 |
|
|
|
1456 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1457 |
|
|
assign p4_cmd_ca[11:0] = p4_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0];
|
1458 |
|
|
else
|
1459 |
|
|
assign p4_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p4_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]};
|
1460 |
|
|
|
1461 |
|
|
|
1462 |
|
|
// port 5 address remapping
|
1463 |
|
|
|
1464 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1465 |
|
|
assign p5_cmd_ra = p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ];
|
1466 |
|
|
else
|
1467 |
|
|
assign p5_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]};
|
1468 |
|
|
|
1469 |
|
|
|
1470 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1471 |
|
|
assign p5_cmd_ba = p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; //14,3,10
|
1472 |
|
|
else
|
1473 |
|
|
assign p5_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH],
|
1474 |
|
|
p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; //14,3,10
|
1475 |
|
|
|
1476 |
|
|
|
1477 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1478 |
|
|
assign p5_cmd_ca[11:0] = p5_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0];
|
1479 |
|
|
else
|
1480 |
|
|
assign p5_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p5_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]};
|
1481 |
|
|
|
1482 |
|
|
end
|
1483 |
|
|
|
1484 |
|
|
else // x8 ***************C_MEM_ADDR_ORDER = 0 : Bank Row Column
|
1485 |
|
|
begin
|
1486 |
|
|
// port 0 address remapping
|
1487 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1488 |
|
|
assign p0_cmd_ba = p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ];
|
1489 |
|
|
else
|
1490 |
|
|
assign p0_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH],
|
1491 |
|
|
p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]};
|
1492 |
|
|
|
1493 |
|
|
|
1494 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1495 |
|
|
assign p0_cmd_ra = p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ];
|
1496 |
|
|
else
|
1497 |
|
|
assign p0_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]};
|
1498 |
|
|
|
1499 |
|
|
|
1500 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1501 |
|
|
assign p0_cmd_ca[11:0] = p0_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0];
|
1502 |
|
|
else
|
1503 |
|
|
assign p0_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p0_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]};
|
1504 |
|
|
|
1505 |
|
|
|
1506 |
|
|
// port 1 address remapping
|
1507 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1508 |
|
|
assign p1_cmd_ba = p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ];
|
1509 |
|
|
else
|
1510 |
|
|
assign p1_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH],
|
1511 |
|
|
p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]};
|
1512 |
|
|
|
1513 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1514 |
|
|
assign p1_cmd_ra = p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ];
|
1515 |
|
|
else
|
1516 |
|
|
assign p1_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]};
|
1517 |
|
|
|
1518 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1519 |
|
|
assign p1_cmd_ca[11:0] = p1_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0];
|
1520 |
|
|
else
|
1521 |
|
|
assign p1_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p1_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]};
|
1522 |
|
|
|
1523 |
|
|
//port 2 address remapping
|
1524 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank 2,13,10 24,23
|
1525 |
|
|
assign p2_cmd_ba = p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ];
|
1526 |
|
|
else
|
1527 |
|
|
assign p2_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH],
|
1528 |
|
|
p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]};
|
1529 |
|
|
|
1530 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1531 |
|
|
assign p2_cmd_ra = p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ];
|
1532 |
|
|
else
|
1533 |
|
|
assign p2_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]};
|
1534 |
|
|
|
1535 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1536 |
|
|
assign p2_cmd_ca[11:0] = p2_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0];
|
1537 |
|
|
else
|
1538 |
|
|
assign p2_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p2_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]};
|
1539 |
|
|
|
1540 |
|
|
// port 3 address remapping
|
1541 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1542 |
|
|
assign p3_cmd_ba = p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ];
|
1543 |
|
|
else
|
1544 |
|
|
assign p3_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH],
|
1545 |
|
|
p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]};
|
1546 |
|
|
|
1547 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1548 |
|
|
assign p3_cmd_ra = p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ];
|
1549 |
|
|
else
|
1550 |
|
|
assign p3_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]};
|
1551 |
|
|
|
1552 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1553 |
|
|
assign p3_cmd_ca[11:0] = p3_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0];
|
1554 |
|
|
else
|
1555 |
|
|
assign p3_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p3_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]};
|
1556 |
|
|
|
1557 |
|
|
|
1558 |
|
|
// port 4 address remapping
|
1559 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1560 |
|
|
assign p4_cmd_ba = p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ];
|
1561 |
|
|
else
|
1562 |
|
|
assign p4_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH],
|
1563 |
|
|
p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]};
|
1564 |
|
|
|
1565 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1566 |
|
|
assign p4_cmd_ra = p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ];
|
1567 |
|
|
else
|
1568 |
|
|
assign p4_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]};
|
1569 |
|
|
|
1570 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1571 |
|
|
assign p4_cmd_ca[11:0] = p4_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0];
|
1572 |
|
|
else
|
1573 |
|
|
assign p4_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p4_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]};
|
1574 |
|
|
|
1575 |
|
|
// port 5 address remapping
|
1576 |
|
|
|
1577 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1578 |
|
|
assign p5_cmd_ba = p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ];
|
1579 |
|
|
else
|
1580 |
|
|
assign p5_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH],
|
1581 |
|
|
p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]};
|
1582 |
|
|
|
1583 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1584 |
|
|
assign p5_cmd_ra = p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ];
|
1585 |
|
|
else
|
1586 |
|
|
assign p5_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]};
|
1587 |
|
|
|
1588 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1589 |
|
|
assign p5_cmd_ca[11:0] = p5_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0];
|
1590 |
|
|
else
|
1591 |
|
|
assign p5_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p5_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]};
|
1592 |
|
|
|
1593 |
|
|
end
|
1594 |
|
|
|
1595 |
|
|
//
|
1596 |
|
|
|
1597 |
|
|
end else if(C_NUM_DQ_PINS == 4) begin : x4_Addr
|
1598 |
|
|
|
1599 |
|
|
if (C_MEM_ADDR_ORDER == "ROW_BANK_COLUMN") begin // C_MEM_ADDR_ORDER = 1 : Row Bank Column
|
1600 |
|
|
|
1601 |
|
|
// port 0 address remapping
|
1602 |
|
|
|
1603 |
|
|
|
1604 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1605 |
|
|
assign p0_cmd_ra = p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1];
|
1606 |
|
|
else
|
1607 |
|
|
assign p0_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]};
|
1608 |
|
|
|
1609 |
|
|
|
1610 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1611 |
|
|
assign p0_cmd_ba = p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1];
|
1612 |
|
|
else
|
1613 |
|
|
assign p0_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]};
|
1614 |
|
|
|
1615 |
|
|
|
1616 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1617 |
|
|
assign p0_cmd_ca = {p0_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; //14,3,11
|
1618 |
|
|
else
|
1619 |
|
|
assign p0_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p0_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1620 |
|
|
|
1621 |
|
|
|
1622 |
|
|
// port 1 address remapping
|
1623 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1624 |
|
|
assign p1_cmd_ra = p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1];
|
1625 |
|
|
else
|
1626 |
|
|
assign p1_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]};
|
1627 |
|
|
|
1628 |
|
|
|
1629 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1630 |
|
|
assign p1_cmd_ba = p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1];
|
1631 |
|
|
else
|
1632 |
|
|
assign p1_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]};
|
1633 |
|
|
|
1634 |
|
|
|
1635 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1636 |
|
|
assign p1_cmd_ca = {p1_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; //14,3,11
|
1637 |
|
|
else
|
1638 |
|
|
assign p1_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p1_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1639 |
|
|
|
1640 |
|
|
// port 2 address remapping
|
1641 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1642 |
|
|
assign p2_cmd_ra = p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1];
|
1643 |
|
|
else
|
1644 |
|
|
assign p2_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]};
|
1645 |
|
|
|
1646 |
|
|
|
1647 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1648 |
|
|
assign p2_cmd_ba = p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1];
|
1649 |
|
|
else
|
1650 |
|
|
assign p2_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]};
|
1651 |
|
|
|
1652 |
|
|
|
1653 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1654 |
|
|
assign p2_cmd_ca = {p2_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; //14,3,11
|
1655 |
|
|
else
|
1656 |
|
|
assign p2_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p2_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1657 |
|
|
|
1658 |
|
|
// port 3 address remapping
|
1659 |
|
|
|
1660 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1661 |
|
|
assign p3_cmd_ra = p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1];
|
1662 |
|
|
else
|
1663 |
|
|
assign p3_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]};
|
1664 |
|
|
|
1665 |
|
|
|
1666 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1667 |
|
|
assign p3_cmd_ba = p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1];
|
1668 |
|
|
else
|
1669 |
|
|
assign p3_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]};
|
1670 |
|
|
|
1671 |
|
|
|
1672 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1673 |
|
|
assign p3_cmd_ca = {p3_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; //14,3,11
|
1674 |
|
|
else
|
1675 |
|
|
assign p3_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p3_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1676 |
|
|
|
1677 |
|
|
|
1678 |
|
|
|
1679 |
|
|
if(C_PORT_CONFIG == "B32_B32_R32_R32_R32_R32" ||
|
1680 |
|
|
C_PORT_CONFIG == "B32_B32_R32_R32_R32_W32" ||
|
1681 |
|
|
C_PORT_CONFIG == "B32_B32_R32_R32_W32_R32" ||
|
1682 |
|
|
C_PORT_CONFIG == "B32_B32_R32_R32_W32_W32" ||
|
1683 |
|
|
C_PORT_CONFIG == "B32_B32_R32_W32_R32_R32" ||
|
1684 |
|
|
C_PORT_CONFIG == "B32_B32_R32_W32_R32_W32" ||
|
1685 |
|
|
C_PORT_CONFIG == "B32_B32_R32_W32_W32_R32" ||
|
1686 |
|
|
C_PORT_CONFIG == "B32_B32_R32_W32_W32_W32" ||
|
1687 |
|
|
C_PORT_CONFIG == "B32_B32_W32_R32_R32_R32" ||
|
1688 |
|
|
C_PORT_CONFIG == "B32_B32_W32_R32_R32_W32" ||
|
1689 |
|
|
C_PORT_CONFIG == "B32_B32_W32_R32_W32_R32" ||
|
1690 |
|
|
C_PORT_CONFIG == "B32_B32_W32_R32_W32_W32" ||
|
1691 |
|
|
C_PORT_CONFIG == "B32_B32_W32_W32_R32_R32" ||
|
1692 |
|
|
C_PORT_CONFIG == "B32_B32_W32_W32_R32_W32" ||
|
1693 |
|
|
C_PORT_CONFIG == "B32_B32_W32_W32_W32_R32" ||
|
1694 |
|
|
C_PORT_CONFIG == "B32_B32_W32_W32_W32_W32"
|
1695 |
|
|
) //begin : x4_Addr_CFG1_OR_CFG2
|
1696 |
|
|
begin
|
1697 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1698 |
|
|
assign p4_cmd_ra = p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1];
|
1699 |
|
|
else
|
1700 |
|
|
assign p4_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]};
|
1701 |
|
|
|
1702 |
|
|
|
1703 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1704 |
|
|
assign p4_cmd_ba = p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1];
|
1705 |
|
|
else
|
1706 |
|
|
assign p4_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]};
|
1707 |
|
|
|
1708 |
|
|
|
1709 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1710 |
|
|
assign p4_cmd_ca = {p4_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; //14,3,11
|
1711 |
|
|
else
|
1712 |
|
|
assign p4_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p4_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1713 |
|
|
|
1714 |
|
|
|
1715 |
|
|
|
1716 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1717 |
|
|
assign p5_cmd_ra = p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1];
|
1718 |
|
|
else
|
1719 |
|
|
assign p5_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]};
|
1720 |
|
|
|
1721 |
|
|
|
1722 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1723 |
|
|
assign p5_cmd_ba = p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1];
|
1724 |
|
|
else
|
1725 |
|
|
assign p5_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]};
|
1726 |
|
|
|
1727 |
|
|
|
1728 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1729 |
|
|
assign p5_cmd_ca = {p5_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; //14,3,11
|
1730 |
|
|
else
|
1731 |
|
|
assign p5_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p5_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1732 |
|
|
|
1733 |
|
|
end
|
1734 |
|
|
|
1735 |
|
|
|
1736 |
|
|
end
|
1737 |
|
|
else // C_MEM_ADDR_ORDER = 1 : Row Bank Column
|
1738 |
|
|
begin
|
1739 |
|
|
|
1740 |
|
|
// port 0 address remapping
|
1741 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1742 |
|
|
assign p0_cmd_ba = p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1];
|
1743 |
|
|
else
|
1744 |
|
|
assign p0_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]};
|
1745 |
|
|
|
1746 |
|
|
|
1747 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1748 |
|
|
assign p0_cmd_ra = p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1];
|
1749 |
|
|
else
|
1750 |
|
|
assign p0_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]};
|
1751 |
|
|
|
1752 |
|
|
|
1753 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1754 |
|
|
assign p0_cmd_ca = {p0_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1755 |
|
|
else
|
1756 |
|
|
assign p0_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p0_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1757 |
|
|
|
1758 |
|
|
|
1759 |
|
|
// port 1 address remapping
|
1760 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1761 |
|
|
assign p1_cmd_ba = p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1];
|
1762 |
|
|
else
|
1763 |
|
|
assign p1_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]};
|
1764 |
|
|
|
1765 |
|
|
|
1766 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1767 |
|
|
assign p1_cmd_ra = p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1];
|
1768 |
|
|
else
|
1769 |
|
|
assign p1_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]};
|
1770 |
|
|
|
1771 |
|
|
|
1772 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1773 |
|
|
assign p1_cmd_ca = {p1_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1774 |
|
|
else
|
1775 |
|
|
assign p1_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p1_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1776 |
|
|
// port 2 address remapping
|
1777 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1778 |
|
|
assign p2_cmd_ba = p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1];
|
1779 |
|
|
else
|
1780 |
|
|
assign p2_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]};
|
1781 |
|
|
|
1782 |
|
|
//***
|
1783 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1784 |
|
|
assign p2_cmd_ra = p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1];
|
1785 |
|
|
else
|
1786 |
|
|
assign p2_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]};
|
1787 |
|
|
|
1788 |
|
|
|
1789 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1790 |
|
|
assign p2_cmd_ca = {p2_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1791 |
|
|
else
|
1792 |
|
|
assign p2_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p2_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1793 |
|
|
// port 3 address remapping
|
1794 |
|
|
|
1795 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1796 |
|
|
assign p3_cmd_ba = p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1];
|
1797 |
|
|
else
|
1798 |
|
|
assign p3_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]};
|
1799 |
|
|
|
1800 |
|
|
|
1801 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1802 |
|
|
assign p3_cmd_ra = p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1];
|
1803 |
|
|
else
|
1804 |
|
|
assign p3_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]};
|
1805 |
|
|
|
1806 |
|
|
|
1807 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1808 |
|
|
assign p3_cmd_ca = {p3_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1809 |
|
|
else
|
1810 |
|
|
assign p3_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p3_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1811 |
|
|
|
1812 |
|
|
|
1813 |
|
|
if(C_PORT_CONFIG == "B32_B32_R32_R32_R32_R32" ||
|
1814 |
|
|
C_PORT_CONFIG == "B32_B32_R32_R32_R32_W32" ||
|
1815 |
|
|
C_PORT_CONFIG == "B32_B32_R32_R32_W32_R32" ||
|
1816 |
|
|
C_PORT_CONFIG == "B32_B32_R32_R32_W32_W32" ||
|
1817 |
|
|
C_PORT_CONFIG == "B32_B32_R32_W32_R32_R32" ||
|
1818 |
|
|
C_PORT_CONFIG == "B32_B32_R32_W32_R32_W32" ||
|
1819 |
|
|
C_PORT_CONFIG == "B32_B32_R32_W32_W32_R32" ||
|
1820 |
|
|
C_PORT_CONFIG == "B32_B32_R32_W32_W32_W32" ||
|
1821 |
|
|
C_PORT_CONFIG == "B32_B32_W32_R32_R32_R32" ||
|
1822 |
|
|
C_PORT_CONFIG == "B32_B32_W32_R32_R32_W32" ||
|
1823 |
|
|
C_PORT_CONFIG == "B32_B32_W32_R32_W32_R32" ||
|
1824 |
|
|
C_PORT_CONFIG == "B32_B32_W32_R32_W32_W32" ||
|
1825 |
|
|
C_PORT_CONFIG == "B32_B32_W32_W32_R32_R32" ||
|
1826 |
|
|
C_PORT_CONFIG == "B32_B32_W32_W32_R32_W32" ||
|
1827 |
|
|
C_PORT_CONFIG == "B32_B32_W32_W32_W32_R32" ||
|
1828 |
|
|
C_PORT_CONFIG == "B32_B32_W32_W32_W32_W32"
|
1829 |
|
|
) //begin : x4_Addr_CFG1_OR_CFG2
|
1830 |
|
|
begin
|
1831 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1832 |
|
|
assign p4_cmd_ba = p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1];
|
1833 |
|
|
else
|
1834 |
|
|
assign p4_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]};
|
1835 |
|
|
|
1836 |
|
|
|
1837 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1838 |
|
|
assign p4_cmd_ra = p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1];
|
1839 |
|
|
else
|
1840 |
|
|
assign p4_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]};
|
1841 |
|
|
|
1842 |
|
|
|
1843 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1844 |
|
|
assign p4_cmd_ca = {p4_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1845 |
|
|
else
|
1846 |
|
|
assign p4_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p4_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1847 |
|
|
|
1848 |
|
|
|
1849 |
|
|
if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank
|
1850 |
|
|
assign p5_cmd_ba = p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1];
|
1851 |
|
|
else
|
1852 |
|
|
assign p5_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]};
|
1853 |
|
|
|
1854 |
|
|
|
1855 |
|
|
if (C_MEM_ADDR_WIDTH == 15) //Row
|
1856 |
|
|
assign p5_cmd_ra = p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1];
|
1857 |
|
|
else
|
1858 |
|
|
assign p5_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]};
|
1859 |
|
|
|
1860 |
|
|
|
1861 |
|
|
if (C_MEM_NUM_COL_BITS == 12) //Column
|
1862 |
|
|
assign p5_cmd_ca = {p5_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1863 |
|
|
else
|
1864 |
|
|
assign p5_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p5_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0};
|
1865 |
|
|
end
|
1866 |
|
|
|
1867 |
|
|
|
1868 |
|
|
|
1869 |
|
|
end
|
1870 |
|
|
|
1871 |
|
|
end // block: x4_Addr
|
1872 |
|
|
|
1873 |
|
|
|
1874 |
|
|
endgenerate
|
1875 |
|
|
|
1876 |
|
|
|
1877 |
|
|
|
1878 |
|
|
generate
|
1879 |
|
|
// if(C_PORT_CONFIG[183:160] == "B32") begin : u_config1_0
|
1880 |
|
|
if(C_PORT_CONFIG == "B32_B32_R32_R32_R32_R32" ||
|
1881 |
|
|
C_PORT_CONFIG == "B32_B32_R32_R32_R32_W32" ||
|
1882 |
|
|
C_PORT_CONFIG == "B32_B32_R32_R32_W32_R32" ||
|
1883 |
|
|
C_PORT_CONFIG == "B32_B32_R32_R32_W32_W32" ||
|
1884 |
|
|
C_PORT_CONFIG == "B32_B32_R32_W32_R32_R32" ||
|
1885 |
|
|
C_PORT_CONFIG == "B32_B32_R32_W32_R32_W32" ||
|
1886 |
|
|
C_PORT_CONFIG == "B32_B32_R32_W32_W32_R32" ||
|
1887 |
|
|
C_PORT_CONFIG == "B32_B32_R32_W32_W32_W32" ||
|
1888 |
|
|
C_PORT_CONFIG == "B32_B32_W32_R32_R32_R32" ||
|
1889 |
|
|
C_PORT_CONFIG == "B32_B32_W32_R32_R32_W32" ||
|
1890 |
|
|
C_PORT_CONFIG == "B32_B32_W32_R32_W32_R32" ||
|
1891 |
|
|
C_PORT_CONFIG == "B32_B32_W32_R32_W32_W32" ||
|
1892 |
|
|
C_PORT_CONFIG == "B32_B32_W32_W32_R32_R32" ||
|
1893 |
|
|
C_PORT_CONFIG == "B32_B32_W32_W32_R32_W32" ||
|
1894 |
|
|
C_PORT_CONFIG == "B32_B32_W32_W32_W32_R32" ||
|
1895 |
|
|
C_PORT_CONFIG == "B32_B32_W32_W32_W32_W32"
|
1896 |
|
|
) begin : u_config1_0
|
1897 |
|
|
|
1898 |
|
|
//synthesis translate_off
|
1899 |
|
|
always @(*)
|
1900 |
|
|
begin
|
1901 |
|
|
if ( C_PORT_CONFIG[119:96] == "W32" && p2_cmd_en == 1'b1
|
1902 |
|
|
&& p2_cmd_instr[2] == 1'b0 && p2_cmd_instr[0] == 1'b1 )
|
1903 |
|
|
begin
|
1904 |
|
|
$display("ERROR - Invalid Command for write only port 2");
|
1905 |
|
|
$finish;
|
1906 |
|
|
end
|
1907 |
|
|
end
|
1908 |
|
|
|
1909 |
|
|
always @(*)
|
1910 |
|
|
begin
|
1911 |
|
|
if ( C_PORT_CONFIG[119:96] == "R32" && p2_cmd_en == 1'b1
|
1912 |
|
|
&& p2_cmd_instr[2] == 1'b0 && p2_cmd_instr[0] == 1'b0 )
|
1913 |
|
|
begin
|
1914 |
|
|
$display("ERROR - Invalid Command for read only port 2");
|
1915 |
|
|
$finish;
|
1916 |
|
|
end
|
1917 |
|
|
end
|
1918 |
|
|
// Catch Invalid command during simulation for Port 3
|
1919 |
|
|
always @(*)
|
1920 |
|
|
begin
|
1921 |
|
|
if ( C_PORT_CONFIG[87:64] == "W32" && p3_cmd_en == 1'b1
|
1922 |
|
|
&& p3_cmd_instr[2] == 1'b0 && p3_cmd_instr[0] == 1'b1 )
|
1923 |
|
|
begin
|
1924 |
|
|
$display("ERROR - Invalid Command for write only port 3");
|
1925 |
|
|
$finish;
|
1926 |
|
|
end
|
1927 |
|
|
end
|
1928 |
|
|
|
1929 |
|
|
always @(*)
|
1930 |
|
|
begin
|
1931 |
|
|
if ( C_PORT_CONFIG[87:64] == "R32" && p3_cmd_en == 1'b1
|
1932 |
|
|
&& p3_cmd_instr[2] == 1'b0 && p3_cmd_instr[0] == 1'b0 )
|
1933 |
|
|
begin
|
1934 |
|
|
$display("ERROR - Invalid Command for read only port 3");
|
1935 |
|
|
$finish;
|
1936 |
|
|
end
|
1937 |
|
|
end
|
1938 |
|
|
|
1939 |
|
|
// Catch Invalid command during simulation for Port 4
|
1940 |
|
|
always @(*)
|
1941 |
|
|
begin
|
1942 |
|
|
if ( C_PORT_CONFIG[55:32] == "W32" && p4_cmd_en == 1'b1
|
1943 |
|
|
&& p4_cmd_instr[2] == 1'b0 && p4_cmd_instr[0] == 1'b1 )
|
1944 |
|
|
begin
|
1945 |
|
|
$display("ERROR - Invalid Command for write only port 4");
|
1946 |
|
|
$finish;
|
1947 |
|
|
end
|
1948 |
|
|
end
|
1949 |
|
|
|
1950 |
|
|
always @(*)
|
1951 |
|
|
begin
|
1952 |
|
|
if ( C_PORT_CONFIG[55:32] == "R32" && p4_cmd_en == 1'b1
|
1953 |
|
|
&& p4_cmd_instr[2] == 1'b0 && p4_cmd_instr[0] == 1'b0 )
|
1954 |
|
|
begin
|
1955 |
|
|
$display("ERROR - Invalid Command for read only port 4");
|
1956 |
|
|
$finish;
|
1957 |
|
|
end
|
1958 |
|
|
end
|
1959 |
|
|
// Catch Invalid command during simulation for Port 5
|
1960 |
|
|
always @(*)
|
1961 |
|
|
begin
|
1962 |
|
|
if ( C_PORT_CONFIG[23:0] == "W32" && p5_cmd_en == 1'b1
|
1963 |
|
|
&& p5_cmd_instr[2] == 1'b0 && p5_cmd_instr[0] == 1'b1 )
|
1964 |
|
|
begin
|
1965 |
|
|
$display("ERROR - Invalid Command for write only port 5");
|
1966 |
|
|
$finish;
|
1967 |
|
|
end
|
1968 |
|
|
end
|
1969 |
|
|
|
1970 |
|
|
always @(*)
|
1971 |
|
|
begin
|
1972 |
|
|
if ( C_PORT_CONFIG[23:0] == "R32" && p5_cmd_en == 1'b1
|
1973 |
|
|
&& p5_cmd_instr[2] == 1'b0 && p5_cmd_instr[0] == 1'b0 )
|
1974 |
|
|
begin
|
1975 |
|
|
$display("ERROR - Invalid Command for read only port 5");
|
1976 |
|
|
$finish;
|
1977 |
|
|
end
|
1978 |
|
|
end
|
1979 |
|
|
//synthesis translate_on
|
1980 |
|
|
|
1981 |
|
|
|
1982 |
|
|
// the local declaration of input port signals doesn't work. The mig_p1_xxx through mig_p5_xxx always ends up
|
1983 |
|
|
// high Z even though there are signals on p1_cmd_xxx through p5_cmd_xxxx.
|
1984 |
|
|
// The only solutions that I have is to have MIG tool remove the entire internal codes that doesn't belongs to the Configuration..
|
1985 |
|
|
//
|
1986 |
|
|
|
1987 |
|
|
// Inputs from Application CMD Port
|
1988 |
|
|
|
1989 |
|
|
if (C_PORT_ENABLE[0] == 1'b1)
|
1990 |
|
|
begin
|
1991 |
|
|
|
1992 |
|
|
assign mig_p0_arb_en = p0_arb_en ;
|
1993 |
|
|
assign mig_p0_cmd_clk = p0_cmd_clk ;
|
1994 |
|
|
assign mig_p0_cmd_en = p0_cmd_en ;
|
1995 |
|
|
assign mig_p0_cmd_ra = p0_cmd_ra ;
|
1996 |
|
|
assign mig_p0_cmd_ba = p0_cmd_ba ;
|
1997 |
|
|
assign mig_p0_cmd_ca = p0_cmd_ca ;
|
1998 |
|
|
assign mig_p0_cmd_instr = p0_cmd_instr;
|
1999 |
|
|
assign mig_p0_cmd_bl = {(p0_cmd_instr[2] | p0_cmd_bl[5]),p0_cmd_bl[4:0]} ;
|
2000 |
|
|
assign p0_cmd_empty = mig_p0_cmd_empty;
|
2001 |
|
|
assign p0_cmd_full = mig_p0_cmd_full ;
|
2002 |
|
|
|
2003 |
|
|
end else
|
2004 |
|
|
begin
|
2005 |
|
|
|
2006 |
|
|
assign mig_p0_arb_en = 'b0;
|
2007 |
|
|
assign mig_p0_cmd_clk = 'b0;
|
2008 |
|
|
assign mig_p0_cmd_en = 'b0;
|
2009 |
|
|
assign mig_p0_cmd_ra = 'b0;
|
2010 |
|
|
assign mig_p0_cmd_ba = 'b0;
|
2011 |
|
|
assign mig_p0_cmd_ca = 'b0;
|
2012 |
|
|
assign mig_p0_cmd_instr = 'b0;
|
2013 |
|
|
assign mig_p0_cmd_bl = 'b0;
|
2014 |
|
|
assign p0_cmd_empty = 'b0;
|
2015 |
|
|
assign p0_cmd_full = 'b0;
|
2016 |
|
|
|
2017 |
|
|
end
|
2018 |
|
|
|
2019 |
|
|
|
2020 |
|
|
if (C_PORT_ENABLE[1] == 1'b1)
|
2021 |
|
|
begin
|
2022 |
|
|
|
2023 |
|
|
|
2024 |
|
|
assign mig_p1_arb_en = p1_arb_en ;
|
2025 |
|
|
assign mig_p1_cmd_clk = p1_cmd_clk ;
|
2026 |
|
|
assign mig_p1_cmd_en = p1_cmd_en ;
|
2027 |
|
|
assign mig_p1_cmd_ra = p1_cmd_ra ;
|
2028 |
|
|
assign mig_p1_cmd_ba = p1_cmd_ba ;
|
2029 |
|
|
assign mig_p1_cmd_ca = p1_cmd_ca ;
|
2030 |
|
|
assign mig_p1_cmd_instr = p1_cmd_instr;
|
2031 |
|
|
assign mig_p1_cmd_bl = {(p1_cmd_instr[2] | p1_cmd_bl[5]),p1_cmd_bl[4:0]} ;
|
2032 |
|
|
assign p1_cmd_empty = mig_p1_cmd_empty;
|
2033 |
|
|
assign p1_cmd_full = mig_p1_cmd_full ;
|
2034 |
|
|
|
2035 |
|
|
end else
|
2036 |
|
|
begin
|
2037 |
|
|
assign mig_p1_arb_en = 'b0;
|
2038 |
|
|
assign mig_p1_cmd_clk = 'b0;
|
2039 |
|
|
assign mig_p1_cmd_en = 'b0;
|
2040 |
|
|
assign mig_p1_cmd_ra = 'b0;
|
2041 |
|
|
assign mig_p1_cmd_ba = 'b0;
|
2042 |
|
|
assign mig_p1_cmd_ca = 'b0;
|
2043 |
|
|
assign mig_p1_cmd_instr = 'b0;
|
2044 |
|
|
assign mig_p1_cmd_bl = 'b0;
|
2045 |
|
|
assign p1_cmd_empty = 'b0;
|
2046 |
|
|
assign p1_cmd_full = 'b0;
|
2047 |
|
|
|
2048 |
|
|
|
2049 |
|
|
end
|
2050 |
|
|
|
2051 |
|
|
|
2052 |
|
|
if (C_PORT_ENABLE[2] == 1'b1)
|
2053 |
|
|
begin
|
2054 |
|
|
|
2055 |
|
|
assign mig_p2_arb_en = p2_arb_en ;
|
2056 |
|
|
assign mig_p2_cmd_clk = p2_cmd_clk ;
|
2057 |
|
|
assign mig_p2_cmd_en = p2_cmd_en ;
|
2058 |
|
|
assign mig_p2_cmd_ra = p2_cmd_ra ;
|
2059 |
|
|
assign mig_p2_cmd_ba = p2_cmd_ba ;
|
2060 |
|
|
assign mig_p2_cmd_ca = p2_cmd_ca ;
|
2061 |
|
|
assign mig_p2_cmd_instr = p2_cmd_instr;
|
2062 |
|
|
assign mig_p2_cmd_bl = {(p2_cmd_instr[2] | p2_cmd_bl[5]),p2_cmd_bl[4:0]} ;
|
2063 |
|
|
assign p2_cmd_empty = mig_p2_cmd_empty;
|
2064 |
|
|
assign p2_cmd_full = mig_p2_cmd_full ;
|
2065 |
|
|
|
2066 |
|
|
end else
|
2067 |
|
|
begin
|
2068 |
|
|
|
2069 |
|
|
assign mig_p2_arb_en = 'b0;
|
2070 |
|
|
assign mig_p2_cmd_clk = 'b0;
|
2071 |
|
|
assign mig_p2_cmd_en = 'b0;
|
2072 |
|
|
assign mig_p2_cmd_ra = 'b0;
|
2073 |
|
|
assign mig_p2_cmd_ba = 'b0;
|
2074 |
|
|
assign mig_p2_cmd_ca = 'b0;
|
2075 |
|
|
assign mig_p2_cmd_instr = 'b0;
|
2076 |
|
|
assign mig_p2_cmd_bl = 'b0;
|
2077 |
|
|
assign p2_cmd_empty = 'b0;
|
2078 |
|
|
assign p2_cmd_full = 'b0;
|
2079 |
|
|
|
2080 |
|
|
end
|
2081 |
|
|
|
2082 |
|
|
|
2083 |
|
|
|
2084 |
|
|
if (C_PORT_ENABLE[3] == 1'b1)
|
2085 |
|
|
begin
|
2086 |
|
|
|
2087 |
|
|
assign mig_p3_arb_en = p3_arb_en ;
|
2088 |
|
|
assign mig_p3_cmd_clk = p3_cmd_clk ;
|
2089 |
|
|
assign mig_p3_cmd_en = p3_cmd_en ;
|
2090 |
|
|
assign mig_p3_cmd_ra = p3_cmd_ra ;
|
2091 |
|
|
assign mig_p3_cmd_ba = p3_cmd_ba ;
|
2092 |
|
|
assign mig_p3_cmd_ca = p3_cmd_ca ;
|
2093 |
|
|
assign mig_p3_cmd_instr = p3_cmd_instr;
|
2094 |
|
|
assign mig_p3_cmd_bl = {(p3_cmd_instr[2] | p3_cmd_bl[5]),p3_cmd_bl[4:0]} ;
|
2095 |
|
|
assign p3_cmd_empty = mig_p3_cmd_empty;
|
2096 |
|
|
assign p3_cmd_full = mig_p3_cmd_full ;
|
2097 |
|
|
|
2098 |
|
|
end else
|
2099 |
|
|
begin
|
2100 |
|
|
assign mig_p3_arb_en = 'b0;
|
2101 |
|
|
assign mig_p3_cmd_clk = 'b0;
|
2102 |
|
|
assign mig_p3_cmd_en = 'b0;
|
2103 |
|
|
assign mig_p3_cmd_ra = 'b0;
|
2104 |
|
|
assign mig_p3_cmd_ba = 'b0;
|
2105 |
|
|
assign mig_p3_cmd_ca = 'b0;
|
2106 |
|
|
assign mig_p3_cmd_instr = 'b0;
|
2107 |
|
|
assign mig_p3_cmd_bl = 'b0;
|
2108 |
|
|
assign p3_cmd_empty = 'b0;
|
2109 |
|
|
assign p3_cmd_full = 'b0;
|
2110 |
|
|
|
2111 |
|
|
end
|
2112 |
|
|
|
2113 |
|
|
if (C_PORT_ENABLE[4] == 1'b1)
|
2114 |
|
|
begin
|
2115 |
|
|
|
2116 |
|
|
assign mig_p4_arb_en = p4_arb_en ;
|
2117 |
|
|
assign mig_p4_cmd_clk = p4_cmd_clk ;
|
2118 |
|
|
assign mig_p4_cmd_en = p4_cmd_en ;
|
2119 |
|
|
assign mig_p4_cmd_ra = p4_cmd_ra ;
|
2120 |
|
|
assign mig_p4_cmd_ba = p4_cmd_ba ;
|
2121 |
|
|
assign mig_p4_cmd_ca = p4_cmd_ca ;
|
2122 |
|
|
assign mig_p4_cmd_instr = p4_cmd_instr;
|
2123 |
|
|
assign mig_p4_cmd_bl = {(p4_cmd_instr[2] | p4_cmd_bl[5]),p4_cmd_bl[4:0]} ;
|
2124 |
|
|
assign p4_cmd_empty = mig_p4_cmd_empty;
|
2125 |
|
|
assign p4_cmd_full = mig_p4_cmd_full ;
|
2126 |
|
|
|
2127 |
|
|
end else
|
2128 |
|
|
begin
|
2129 |
|
|
assign mig_p4_arb_en = 'b0;
|
2130 |
|
|
assign mig_p4_cmd_clk = 'b0;
|
2131 |
|
|
assign mig_p4_cmd_en = 'b0;
|
2132 |
|
|
assign mig_p4_cmd_ra = 'b0;
|
2133 |
|
|
assign mig_p4_cmd_ba = 'b0;
|
2134 |
|
|
assign mig_p4_cmd_ca = 'b0;
|
2135 |
|
|
assign mig_p4_cmd_instr = 'b0;
|
2136 |
|
|
assign mig_p4_cmd_bl = 'b0;
|
2137 |
|
|
assign p4_cmd_empty = 'b0;
|
2138 |
|
|
assign p4_cmd_full = 'b0;
|
2139 |
|
|
|
2140 |
|
|
|
2141 |
|
|
|
2142 |
|
|
end
|
2143 |
|
|
|
2144 |
|
|
if (C_PORT_ENABLE[5] == 1'b1)
|
2145 |
|
|
begin
|
2146 |
|
|
|
2147 |
|
|
assign mig_p5_arb_en = p5_arb_en ;
|
2148 |
|
|
assign mig_p5_cmd_clk = p5_cmd_clk ;
|
2149 |
|
|
assign mig_p5_cmd_en = p5_cmd_en ;
|
2150 |
|
|
assign mig_p5_cmd_ra = p5_cmd_ra ;
|
2151 |
|
|
assign mig_p5_cmd_ba = p5_cmd_ba ;
|
2152 |
|
|
assign mig_p5_cmd_ca = p5_cmd_ca ;
|
2153 |
|
|
assign mig_p5_cmd_instr = p5_cmd_instr;
|
2154 |
|
|
assign mig_p5_cmd_bl = {(p5_cmd_instr[2] | p5_cmd_bl[5]),p5_cmd_bl[4:0]} ;
|
2155 |
|
|
assign p5_cmd_empty = mig_p5_cmd_empty;
|
2156 |
|
|
assign p5_cmd_full = mig_p5_cmd_full ;
|
2157 |
|
|
|
2158 |
|
|
end else
|
2159 |
|
|
begin
|
2160 |
|
|
assign mig_p5_arb_en = 'b0;
|
2161 |
|
|
assign mig_p5_cmd_clk = 'b0;
|
2162 |
|
|
assign mig_p5_cmd_en = 'b0;
|
2163 |
|
|
assign mig_p5_cmd_ra = 'b0;
|
2164 |
|
|
assign mig_p5_cmd_ba = 'b0;
|
2165 |
|
|
assign mig_p5_cmd_ca = 'b0;
|
2166 |
|
|
assign mig_p5_cmd_instr = 'b0;
|
2167 |
|
|
assign mig_p5_cmd_bl = 'b0;
|
2168 |
|
|
assign p5_cmd_empty = 'b0;
|
2169 |
|
|
assign p5_cmd_full = 'b0;
|
2170 |
|
|
|
2171 |
|
|
|
2172 |
|
|
end
|
2173 |
|
|
|
2174 |
|
|
|
2175 |
|
|
|
2176 |
|
|
|
2177 |
|
|
// Inputs from Application User Port
|
2178 |
|
|
|
2179 |
|
|
// Port 0
|
2180 |
|
|
if (C_PORT_ENABLE[0] == 1'b1)
|
2181 |
|
|
begin
|
2182 |
|
|
assign mig_p0_wr_clk = p0_wr_clk;
|
2183 |
|
|
assign mig_p0_rd_clk = p0_rd_clk;
|
2184 |
|
|
assign mig_p0_wr_en = p0_wr_en;
|
2185 |
|
|
assign mig_p0_rd_en = p0_rd_en;
|
2186 |
|
|
assign mig_p0_wr_mask = p0_wr_mask[3:0];
|
2187 |
|
|
assign mig_p0_wr_data = p0_wr_data[31:0];
|
2188 |
|
|
assign p0_rd_data = mig_p0_rd_data;
|
2189 |
|
|
assign p0_rd_full = mig_p0_rd_full;
|
2190 |
|
|
assign p0_rd_empty = mig_p0_rd_empty;
|
2191 |
|
|
assign p0_rd_error = mig_p0_rd_error;
|
2192 |
|
|
assign p0_wr_error = mig_p0_wr_error;
|
2193 |
|
|
assign p0_rd_overflow = mig_p0_rd_overflow;
|
2194 |
|
|
assign p0_wr_underrun = mig_p0_wr_underrun;
|
2195 |
|
|
assign p0_wr_empty = mig_p0_wr_empty;
|
2196 |
|
|
assign p0_wr_full = mig_p0_wr_full;
|
2197 |
|
|
assign p0_wr_count = mig_p0_wr_count;
|
2198 |
|
|
assign p0_rd_count = mig_p0_rd_count ;
|
2199 |
|
|
|
2200 |
|
|
|
2201 |
|
|
end
|
2202 |
|
|
else
|
2203 |
|
|
begin
|
2204 |
|
|
assign mig_p0_wr_clk = 'b0;
|
2205 |
|
|
assign mig_p0_rd_clk = 'b0;
|
2206 |
|
|
assign mig_p0_wr_en = 'b0;
|
2207 |
|
|
assign mig_p0_rd_en = 'b0;
|
2208 |
|
|
assign mig_p0_wr_mask = 'b0;
|
2209 |
|
|
assign mig_p0_wr_data = 'b0;
|
2210 |
|
|
assign p0_rd_data = 'b0;
|
2211 |
|
|
assign p0_rd_full = 'b0;
|
2212 |
|
|
assign p0_rd_empty = 'b0;
|
2213 |
|
|
assign p0_rd_error = 'b0;
|
2214 |
|
|
assign p0_wr_error = 'b0;
|
2215 |
|
|
assign p0_rd_overflow = 'b0;
|
2216 |
|
|
assign p0_wr_underrun = 'b0;
|
2217 |
|
|
assign p0_wr_empty = 'b0;
|
2218 |
|
|
assign p0_wr_full = 'b0;
|
2219 |
|
|
assign p0_wr_count = 'b0;
|
2220 |
|
|
assign p0_rd_count = 'b0;
|
2221 |
|
|
|
2222 |
|
|
|
2223 |
|
|
end
|
2224 |
|
|
|
2225 |
|
|
|
2226 |
|
|
// Port 1
|
2227 |
|
|
if (C_PORT_ENABLE[1] == 1'b1)
|
2228 |
|
|
begin
|
2229 |
|
|
|
2230 |
|
|
assign mig_p1_wr_clk = p1_wr_clk;
|
2231 |
|
|
assign mig_p1_rd_clk = p1_rd_clk;
|
2232 |
|
|
assign mig_p1_wr_en = p1_wr_en;
|
2233 |
|
|
assign mig_p1_wr_mask = p1_wr_mask[3:0];
|
2234 |
|
|
assign mig_p1_wr_data = p1_wr_data[31:0];
|
2235 |
|
|
assign mig_p1_rd_en = p1_rd_en;
|
2236 |
|
|
assign p1_rd_data = mig_p1_rd_data;
|
2237 |
|
|
assign p1_rd_empty = mig_p1_rd_empty;
|
2238 |
|
|
assign p1_rd_full = mig_p1_rd_full;
|
2239 |
|
|
assign p1_rd_error = mig_p1_rd_error;
|
2240 |
|
|
assign p1_wr_error = mig_p1_wr_error;
|
2241 |
|
|
assign p1_rd_overflow = mig_p1_rd_overflow;
|
2242 |
|
|
assign p1_wr_underrun = mig_p1_wr_underrun;
|
2243 |
|
|
assign p1_wr_empty = mig_p1_wr_empty;
|
2244 |
|
|
assign p1_wr_full = mig_p1_wr_full;
|
2245 |
|
|
assign p1_wr_count = mig_p1_wr_count;
|
2246 |
|
|
assign p1_rd_count = mig_p1_rd_count ;
|
2247 |
|
|
|
2248 |
|
|
end else
|
2249 |
|
|
begin
|
2250 |
|
|
|
2251 |
|
|
assign mig_p1_wr_clk = 'b0;
|
2252 |
|
|
assign mig_p1_rd_clk = 'b0;
|
2253 |
|
|
assign mig_p1_wr_en = 'b0;
|
2254 |
|
|
assign mig_p1_wr_mask = 'b0;
|
2255 |
|
|
assign mig_p1_wr_data = 'b0;
|
2256 |
|
|
assign mig_p1_rd_en = 'b0;
|
2257 |
|
|
assign p1_rd_data = 'b0;
|
2258 |
|
|
assign p1_rd_empty = 'b0;
|
2259 |
|
|
assign p1_rd_full = 'b0;
|
2260 |
|
|
assign p1_rd_error = 'b0;
|
2261 |
|
|
assign p1_wr_error = 'b0;
|
2262 |
|
|
assign p1_rd_overflow = 'b0;
|
2263 |
|
|
assign p1_wr_underrun = 'b0;
|
2264 |
|
|
assign p1_wr_empty = 'b0;
|
2265 |
|
|
assign p1_wr_full = 'b0;
|
2266 |
|
|
assign p1_wr_count = 'b0;
|
2267 |
|
|
assign p1_rd_count = 'b0;
|
2268 |
|
|
|
2269 |
|
|
|
2270 |
|
|
end
|
2271 |
|
|
|
2272 |
|
|
|
2273 |
|
|
|
2274 |
|
|
|
2275 |
|
|
|
2276 |
|
|
// whenever PORT 2 is in Write mode
|
2277 |
|
|
if(C_PORT_CONFIG[183:160] == "B32" && C_PORT_CONFIG[119:96] == "W32") begin : u_config1_2W
|
2278 |
|
|
if (C_PORT_ENABLE[2] == 1'b1)
|
2279 |
|
|
begin
|
2280 |
|
|
assign mig_p2_clk = p2_wr_clk;
|
2281 |
|
|
assign mig_p2_wr_data = p2_wr_data[31:0];
|
2282 |
|
|
assign mig_p2_wr_mask = p2_wr_mask[3:0];
|
2283 |
|
|
assign mig_p2_en = p2_wr_en; // this signal will not shown up if the port 5 is for read dir
|
2284 |
|
|
assign p2_wr_error = mig_p2_error;
|
2285 |
|
|
assign p2_wr_full = mig_p2_full;
|
2286 |
|
|
assign p2_wr_empty = mig_p2_empty;
|
2287 |
|
|
assign p2_wr_underrun = mig_p2_underrun;
|
2288 |
|
|
assign p2_wr_count = mig_p2_count ; // wr port
|
2289 |
|
|
|
2290 |
|
|
|
2291 |
|
|
end else
|
2292 |
|
|
begin
|
2293 |
|
|
assign mig_p2_clk = 'b0;
|
2294 |
|
|
assign mig_p2_wr_data = 'b0;
|
2295 |
|
|
assign mig_p2_wr_mask = 'b0;
|
2296 |
|
|
assign mig_p2_en = 'b0;
|
2297 |
|
|
assign p2_wr_error = 'b0;
|
2298 |
|
|
assign p2_wr_full = 'b0;
|
2299 |
|
|
assign p2_wr_empty = 'b0;
|
2300 |
|
|
assign p2_wr_underrun = 'b0;
|
2301 |
|
|
assign p2_wr_count = 'b0;
|
2302 |
|
|
|
2303 |
|
|
end
|
2304 |
|
|
assign p2_rd_data = 'b0;
|
2305 |
|
|
assign p2_rd_overflow = 'b0;
|
2306 |
|
|
assign p2_rd_error = 'b0;
|
2307 |
|
|
assign p2_rd_full = 'b0;
|
2308 |
|
|
assign p2_rd_empty = 'b0;
|
2309 |
|
|
assign p2_rd_count = 'b0;
|
2310 |
|
|
// assign p2_rd_error = 'b0;
|
2311 |
|
|
|
2312 |
|
|
|
2313 |
|
|
|
2314 |
|
|
end else if(C_PORT_CONFIG[183:160] == "B32" && C_PORT_CONFIG[119:96] == "R32") begin : u_config1_2R
|
2315 |
|
|
|
2316 |
|
|
if (C_PORT_ENABLE[2] == 1'b1)
|
2317 |
|
|
begin
|
2318 |
|
|
assign mig_p2_clk = p2_rd_clk;
|
2319 |
|
|
assign p2_rd_data = mig_p2_rd_data;
|
2320 |
|
|
assign mig_p2_en = p2_rd_en;
|
2321 |
|
|
assign p2_rd_overflow = mig_p2_overflow;
|
2322 |
|
|
assign p2_rd_error = mig_p2_error;
|
2323 |
|
|
assign p2_rd_full = mig_p2_full;
|
2324 |
|
|
assign p2_rd_empty = mig_p2_empty;
|
2325 |
|
|
assign p2_rd_count = mig_p2_count ; // wr port
|
2326 |
|
|
|
2327 |
|
|
end else
|
2328 |
|
|
begin
|
2329 |
|
|
assign mig_p2_clk = 'b0;
|
2330 |
|
|
assign p2_rd_data = 'b0;
|
2331 |
|
|
assign mig_p2_en = 'b0;
|
2332 |
|
|
|
2333 |
|
|
assign p2_rd_overflow = 'b0;
|
2334 |
|
|
assign p2_rd_error = 'b0;
|
2335 |
|
|
assign p2_rd_full = 'b0;
|
2336 |
|
|
assign p2_rd_empty = 'b0;
|
2337 |
|
|
assign p2_rd_count = 'b0;
|
2338 |
|
|
|
2339 |
|
|
end
|
2340 |
|
|
assign mig_p2_wr_data = 'b0;
|
2341 |
|
|
assign mig_p2_wr_mask = 'b0;
|
2342 |
|
|
assign p2_wr_error = 'b0;
|
2343 |
|
|
assign p2_wr_full = 'b0;
|
2344 |
|
|
assign p2_wr_empty = 'b0;
|
2345 |
|
|
assign p2_wr_underrun = 'b0;
|
2346 |
|
|
assign p2_wr_count = 'b0;
|
2347 |
|
|
|
2348 |
|
|
end
|
2349 |
|
|
if(C_PORT_CONFIG[183:160] == "B32" && C_PORT_CONFIG[87:64] == "W32") begin : u_config1_3W
|
2350 |
|
|
// whenever PORT 3 is in Write mode
|
2351 |
|
|
|
2352 |
|
|
if (C_PORT_ENABLE[3] == 1'b1)
|
2353 |
|
|
begin
|
2354 |
|
|
|
2355 |
|
|
assign mig_p3_clk = p3_wr_clk;
|
2356 |
|
|
assign mig_p3_wr_data = p3_wr_data[31:0];
|
2357 |
|
|
assign mig_p3_wr_mask = p3_wr_mask[3:0];
|
2358 |
|
|
assign mig_p3_en = p3_wr_en;
|
2359 |
|
|
assign p3_wr_full = mig_p3_full;
|
2360 |
|
|
assign p3_wr_empty = mig_p3_empty;
|
2361 |
|
|
assign p3_wr_underrun = mig_p3_underrun;
|
2362 |
|
|
assign p3_wr_count = mig_p3_count ; // wr port
|
2363 |
|
|
assign p3_wr_error = mig_p3_error;
|
2364 |
|
|
|
2365 |
|
|
end else
|
2366 |
|
|
begin
|
2367 |
|
|
assign mig_p3_clk = 'b0;
|
2368 |
|
|
assign mig_p3_wr_data = 'b0;
|
2369 |
|
|
assign mig_p3_wr_mask = 'b0;
|
2370 |
|
|
assign mig_p3_en = 'b0;
|
2371 |
|
|
assign p3_wr_full = 'b0;
|
2372 |
|
|
assign p3_wr_empty = 'b0;
|
2373 |
|
|
assign p3_wr_underrun = 'b0;
|
2374 |
|
|
assign p3_wr_count = 'b0;
|
2375 |
|
|
assign p3_wr_error = 'b0;
|
2376 |
|
|
|
2377 |
|
|
end
|
2378 |
|
|
assign p3_rd_overflow = 'b0;
|
2379 |
|
|
assign p3_rd_error = 'b0;
|
2380 |
|
|
assign p3_rd_full = 'b0;
|
2381 |
|
|
assign p3_rd_empty = 'b0;
|
2382 |
|
|
assign p3_rd_count = 'b0;
|
2383 |
|
|
assign p3_rd_data = 'b0;
|
2384 |
|
|
|
2385 |
|
|
|
2386 |
|
|
end else if(C_PORT_CONFIG[183:160] == "B32" && C_PORT_CONFIG[87:64] == "R32") begin : u_config1_3R
|
2387 |
|
|
|
2388 |
|
|
if (C_PORT_ENABLE[3] == 1'b1)
|
2389 |
|
|
begin
|
2390 |
|
|
|
2391 |
|
|
assign mig_p3_clk = p3_rd_clk;
|
2392 |
|
|
assign p3_rd_data = mig_p3_rd_data;
|
2393 |
|
|
assign mig_p3_en = p3_rd_en; // this signal will not shown up if the port 5 is for write dir
|
2394 |
|
|
assign p3_rd_overflow = mig_p3_overflow;
|
2395 |
|
|
assign p3_rd_error = mig_p3_error;
|
2396 |
|
|
assign p3_rd_full = mig_p3_full;
|
2397 |
|
|
assign p3_rd_empty = mig_p3_empty;
|
2398 |
|
|
assign p3_rd_count = mig_p3_count ; // wr port
|
2399 |
|
|
end else
|
2400 |
|
|
begin
|
2401 |
|
|
assign mig_p3_clk = 'b0;
|
2402 |
|
|
assign mig_p3_en = 'b0;
|
2403 |
|
|
assign p3_rd_overflow = 'b0;
|
2404 |
|
|
assign p3_rd_full = 'b0;
|
2405 |
|
|
assign p3_rd_empty = 'b0;
|
2406 |
|
|
assign p3_rd_count = 'b0;
|
2407 |
|
|
assign p3_rd_error = 'b0;
|
2408 |
|
|
assign p3_rd_data = 'b0;
|
2409 |
|
|
end
|
2410 |
|
|
assign p3_wr_full = 'b0;
|
2411 |
|
|
assign p3_wr_empty = 'b0;
|
2412 |
|
|
assign p3_wr_underrun = 'b0;
|
2413 |
|
|
assign p3_wr_count = 'b0;
|
2414 |
|
|
assign p3_wr_error = 'b0;
|
2415 |
|
|
assign mig_p3_wr_data = 'b0;
|
2416 |
|
|
assign mig_p3_wr_mask = 'b0;
|
2417 |
|
|
end
|
2418 |
|
|
if(C_PORT_CONFIG[183:160] == "B32" && C_PORT_CONFIG[55:32] == "W32") begin : u_config1_4W
|
2419 |
|
|
// whenever PORT 4 is in Write mode
|
2420 |
|
|
|
2421 |
|
|
if (C_PORT_ENABLE[4] == 1'b1)
|
2422 |
|
|
begin
|
2423 |
|
|
|
2424 |
|
|
assign mig_p4_clk = p4_wr_clk;
|
2425 |
|
|
assign mig_p4_wr_data = p4_wr_data[31:0];
|
2426 |
|
|
assign mig_p4_wr_mask = p4_wr_mask[3:0];
|
2427 |
|
|
assign mig_p4_en = p4_wr_en; // this signal will not shown up if the port 5 is for read dir
|
2428 |
|
|
assign p4_wr_full = mig_p4_full;
|
2429 |
|
|
assign p4_wr_empty = mig_p4_empty;
|
2430 |
|
|
assign p4_wr_underrun = mig_p4_underrun;
|
2431 |
|
|
assign p4_wr_count = mig_p4_count ; // wr port
|
2432 |
|
|
assign p4_wr_error = mig_p4_error;
|
2433 |
|
|
|
2434 |
|
|
end else
|
2435 |
|
|
begin
|
2436 |
|
|
assign mig_p4_clk = 'b0;
|
2437 |
|
|
assign mig_p4_wr_data = 'b0;
|
2438 |
|
|
assign mig_p4_wr_mask = 'b0;
|
2439 |
|
|
assign mig_p4_en = 'b0;
|
2440 |
|
|
assign p4_wr_full = 'b0;
|
2441 |
|
|
assign p4_wr_empty = 'b0;
|
2442 |
|
|
assign p4_wr_underrun = 'b0;
|
2443 |
|
|
assign p4_wr_count = 'b0;
|
2444 |
|
|
assign p4_wr_error = 'b0;
|
2445 |
|
|
end
|
2446 |
|
|
assign p4_rd_overflow = 'b0;
|
2447 |
|
|
assign p4_rd_error = 'b0;
|
2448 |
|
|
assign p4_rd_full = 'b0;
|
2449 |
|
|
assign p4_rd_empty = 'b0;
|
2450 |
|
|
assign p4_rd_count = 'b0;
|
2451 |
|
|
assign p4_rd_data = 'b0;
|
2452 |
|
|
|
2453 |
|
|
end else if(C_PORT_CONFIG[183:160] == "B32" && C_PORT_CONFIG[55:32] == "R32") begin : u_config1_4R
|
2454 |
|
|
|
2455 |
|
|
if (C_PORT_ENABLE[4] == 1'b1)
|
2456 |
|
|
begin
|
2457 |
|
|
assign mig_p4_clk = p4_rd_clk;
|
2458 |
|
|
assign p4_rd_data = mig_p4_rd_data;
|
2459 |
|
|
assign mig_p4_en = p4_rd_en; // this signal will not shown up if the port 5 is for write dir
|
2460 |
|
|
assign p4_rd_overflow = mig_p4_overflow;
|
2461 |
|
|
assign p4_rd_error = mig_p4_error;
|
2462 |
|
|
assign p4_rd_full = mig_p4_full;
|
2463 |
|
|
assign p4_rd_empty = mig_p4_empty;
|
2464 |
|
|
assign p4_rd_count = mig_p4_count ; // wr port
|
2465 |
|
|
|
2466 |
|
|
end else
|
2467 |
|
|
begin
|
2468 |
|
|
assign mig_p4_clk = 'b0;
|
2469 |
|
|
assign p4_rd_data = 'b0;
|
2470 |
|
|
assign mig_p4_en = 'b0;
|
2471 |
|
|
assign p4_rd_overflow = 'b0;
|
2472 |
|
|
assign p4_rd_error = 'b0;
|
2473 |
|
|
assign p4_rd_full = 'b0;
|
2474 |
|
|
assign p4_rd_empty = 'b0;
|
2475 |
|
|
assign p4_rd_count = 'b0;
|
2476 |
|
|
end
|
2477 |
|
|
assign p4_wr_full = 'b0;
|
2478 |
|
|
assign p4_wr_empty = 'b0;
|
2479 |
|
|
assign p4_wr_underrun = 'b0;
|
2480 |
|
|
assign p4_wr_count = 'b0;
|
2481 |
|
|
assign p4_wr_error = 'b0;
|
2482 |
|
|
assign mig_p4_wr_data = 'b0;
|
2483 |
|
|
assign mig_p4_wr_mask = 'b0;
|
2484 |
|
|
|
2485 |
|
|
|
2486 |
|
|
|
2487 |
|
|
|
2488 |
|
|
end
|
2489 |
|
|
|
2490 |
|
|
if(C_PORT_CONFIG[183:160] == "B32" && C_PORT_CONFIG[23:0] == "W32") begin : u_config1_5W
|
2491 |
|
|
// whenever PORT 5 is in Write mode
|
2492 |
|
|
|
2493 |
|
|
|
2494 |
|
|
if (C_PORT_ENABLE[5] == 1'b1)
|
2495 |
|
|
begin
|
2496 |
|
|
assign mig_p5_clk = p5_wr_clk;
|
2497 |
|
|
assign mig_p5_wr_data = p5_wr_data[31:0];
|
2498 |
|
|
assign mig_p5_wr_mask = p5_wr_mask[3:0];
|
2499 |
|
|
assign mig_p5_en = p5_wr_en;
|
2500 |
|
|
assign p5_wr_full = mig_p5_full;
|
2501 |
|
|
assign p5_wr_empty = mig_p5_empty;
|
2502 |
|
|
assign p5_wr_underrun = mig_p5_underrun;
|
2503 |
|
|
assign p5_wr_count = mig_p5_count ;
|
2504 |
|
|
assign p5_wr_error = mig_p5_error;
|
2505 |
|
|
|
2506 |
|
|
end else
|
2507 |
|
|
begin
|
2508 |
|
|
assign mig_p5_clk = 'b0;
|
2509 |
|
|
assign mig_p5_wr_data = 'b0;
|
2510 |
|
|
assign mig_p5_wr_mask = 'b0;
|
2511 |
|
|
assign mig_p5_en = 'b0;
|
2512 |
|
|
assign p5_wr_full = 'b0;
|
2513 |
|
|
assign p5_wr_empty = 'b0;
|
2514 |
|
|
assign p5_wr_underrun = 'b0;
|
2515 |
|
|
assign p5_wr_count = 'b0;
|
2516 |
|
|
assign p5_wr_error = 'b0;
|
2517 |
|
|
end
|
2518 |
|
|
assign p5_rd_data = 'b0;
|
2519 |
|
|
assign p5_rd_overflow = 'b0;
|
2520 |
|
|
assign p5_rd_error = 'b0;
|
2521 |
|
|
assign p5_rd_full = 'b0;
|
2522 |
|
|
assign p5_rd_empty = 'b0;
|
2523 |
|
|
assign p5_rd_count = 'b0;
|
2524 |
|
|
|
2525 |
|
|
|
2526 |
|
|
|
2527 |
|
|
|
2528 |
|
|
end else if(C_PORT_CONFIG[183:160] == "B32" && C_PORT_CONFIG[23:0] == "R32") begin : u_config1_5R
|
2529 |
|
|
|
2530 |
|
|
if (C_PORT_ENABLE[5] == 1'b1)
|
2531 |
|
|
begin
|
2532 |
|
|
|
2533 |
|
|
assign mig_p5_clk = p5_rd_clk;
|
2534 |
|
|
assign p5_rd_data = mig_p5_rd_data;
|
2535 |
|
|
assign mig_p5_en = p5_rd_en;
|
2536 |
|
|
assign p5_rd_overflow = mig_p5_overflow;
|
2537 |
|
|
assign p5_rd_error = mig_p5_error;
|
2538 |
|
|
assign p5_rd_full = mig_p5_full;
|
2539 |
|
|
assign p5_rd_empty = mig_p5_empty;
|
2540 |
|
|
assign p5_rd_count = mig_p5_count ;
|
2541 |
|
|
|
2542 |
|
|
end else
|
2543 |
|
|
begin
|
2544 |
|
|
assign mig_p5_clk = 'b0;
|
2545 |
|
|
assign p5_rd_data = 'b0;
|
2546 |
|
|
assign mig_p5_en = 'b0;
|
2547 |
|
|
assign p5_rd_overflow = 'b0;
|
2548 |
|
|
assign p5_rd_error = 'b0;
|
2549 |
|
|
assign p5_rd_full = 'b0;
|
2550 |
|
|
assign p5_rd_empty = 'b0;
|
2551 |
|
|
assign p5_rd_count = 'b0;
|
2552 |
|
|
|
2553 |
|
|
end
|
2554 |
|
|
assign p5_wr_full = 'b0;
|
2555 |
|
|
assign p5_wr_empty = 'b0;
|
2556 |
|
|
assign p5_wr_underrun = 'b0;
|
2557 |
|
|
assign p5_wr_count = 'b0;
|
2558 |
|
|
assign p5_wr_error = 'b0;
|
2559 |
|
|
assign mig_p5_wr_data = 'b0;
|
2560 |
|
|
assign mig_p5_wr_mask = 'b0;
|
2561 |
|
|
|
2562 |
|
|
end
|
2563 |
|
|
|
2564 |
|
|
end else if(C_PORT_CONFIG == "B32_B32_B32_B32" ) begin : u_config_2
|
2565 |
|
|
|
2566 |
|
|
|
2567 |
|
|
// Inputs from Application CMD Port
|
2568 |
|
|
// ************* need to hook up rd /wr error outputs
|
2569 |
|
|
|
2570 |
|
|
if (C_PORT_ENABLE[0] == 1'b1)
|
2571 |
|
|
begin
|
2572 |
|
|
// command port signals
|
2573 |
|
|
assign mig_p0_arb_en = p0_arb_en ;
|
2574 |
|
|
assign mig_p0_cmd_clk = p0_cmd_clk ;
|
2575 |
|
|
assign mig_p0_cmd_en = p0_cmd_en ;
|
2576 |
|
|
assign mig_p0_cmd_ra = p0_cmd_ra ;
|
2577 |
|
|
assign mig_p0_cmd_ba = p0_cmd_ba ;
|
2578 |
|
|
assign mig_p0_cmd_ca = p0_cmd_ca ;
|
2579 |
|
|
assign mig_p0_cmd_instr = p0_cmd_instr;
|
2580 |
|
|
assign mig_p0_cmd_bl = {(p0_cmd_instr[2] | p0_cmd_bl[5]),p0_cmd_bl[4:0]} ;
|
2581 |
|
|
|
2582 |
|
|
// Data port signals
|
2583 |
|
|
assign mig_p0_rd_en = p0_rd_en;
|
2584 |
|
|
assign mig_p0_wr_clk = p0_wr_clk;
|
2585 |
|
|
assign mig_p0_rd_clk = p0_rd_clk;
|
2586 |
|
|
assign mig_p0_wr_en = p0_wr_en;
|
2587 |
|
|
assign mig_p0_wr_data = p0_wr_data[31:0];
|
2588 |
|
|
assign mig_p0_wr_mask = p0_wr_mask[3:0];
|
2589 |
|
|
assign p0_wr_count = mig_p0_wr_count;
|
2590 |
|
|
assign p0_rd_count = mig_p0_rd_count ;
|
2591 |
|
|
|
2592 |
|
|
|
2593 |
|
|
|
2594 |
|
|
end else
|
2595 |
|
|
begin
|
2596 |
|
|
assign mig_p0_arb_en = 'b0;
|
2597 |
|
|
assign mig_p0_cmd_clk = 'b0;
|
2598 |
|
|
assign mig_p0_cmd_en = 'b0;
|
2599 |
|
|
assign mig_p0_cmd_ra = 'b0;
|
2600 |
|
|
assign mig_p0_cmd_ba = 'b0;
|
2601 |
|
|
assign mig_p0_cmd_ca = 'b0;
|
2602 |
|
|
assign mig_p0_cmd_instr = 'b0;
|
2603 |
|
|
assign mig_p0_cmd_bl = 'b0;
|
2604 |
|
|
|
2605 |
|
|
assign mig_p0_rd_en = 'b0;
|
2606 |
|
|
assign mig_p0_wr_clk = 'b0;
|
2607 |
|
|
assign mig_p0_rd_clk = 'b0;
|
2608 |
|
|
assign mig_p0_wr_en = 'b0;
|
2609 |
|
|
assign mig_p0_wr_data = 'b0;
|
2610 |
|
|
assign mig_p0_wr_mask = 'b0;
|
2611 |
|
|
assign p0_wr_count = 'b0;
|
2612 |
|
|
assign p0_rd_count = 'b0;
|
2613 |
|
|
|
2614 |
|
|
|
2615 |
|
|
end
|
2616 |
|
|
|
2617 |
|
|
assign p0_cmd_empty = mig_p0_cmd_empty ;
|
2618 |
|
|
assign p0_cmd_full = mig_p0_cmd_full ;
|
2619 |
|
|
|
2620 |
|
|
|
2621 |
|
|
if (C_PORT_ENABLE[1] == 1'b1)
|
2622 |
|
|
begin
|
2623 |
|
|
// command port signals
|
2624 |
|
|
|
2625 |
|
|
assign mig_p1_arb_en = p1_arb_en ;
|
2626 |
|
|
assign mig_p1_cmd_clk = p1_cmd_clk ;
|
2627 |
|
|
assign mig_p1_cmd_en = p1_cmd_en ;
|
2628 |
|
|
assign mig_p1_cmd_ra = p1_cmd_ra ;
|
2629 |
|
|
assign mig_p1_cmd_ba = p1_cmd_ba ;
|
2630 |
|
|
assign mig_p1_cmd_ca = p1_cmd_ca ;
|
2631 |
|
|
assign mig_p1_cmd_instr = p1_cmd_instr;
|
2632 |
|
|
assign mig_p1_cmd_bl = {(p1_cmd_instr[2] | p1_cmd_bl[5]),p1_cmd_bl[4:0]} ;
|
2633 |
|
|
// Data port signals
|
2634 |
|
|
|
2635 |
|
|
assign mig_p1_wr_en = p1_wr_en;
|
2636 |
|
|
assign mig_p1_wr_clk = p1_wr_clk;
|
2637 |
|
|
assign mig_p1_rd_en = p1_rd_en;
|
2638 |
|
|
assign mig_p1_wr_data = p1_wr_data[31:0];
|
2639 |
|
|
assign mig_p1_wr_mask = p1_wr_mask[3:0];
|
2640 |
|
|
assign mig_p1_rd_clk = p1_rd_clk;
|
2641 |
|
|
assign p1_wr_count = mig_p1_wr_count;
|
2642 |
|
|
assign p1_rd_count = mig_p1_rd_count;
|
2643 |
|
|
|
2644 |
|
|
end else
|
2645 |
|
|
begin
|
2646 |
|
|
|
2647 |
|
|
assign mig_p1_arb_en = 'b0;
|
2648 |
|
|
assign mig_p1_cmd_clk = 'b0;
|
2649 |
|
|
assign mig_p1_cmd_en = 'b0;
|
2650 |
|
|
assign mig_p1_cmd_ra = 'b0;
|
2651 |
|
|
assign mig_p1_cmd_ba = 'b0;
|
2652 |
|
|
assign mig_p1_cmd_ca = 'b0;
|
2653 |
|
|
assign mig_p1_cmd_instr = 'b0;
|
2654 |
|
|
assign mig_p1_cmd_bl = 'b0;
|
2655 |
|
|
// Data port signals
|
2656 |
|
|
assign mig_p1_wr_en = 'b0;
|
2657 |
|
|
assign mig_p1_wr_clk = 'b0;
|
2658 |
|
|
assign mig_p1_rd_en = 'b0;
|
2659 |
|
|
assign mig_p1_wr_data = 'b0;
|
2660 |
|
|
assign mig_p1_wr_mask = 'b0;
|
2661 |
|
|
assign mig_p1_rd_clk = 'b0;
|
2662 |
|
|
assign p1_wr_count = 'b0;
|
2663 |
|
|
assign p1_rd_count = 'b0;
|
2664 |
|
|
|
2665 |
|
|
end
|
2666 |
|
|
|
2667 |
|
|
|
2668 |
|
|
assign p1_cmd_empty = mig_p1_cmd_empty ;
|
2669 |
|
|
assign p1_cmd_full = mig_p1_cmd_full ;
|
2670 |
|
|
|
2671 |
|
|
if (C_PORT_ENABLE[2] == 1'b1)
|
2672 |
|
|
begin //MCB Physical port Logical Port
|
2673 |
|
|
assign mig_p2_arb_en = p2_arb_en ;
|
2674 |
|
|
assign mig_p2_cmd_clk = p2_cmd_clk ;
|
2675 |
|
|
assign mig_p2_cmd_en = p2_cmd_en ;
|
2676 |
|
|
assign mig_p2_cmd_ra = p2_cmd_ra ;
|
2677 |
|
|
assign mig_p2_cmd_ba = p2_cmd_ba ;
|
2678 |
|
|
assign mig_p2_cmd_ca = p2_cmd_ca ;
|
2679 |
|
|
assign mig_p2_cmd_instr = p2_cmd_instr;
|
2680 |
|
|
assign mig_p2_cmd_bl = {(p2_cmd_instr[2] | p2_cmd_bl[5]),p2_cmd_bl[4:0]} ;
|
2681 |
|
|
|
2682 |
|
|
assign mig_p2_en = p2_rd_en;
|
2683 |
|
|
assign mig_p2_clk = p2_rd_clk;
|
2684 |
|
|
assign mig_p3_en = p2_wr_en;
|
2685 |
|
|
assign mig_p3_clk = p2_wr_clk;
|
2686 |
|
|
assign mig_p3_wr_data = p2_wr_data[31:0];
|
2687 |
|
|
assign mig_p3_wr_mask = p2_wr_mask[3:0];
|
2688 |
|
|
assign p2_wr_count = mig_p3_count;
|
2689 |
|
|
assign p2_rd_count = mig_p2_count;
|
2690 |
|
|
|
2691 |
|
|
end else
|
2692 |
|
|
begin
|
2693 |
|
|
|
2694 |
|
|
assign mig_p2_arb_en = 'b0;
|
2695 |
|
|
assign mig_p2_cmd_clk = 'b0;
|
2696 |
|
|
assign mig_p2_cmd_en = 'b0;
|
2697 |
|
|
assign mig_p2_cmd_ra = 'b0;
|
2698 |
|
|
assign mig_p2_cmd_ba = 'b0;
|
2699 |
|
|
assign mig_p2_cmd_ca = 'b0;
|
2700 |
|
|
assign mig_p2_cmd_instr = 'b0;
|
2701 |
|
|
assign mig_p2_cmd_bl = 'b0;
|
2702 |
|
|
|
2703 |
|
|
assign mig_p2_en = 'b0;
|
2704 |
|
|
assign mig_p2_clk = 'b0;
|
2705 |
|
|
assign mig_p3_en = 'b0;
|
2706 |
|
|
assign mig_p3_clk = 'b0;
|
2707 |
|
|
assign mig_p3_wr_data = 'b0;
|
2708 |
|
|
assign mig_p3_wr_mask = 'b0;
|
2709 |
|
|
assign p2_rd_count = 'b0;
|
2710 |
|
|
assign p2_wr_count = 'b0;
|
2711 |
|
|
|
2712 |
|
|
end
|
2713 |
|
|
|
2714 |
|
|
assign p2_cmd_empty = mig_p2_cmd_empty ;
|
2715 |
|
|
assign p2_cmd_full = mig_p2_cmd_full ;
|
2716 |
|
|
|
2717 |
|
|
if (C_PORT_ENABLE[3] == 1'b1)
|
2718 |
|
|
begin //MCB Physical port Logical Port
|
2719 |
|
|
assign mig_p4_arb_en = p3_arb_en ;
|
2720 |
|
|
assign mig_p4_cmd_clk = p3_cmd_clk ;
|
2721 |
|
|
assign mig_p4_cmd_en = p3_cmd_en ;
|
2722 |
|
|
assign mig_p4_cmd_ra = p3_cmd_ra ;
|
2723 |
|
|
assign mig_p4_cmd_ba = p3_cmd_ba ;
|
2724 |
|
|
assign mig_p4_cmd_ca = p3_cmd_ca ;
|
2725 |
|
|
assign mig_p4_cmd_instr = p3_cmd_instr;
|
2726 |
|
|
assign mig_p4_cmd_bl = {(p3_cmd_instr[2] | p3_cmd_bl[5]),p3_cmd_bl[4:0]} ;
|
2727 |
|
|
|
2728 |
|
|
assign mig_p4_clk = p3_rd_clk;
|
2729 |
|
|
assign mig_p4_en = p3_rd_en;
|
2730 |
|
|
assign mig_p5_clk = p3_wr_clk;
|
2731 |
|
|
assign mig_p5_en = p3_wr_en;
|
2732 |
|
|
assign mig_p5_wr_data = p3_wr_data[31:0];
|
2733 |
|
|
assign mig_p5_wr_mask = p3_wr_mask[3:0];
|
2734 |
|
|
assign p3_rd_count = mig_p4_count;
|
2735 |
|
|
assign p3_wr_count = mig_p5_count;
|
2736 |
|
|
|
2737 |
|
|
|
2738 |
|
|
end else
|
2739 |
|
|
begin
|
2740 |
|
|
assign mig_p4_arb_en = 'b0;
|
2741 |
|
|
assign mig_p4_cmd_clk = 'b0;
|
2742 |
|
|
assign mig_p4_cmd_en = 'b0;
|
2743 |
|
|
assign mig_p4_cmd_ra = 'b0;
|
2744 |
|
|
assign mig_p4_cmd_ba = 'b0;
|
2745 |
|
|
assign mig_p4_cmd_ca = 'b0;
|
2746 |
|
|
assign mig_p4_cmd_instr = 'b0;
|
2747 |
|
|
assign mig_p4_cmd_bl = 'b0;
|
2748 |
|
|
|
2749 |
|
|
assign mig_p4_clk = 'b0;
|
2750 |
|
|
assign mig_p4_en = 'b0;
|
2751 |
|
|
assign mig_p5_clk = 'b0;
|
2752 |
|
|
assign mig_p5_en = 'b0;
|
2753 |
|
|
assign mig_p5_wr_data = 'b0;
|
2754 |
|
|
assign mig_p5_wr_mask = 'b0;
|
2755 |
|
|
assign p3_rd_count = 'b0;
|
2756 |
|
|
assign p3_wr_count = 'b0;
|
2757 |
|
|
|
2758 |
|
|
|
2759 |
|
|
|
2760 |
|
|
end
|
2761 |
|
|
|
2762 |
|
|
assign p3_cmd_empty = mig_p4_cmd_empty ;
|
2763 |
|
|
assign p3_cmd_full = mig_p4_cmd_full ;
|
2764 |
|
|
|
2765 |
|
|
|
2766 |
|
|
// outputs to Applications User Port
|
2767 |
|
|
assign p0_rd_data = mig_p0_rd_data;
|
2768 |
|
|
assign p1_rd_data = mig_p1_rd_data;
|
2769 |
|
|
assign p2_rd_data = mig_p2_rd_data;
|
2770 |
|
|
assign p3_rd_data = mig_p4_rd_data;
|
2771 |
|
|
|
2772 |
|
|
assign p0_rd_empty = mig_p0_rd_empty;
|
2773 |
|
|
assign p1_rd_empty = mig_p1_rd_empty;
|
2774 |
|
|
assign p2_rd_empty = mig_p2_empty;
|
2775 |
|
|
assign p3_rd_empty = mig_p4_empty;
|
2776 |
|
|
|
2777 |
|
|
assign p0_rd_full = mig_p0_rd_full;
|
2778 |
|
|
assign p1_rd_full = mig_p1_rd_full;
|
2779 |
|
|
assign p2_rd_full = mig_p2_full;
|
2780 |
|
|
assign p3_rd_full = mig_p4_full;
|
2781 |
|
|
|
2782 |
|
|
assign p0_rd_error = mig_p0_rd_error;
|
2783 |
|
|
assign p1_rd_error = mig_p1_rd_error;
|
2784 |
|
|
assign p2_rd_error = mig_p2_error;
|
2785 |
|
|
assign p3_rd_error = mig_p4_error;
|
2786 |
|
|
|
2787 |
|
|
assign p0_rd_overflow = mig_p0_rd_overflow;
|
2788 |
|
|
assign p1_rd_overflow = mig_p1_rd_overflow;
|
2789 |
|
|
assign p2_rd_overflow = mig_p2_overflow;
|
2790 |
|
|
assign p3_rd_overflow = mig_p4_overflow;
|
2791 |
|
|
|
2792 |
|
|
assign p0_wr_underrun = mig_p0_wr_underrun;
|
2793 |
|
|
assign p1_wr_underrun = mig_p1_wr_underrun;
|
2794 |
|
|
assign p2_wr_underrun = mig_p3_underrun;
|
2795 |
|
|
assign p3_wr_underrun = mig_p5_underrun;
|
2796 |
|
|
|
2797 |
|
|
assign p0_wr_empty = mig_p0_wr_empty;
|
2798 |
|
|
assign p1_wr_empty = mig_p1_wr_empty;
|
2799 |
|
|
assign p2_wr_empty = mig_p3_empty;
|
2800 |
|
|
assign p3_wr_empty = mig_p5_empty;
|
2801 |
|
|
|
2802 |
|
|
assign p0_wr_full = mig_p0_wr_full;
|
2803 |
|
|
assign p1_wr_full = mig_p1_wr_full;
|
2804 |
|
|
assign p2_wr_full = mig_p3_full;
|
2805 |
|
|
assign p3_wr_full = mig_p5_full;
|
2806 |
|
|
|
2807 |
|
|
assign p0_wr_error = mig_p0_wr_error;
|
2808 |
|
|
assign p1_wr_error = mig_p1_wr_error;
|
2809 |
|
|
assign p2_wr_error = mig_p3_error;
|
2810 |
|
|
assign p3_wr_error = mig_p5_error;
|
2811 |
|
|
|
2812 |
|
|
// unused ports signals
|
2813 |
|
|
assign p4_cmd_empty = 1'b0;
|
2814 |
|
|
assign p4_cmd_full = 1'b0;
|
2815 |
|
|
assign mig_p2_wr_mask = 'b0;
|
2816 |
|
|
assign mig_p4_wr_mask = 'b0;
|
2817 |
|
|
|
2818 |
|
|
assign mig_p2_wr_data = 'b0;
|
2819 |
|
|
assign mig_p4_wr_data = 'b0;
|
2820 |
|
|
|
2821 |
|
|
assign p5_cmd_empty = 1'b0;
|
2822 |
|
|
assign p5_cmd_full = 1'b0;
|
2823 |
|
|
|
2824 |
|
|
|
2825 |
|
|
assign mig_p3_cmd_clk = 1'b0;
|
2826 |
|
|
assign mig_p3_cmd_en = 1'b0;
|
2827 |
|
|
assign mig_p3_cmd_ra = 15'd0;
|
2828 |
|
|
assign mig_p3_cmd_ba = 3'd0;
|
2829 |
|
|
assign mig_p3_cmd_ca = 12'd0;
|
2830 |
|
|
assign mig_p3_cmd_instr = 3'd0;
|
2831 |
|
|
assign mig_p3_cmd_bl = 6'd0;
|
2832 |
|
|
assign mig_p3_arb_en = 1'b0; // physical cmd port 3 is not used in this config
|
2833 |
|
|
|
2834 |
|
|
|
2835 |
|
|
|
2836 |
|
|
|
2837 |
|
|
assign mig_p5_arb_en = 1'b0; // physical cmd port 3 is not used in this config
|
2838 |
|
|
assign mig_p5_cmd_clk = 1'b0;
|
2839 |
|
|
assign mig_p5_cmd_en = 1'b0;
|
2840 |
|
|
assign mig_p5_cmd_ra = 15'd0;
|
2841 |
|
|
assign mig_p5_cmd_ba = 3'd0;
|
2842 |
|
|
assign mig_p5_cmd_ca = 12'd0;
|
2843 |
|
|
assign mig_p5_cmd_instr = 3'd0;
|
2844 |
|
|
assign mig_p5_cmd_bl = 6'd0;
|
2845 |
|
|
|
2846 |
|
|
|
2847 |
|
|
|
2848 |
|
|
////////////////////////////////////////////////////////////////////////////
|
2849 |
|
|
/////////////////////////////////////////////////////////////////////////////
|
2850 |
|
|
////
|
2851 |
|
|
//// B64_B32_B32
|
2852 |
|
|
////
|
2853 |
|
|
/////////////////////////////////////////////////////////////////////////////
|
2854 |
|
|
////////////////////////////////////////////////////////////////////////////
|
2855 |
|
|
|
2856 |
|
|
|
2857 |
|
|
|
2858 |
|
|
end else if(C_PORT_CONFIG == "B64_B32_B32" ) begin : u_config_3
|
2859 |
|
|
|
2860 |
|
|
// Inputs from Application CMD Port
|
2861 |
|
|
|
2862 |
|
|
|
2863 |
|
|
if (C_PORT_ENABLE[0] == 1'b1)
|
2864 |
|
|
begin
|
2865 |
|
|
assign mig_p0_arb_en = p0_arb_en ;
|
2866 |
|
|
assign mig_p0_cmd_clk = p0_cmd_clk ;
|
2867 |
|
|
assign mig_p0_cmd_en = p0_cmd_en ;
|
2868 |
|
|
assign mig_p0_cmd_ra = p0_cmd_ra ;
|
2869 |
|
|
assign mig_p0_cmd_ba = p0_cmd_ba ;
|
2870 |
|
|
assign mig_p0_cmd_ca = p0_cmd_ca ;
|
2871 |
|
|
assign mig_p0_cmd_instr = p0_cmd_instr;
|
2872 |
|
|
assign mig_p0_cmd_bl = {(p0_cmd_instr[2] | p0_cmd_bl[5]),p0_cmd_bl[4:0]} ;
|
2873 |
|
|
assign p0_cmd_empty = mig_p0_cmd_empty ;
|
2874 |
|
|
assign p0_cmd_full = mig_p0_cmd_full ;
|
2875 |
|
|
|
2876 |
|
|
assign mig_p0_wr_clk = p0_wr_clk;
|
2877 |
|
|
assign mig_p0_rd_clk = p0_rd_clk;
|
2878 |
|
|
assign mig_p1_wr_clk = p0_wr_clk;
|
2879 |
|
|
assign mig_p1_rd_clk = p0_rd_clk;
|
2880 |
|
|
|
2881 |
|
|
assign mig_p0_wr_en = p0_wr_en & !p0_wr_full;
|
2882 |
|
|
assign mig_p1_wr_en = p0_wr_en & !p0_wr_full;
|
2883 |
|
|
assign mig_p0_wr_data = p0_wr_data[31:0];
|
2884 |
|
|
assign mig_p0_wr_mask = p0_wr_mask[3:0];
|
2885 |
|
|
assign mig_p1_wr_data = p0_wr_data[63 : 32];
|
2886 |
|
|
assign mig_p1_wr_mask = p0_wr_mask[7 : 4];
|
2887 |
|
|
|
2888 |
|
|
assign p0_rd_empty = mig_p1_rd_empty;
|
2889 |
|
|
assign p0_rd_data = {mig_p1_rd_data , mig_p0_rd_data};
|
2890 |
|
|
assign mig_p0_rd_en = p0_rd_en & !p0_rd_empty;
|
2891 |
|
|
assign mig_p1_rd_en = p0_rd_en & !p0_rd_empty;
|
2892 |
|
|
|
2893 |
|
|
|
2894 |
|
|
assign p0_wr_count = mig_p1_wr_count; // B64 for port 0, map most significant port to output
|
2895 |
|
|
assign p0_rd_count = mig_p1_rd_count;
|
2896 |
|
|
assign p0_wr_empty = mig_p1_wr_empty;
|
2897 |
|
|
assign p0_wr_error = mig_p1_wr_error | mig_p0_wr_error;
|
2898 |
|
|
assign p0_wr_full = mig_p1_wr_full;
|
2899 |
|
|
assign p0_wr_underrun = mig_p1_wr_underrun | mig_p0_wr_underrun;
|
2900 |
|
|
assign p0_rd_overflow = mig_p1_rd_overflow | mig_p0_rd_overflow;
|
2901 |
|
|
assign p0_rd_error = mig_p1_rd_error | mig_p0_rd_error;
|
2902 |
|
|
assign p0_rd_full = mig_p1_rd_full;
|
2903 |
|
|
|
2904 |
|
|
|
2905 |
|
|
end else
|
2906 |
|
|
begin
|
2907 |
|
|
|
2908 |
|
|
assign mig_p0_arb_en = 'b0;
|
2909 |
|
|
assign mig_p0_cmd_clk = 'b0;
|
2910 |
|
|
assign mig_p0_cmd_en = 'b0;
|
2911 |
|
|
assign mig_p0_cmd_ra = 'b0;
|
2912 |
|
|
assign mig_p0_cmd_ba = 'b0;
|
2913 |
|
|
assign mig_p0_cmd_ca = 'b0;
|
2914 |
|
|
assign mig_p0_cmd_instr = 'b0;
|
2915 |
|
|
assign mig_p0_cmd_bl = 'b0;
|
2916 |
|
|
assign p0_cmd_empty = 'b0;
|
2917 |
|
|
assign p0_cmd_full = 'b0;
|
2918 |
|
|
|
2919 |
|
|
|
2920 |
|
|
assign mig_p0_wr_clk = 'b0;
|
2921 |
|
|
assign mig_p0_rd_clk = 'b0;
|
2922 |
|
|
assign mig_p1_wr_clk = 'b0;
|
2923 |
|
|
assign mig_p1_rd_clk = 'b0;
|
2924 |
|
|
|
2925 |
|
|
assign mig_p0_wr_en = 'b0;
|
2926 |
|
|
assign mig_p1_wr_en = 'b0;
|
2927 |
|
|
assign mig_p0_wr_data = 'b0;
|
2928 |
|
|
assign mig_p0_wr_mask = 'b0;
|
2929 |
|
|
assign mig_p1_wr_data = 'b0;
|
2930 |
|
|
assign mig_p1_wr_mask = 'b0;
|
2931 |
|
|
|
2932 |
|
|
assign p0_rd_empty = 'b0;
|
2933 |
|
|
assign p0_rd_data = 'b0;
|
2934 |
|
|
assign mig_p0_rd_en = 'b0;
|
2935 |
|
|
assign mig_p1_rd_en = 'b0;
|
2936 |
|
|
|
2937 |
|
|
|
2938 |
|
|
assign p0_wr_count = 'b0;
|
2939 |
|
|
assign p0_rd_count = 'b0;
|
2940 |
|
|
assign p0_wr_empty = 'b0;
|
2941 |
|
|
assign p0_wr_error = 'b0;
|
2942 |
|
|
assign p0_wr_full = 'b0;
|
2943 |
|
|
assign p0_wr_underrun = 'b0;
|
2944 |
|
|
assign p0_rd_overflow = 'b0;
|
2945 |
|
|
assign p0_rd_error = 'b0;
|
2946 |
|
|
assign p0_rd_full = 'b0;
|
2947 |
|
|
|
2948 |
|
|
|
2949 |
|
|
end
|
2950 |
|
|
|
2951 |
|
|
|
2952 |
|
|
|
2953 |
|
|
if (C_PORT_ENABLE[1] == 1'b1)
|
2954 |
|
|
begin
|
2955 |
|
|
|
2956 |
|
|
assign mig_p2_arb_en = p1_arb_en ;
|
2957 |
|
|
assign mig_p2_cmd_clk = p1_cmd_clk ;
|
2958 |
|
|
assign mig_p2_cmd_en = p1_cmd_en ;
|
2959 |
|
|
assign mig_p2_cmd_ra = p1_cmd_ra ;
|
2960 |
|
|
assign mig_p2_cmd_ba = p1_cmd_ba ;
|
2961 |
|
|
assign mig_p2_cmd_ca = p1_cmd_ca ;
|
2962 |
|
|
assign mig_p2_cmd_instr = p1_cmd_instr;
|
2963 |
|
|
assign mig_p2_cmd_bl = {(p1_cmd_instr[2] | p1_cmd_bl[5]),p1_cmd_bl[4:0]} ;
|
2964 |
|
|
assign p1_cmd_empty = mig_p2_cmd_empty;
|
2965 |
|
|
assign p1_cmd_full = mig_p2_cmd_full;
|
2966 |
|
|
|
2967 |
|
|
assign mig_p2_clk = p1_rd_clk;
|
2968 |
|
|
assign mig_p3_clk = p1_wr_clk;
|
2969 |
|
|
|
2970 |
|
|
assign mig_p3_en = p1_wr_en;
|
2971 |
|
|
assign mig_p3_wr_data = p1_wr_data[31:0];
|
2972 |
|
|
assign mig_p3_wr_mask = p1_wr_mask[3:0];
|
2973 |
|
|
assign mig_p2_en = p1_rd_en;
|
2974 |
|
|
|
2975 |
|
|
assign p1_rd_data = mig_p2_rd_data;
|
2976 |
|
|
assign p1_wr_count = mig_p3_count;
|
2977 |
|
|
assign p1_rd_count = mig_p2_count;
|
2978 |
|
|
assign p1_wr_empty = mig_p3_empty;
|
2979 |
|
|
assign p1_wr_error = mig_p3_error;
|
2980 |
|
|
assign p1_wr_full = mig_p3_full;
|
2981 |
|
|
assign p1_wr_underrun = mig_p3_underrun;
|
2982 |
|
|
assign p1_rd_overflow = mig_p2_overflow;
|
2983 |
|
|
assign p1_rd_error = mig_p2_error;
|
2984 |
|
|
assign p1_rd_full = mig_p2_full;
|
2985 |
|
|
assign p1_rd_empty = mig_p2_empty;
|
2986 |
|
|
|
2987 |
|
|
end else
|
2988 |
|
|
begin
|
2989 |
|
|
|
2990 |
|
|
assign mig_p2_arb_en = 'b0;
|
2991 |
|
|
assign mig_p2_cmd_clk = 'b0;
|
2992 |
|
|
assign mig_p2_cmd_en = 'b0;
|
2993 |
|
|
assign mig_p2_cmd_ra = 'b0;
|
2994 |
|
|
assign mig_p2_cmd_ba = 'b0;
|
2995 |
|
|
assign mig_p2_cmd_ca = 'b0;
|
2996 |
|
|
assign mig_p2_cmd_instr = 'b0;
|
2997 |
|
|
assign mig_p2_cmd_bl = 'b0;
|
2998 |
|
|
assign p1_cmd_empty = 'b0;
|
2999 |
|
|
assign p1_cmd_full = 'b0;
|
3000 |
|
|
assign mig_p3_en = 'b0;
|
3001 |
|
|
assign mig_p3_wr_data = 'b0;
|
3002 |
|
|
assign mig_p3_wr_mask = 'b0;
|
3003 |
|
|
assign mig_p2_en = 'b0;
|
3004 |
|
|
|
3005 |
|
|
assign mig_p2_clk = 'b0;
|
3006 |
|
|
assign mig_p3_clk = 'b0;
|
3007 |
|
|
|
3008 |
|
|
assign p1_rd_data = 'b0;
|
3009 |
|
|
assign p1_wr_count = 'b0;
|
3010 |
|
|
assign p1_rd_count = 'b0;
|
3011 |
|
|
assign p1_wr_empty = 'b0;
|
3012 |
|
|
assign p1_wr_error = 'b0;
|
3013 |
|
|
assign p1_wr_full = 'b0;
|
3014 |
|
|
assign p1_wr_underrun = 'b0;
|
3015 |
|
|
assign p1_rd_overflow = 'b0;
|
3016 |
|
|
assign p1_rd_error = 'b0;
|
3017 |
|
|
assign p1_rd_full = 'b0;
|
3018 |
|
|
assign p1_rd_empty = 'b0;
|
3019 |
|
|
|
3020 |
|
|
end
|
3021 |
|
|
|
3022 |
|
|
if (C_PORT_ENABLE[2] == 1'b1)
|
3023 |
|
|
begin
|
3024 |
|
|
assign mig_p4_arb_en = p2_arb_en ;
|
3025 |
|
|
assign mig_p4_cmd_clk = p2_cmd_clk ;
|
3026 |
|
|
assign mig_p4_cmd_en = p2_cmd_en ;
|
3027 |
|
|
assign mig_p4_cmd_ra = p2_cmd_ra ;
|
3028 |
|
|
assign mig_p4_cmd_ba = p2_cmd_ba ;
|
3029 |
|
|
assign mig_p4_cmd_ca = p2_cmd_ca ;
|
3030 |
|
|
assign mig_p4_cmd_instr = p2_cmd_instr;
|
3031 |
|
|
assign mig_p4_cmd_bl = {(p2_cmd_instr[2] | p2_cmd_bl[5]),p2_cmd_bl[4:0]} ;
|
3032 |
|
|
assign p2_cmd_empty = mig_p4_cmd_empty ;
|
3033 |
|
|
assign p2_cmd_full = mig_p4_cmd_full ;
|
3034 |
|
|
assign mig_p5_en = p2_wr_en;
|
3035 |
|
|
assign mig_p5_wr_data = p2_wr_data[31:0];
|
3036 |
|
|
assign mig_p5_wr_mask = p2_wr_mask[3:0];
|
3037 |
|
|
assign mig_p4_en = p2_rd_en;
|
3038 |
|
|
|
3039 |
|
|
assign mig_p4_clk = p2_rd_clk;
|
3040 |
|
|
assign mig_p5_clk = p2_wr_clk;
|
3041 |
|
|
|
3042 |
|
|
assign p2_rd_data = mig_p4_rd_data;
|
3043 |
|
|
assign p2_wr_count = mig_p5_count;
|
3044 |
|
|
assign p2_rd_count = mig_p4_count;
|
3045 |
|
|
assign p2_wr_empty = mig_p5_empty;
|
3046 |
|
|
assign p2_wr_full = mig_p5_full;
|
3047 |
|
|
assign p2_wr_error = mig_p5_error;
|
3048 |
|
|
assign p2_wr_underrun = mig_p5_underrun;
|
3049 |
|
|
assign p2_rd_overflow = mig_p4_overflow;
|
3050 |
|
|
assign p2_rd_error = mig_p4_error;
|
3051 |
|
|
assign p2_rd_full = mig_p4_full;
|
3052 |
|
|
assign p2_rd_empty = mig_p4_empty;
|
3053 |
|
|
|
3054 |
|
|
end else
|
3055 |
|
|
begin
|
3056 |
|
|
assign mig_p4_arb_en = 'b0;
|
3057 |
|
|
assign mig_p4_cmd_clk = 'b0;
|
3058 |
|
|
assign mig_p4_cmd_en = 'b0;
|
3059 |
|
|
assign mig_p4_cmd_ra = 'b0;
|
3060 |
|
|
assign mig_p4_cmd_ba = 'b0;
|
3061 |
|
|
assign mig_p4_cmd_ca = 'b0;
|
3062 |
|
|
assign mig_p4_cmd_instr = 'b0;
|
3063 |
|
|
assign mig_p4_cmd_bl = 'b0;
|
3064 |
|
|
assign p2_cmd_empty = 'b0;
|
3065 |
|
|
assign p2_cmd_full = 'b0;
|
3066 |
|
|
assign mig_p5_en = 'b0;
|
3067 |
|
|
assign mig_p5_wr_data = 'b0;
|
3068 |
|
|
assign mig_p5_wr_mask = 'b0;
|
3069 |
|
|
assign mig_p4_en = 'b0;
|
3070 |
|
|
|
3071 |
|
|
assign mig_p4_clk = 'b0;
|
3072 |
|
|
assign mig_p5_clk = 'b0;
|
3073 |
|
|
|
3074 |
|
|
assign p2_rd_data = 'b0;
|
3075 |
|
|
assign p2_wr_count = 'b0;
|
3076 |
|
|
assign p2_rd_count = 'b0;
|
3077 |
|
|
assign p2_wr_empty = 'b0;
|
3078 |
|
|
assign p2_wr_full = 'b0;
|
3079 |
|
|
assign p2_wr_error = 'b0;
|
3080 |
|
|
assign p2_wr_underrun = 'b0;
|
3081 |
|
|
assign p2_rd_overflow = 'b0;
|
3082 |
|
|
assign p2_rd_error = 'b0;
|
3083 |
|
|
assign p2_rd_full = 'b0;
|
3084 |
|
|
assign p2_rd_empty = 'b0;
|
3085 |
|
|
|
3086 |
|
|
end
|
3087 |
|
|
|
3088 |
|
|
|
3089 |
|
|
// MCB's port 1,3,5 is not used in this Config mode
|
3090 |
|
|
assign mig_p1_arb_en = 1'b0;
|
3091 |
|
|
assign mig_p1_cmd_clk = 1'b0;
|
3092 |
|
|
assign mig_p1_cmd_en = 1'b0;
|
3093 |
|
|
assign mig_p1_cmd_ra = 15'd0;
|
3094 |
|
|
assign mig_p1_cmd_ba = 3'd0;
|
3095 |
|
|
assign mig_p1_cmd_ca = 12'd0;
|
3096 |
|
|
|
3097 |
|
|
assign mig_p1_cmd_instr = 3'd0;
|
3098 |
|
|
assign mig_p1_cmd_bl = 6'd0;
|
3099 |
|
|
|
3100 |
|
|
assign mig_p3_arb_en = 1'b0;
|
3101 |
|
|
assign mig_p3_cmd_clk = 1'b0;
|
3102 |
|
|
assign mig_p3_cmd_en = 1'b0;
|
3103 |
|
|
assign mig_p3_cmd_ra = 15'd0;
|
3104 |
|
|
assign mig_p3_cmd_ba = 3'd0;
|
3105 |
|
|
assign mig_p3_cmd_ca = 12'd0;
|
3106 |
|
|
|
3107 |
|
|
assign mig_p3_cmd_instr = 3'd0;
|
3108 |
|
|
assign mig_p3_cmd_bl = 6'd0;
|
3109 |
|
|
|
3110 |
|
|
assign mig_p5_arb_en = 1'b0;
|
3111 |
|
|
assign mig_p5_cmd_clk = 1'b0;
|
3112 |
|
|
assign mig_p5_cmd_en = 1'b0;
|
3113 |
|
|
assign mig_p5_cmd_ra = 15'd0;
|
3114 |
|
|
assign mig_p5_cmd_ba = 3'd0;
|
3115 |
|
|
assign mig_p5_cmd_ca = 12'd0;
|
3116 |
|
|
|
3117 |
|
|
assign mig_p5_cmd_instr = 3'd0;
|
3118 |
|
|
assign mig_p5_cmd_bl = 6'd0;
|
3119 |
|
|
|
3120 |
|
|
|
3121 |
|
|
|
3122 |
|
|
end else if(C_PORT_CONFIG == "B64_B64" ) begin : u_config_4
|
3123 |
|
|
|
3124 |
|
|
// Inputs from Application CMD Port
|
3125 |
|
|
|
3126 |
|
|
if (C_PORT_ENABLE[0] == 1'b1)
|
3127 |
|
|
begin
|
3128 |
|
|
|
3129 |
|
|
assign mig_p0_arb_en = p0_arb_en ;
|
3130 |
|
|
assign mig_p1_arb_en = p0_arb_en ;
|
3131 |
|
|
|
3132 |
|
|
assign mig_p0_cmd_clk = p0_cmd_clk ;
|
3133 |
|
|
assign mig_p0_cmd_en = p0_cmd_en ;
|
3134 |
|
|
assign mig_p0_cmd_ra = p0_cmd_ra ;
|
3135 |
|
|
assign mig_p0_cmd_ba = p0_cmd_ba ;
|
3136 |
|
|
assign mig_p0_cmd_ca = p0_cmd_ca ;
|
3137 |
|
|
assign mig_p0_cmd_instr = p0_cmd_instr;
|
3138 |
|
|
assign mig_p0_cmd_bl = {(p0_cmd_instr[2] | p0_cmd_bl[5]),p0_cmd_bl[4:0]} ;
|
3139 |
|
|
|
3140 |
|
|
|
3141 |
|
|
assign mig_p0_wr_clk = p0_wr_clk;
|
3142 |
|
|
assign mig_p0_rd_clk = p0_rd_clk;
|
3143 |
|
|
assign mig_p1_wr_clk = p0_wr_clk;
|
3144 |
|
|
assign mig_p1_rd_clk = p0_rd_clk;
|
3145 |
|
|
assign mig_p0_wr_en = p0_wr_en & !p0_wr_full;
|
3146 |
|
|
assign mig_p0_wr_data = p0_wr_data[31:0];
|
3147 |
|
|
assign mig_p0_wr_mask = p0_wr_mask[3:0];
|
3148 |
|
|
assign mig_p1_wr_data = p0_wr_data[63 : 32];
|
3149 |
|
|
assign mig_p1_wr_mask = p0_wr_mask[7 : 4];
|
3150 |
|
|
assign mig_p1_wr_en = p0_wr_en & !p0_wr_full;
|
3151 |
|
|
assign mig_p0_rd_en = p0_rd_en & !p0_rd_empty;
|
3152 |
|
|
assign mig_p1_rd_en = p0_rd_en & !p0_rd_empty;
|
3153 |
|
|
assign p0_rd_data = {mig_p1_rd_data , mig_p0_rd_data};
|
3154 |
|
|
|
3155 |
|
|
assign p0_cmd_empty = mig_p0_cmd_empty ;
|
3156 |
|
|
assign p0_cmd_full = mig_p0_cmd_full ;
|
3157 |
|
|
assign p0_wr_empty = mig_p1_wr_empty;
|
3158 |
|
|
assign p0_wr_full = mig_p1_wr_full;
|
3159 |
|
|
assign p0_wr_error = mig_p1_wr_error | mig_p0_wr_error;
|
3160 |
|
|
assign p0_wr_count = mig_p1_wr_count;
|
3161 |
|
|
assign p0_rd_count = mig_p1_rd_count;
|
3162 |
|
|
assign p0_wr_underrun = mig_p1_wr_underrun | mig_p0_wr_underrun;
|
3163 |
|
|
assign p0_rd_overflow = mig_p1_rd_overflow | mig_p0_rd_overflow;
|
3164 |
|
|
assign p0_rd_error = mig_p1_rd_error | mig_p0_rd_error;
|
3165 |
|
|
assign p0_rd_full = mig_p1_rd_full;
|
3166 |
|
|
assign p0_rd_empty = mig_p1_rd_empty;
|
3167 |
|
|
|
3168 |
|
|
|
3169 |
|
|
end else
|
3170 |
|
|
begin
|
3171 |
|
|
assign mig_p0_arb_en = 'b0;
|
3172 |
|
|
assign mig_p0_cmd_clk = 'b0;
|
3173 |
|
|
assign mig_p0_cmd_en = 'b0;
|
3174 |
|
|
assign mig_p0_cmd_ra = 'b0;
|
3175 |
|
|
assign mig_p0_cmd_ba = 'b0;
|
3176 |
|
|
assign mig_p0_cmd_ca = 'b0;
|
3177 |
|
|
assign mig_p0_cmd_instr = 'b0;
|
3178 |
|
|
assign mig_p0_cmd_bl = 'b0;
|
3179 |
|
|
|
3180 |
|
|
assign mig_p0_wr_clk = 'b0;
|
3181 |
|
|
assign mig_p0_rd_clk = 'b0;
|
3182 |
|
|
assign mig_p1_wr_clk = 'b0;
|
3183 |
|
|
assign mig_p1_rd_clk = 'b0;
|
3184 |
|
|
assign mig_p0_wr_en = 'b0;
|
3185 |
|
|
assign mig_p1_wr_en = 'b0;
|
3186 |
|
|
assign mig_p0_wr_data = 'b0;
|
3187 |
|
|
assign mig_p0_wr_mask = 'b0;
|
3188 |
|
|
assign mig_p1_wr_data = 'b0;
|
3189 |
|
|
assign mig_p1_wr_mask = 'b0;
|
3190 |
|
|
// assign mig_p1_wr_en = 'b0;
|
3191 |
|
|
assign mig_p0_rd_en = 'b0;
|
3192 |
|
|
assign mig_p1_rd_en = 'b0;
|
3193 |
|
|
assign p0_rd_data = 'b0;
|
3194 |
|
|
|
3195 |
|
|
|
3196 |
|
|
assign p0_cmd_empty = 'b0;
|
3197 |
|
|
assign p0_cmd_full = 'b0;
|
3198 |
|
|
assign p0_wr_empty = 'b0;
|
3199 |
|
|
assign p0_wr_full = 'b0;
|
3200 |
|
|
assign p0_wr_error = 'b0;
|
3201 |
|
|
assign p0_wr_count = 'b0;
|
3202 |
|
|
assign p0_rd_count = 'b0;
|
3203 |
|
|
assign p0_wr_underrun = 'b0;
|
3204 |
|
|
assign p0_rd_overflow = 'b0;
|
3205 |
|
|
assign p0_rd_error = 'b0;
|
3206 |
|
|
assign p0_rd_full = 'b0;
|
3207 |
|
|
assign p0_rd_empty = 'b0;
|
3208 |
|
|
|
3209 |
|
|
|
3210 |
|
|
end
|
3211 |
|
|
|
3212 |
|
|
|
3213 |
|
|
|
3214 |
|
|
if (C_PORT_ENABLE[1] == 1'b1)
|
3215 |
|
|
begin
|
3216 |
|
|
|
3217 |
|
|
assign mig_p2_arb_en = p1_arb_en ;
|
3218 |
|
|
|
3219 |
|
|
assign mig_p2_cmd_clk = p1_cmd_clk ;
|
3220 |
|
|
assign mig_p2_cmd_en = p1_cmd_en ;
|
3221 |
|
|
assign mig_p2_cmd_ra = p1_cmd_ra ;
|
3222 |
|
|
assign mig_p2_cmd_ba = p1_cmd_ba ;
|
3223 |
|
|
assign mig_p2_cmd_ca = p1_cmd_ca ;
|
3224 |
|
|
assign mig_p2_cmd_instr = p1_cmd_instr;
|
3225 |
|
|
assign mig_p2_cmd_bl = {(p1_cmd_instr[2] | p1_cmd_bl[5]),p1_cmd_bl[4:0]} ;
|
3226 |
|
|
|
3227 |
|
|
|
3228 |
|
|
assign mig_p2_clk = p1_rd_clk;
|
3229 |
|
|
assign mig_p3_clk = p1_wr_clk;
|
3230 |
|
|
assign mig_p4_clk = p1_rd_clk;
|
3231 |
|
|
assign mig_p5_clk = p1_wr_clk;
|
3232 |
|
|
assign mig_p3_en = p1_wr_en & !p1_wr_full;
|
3233 |
|
|
assign mig_p5_en = p1_wr_en & !p1_wr_full;
|
3234 |
|
|
assign mig_p3_wr_data = p1_wr_data[31:0];
|
3235 |
|
|
assign mig_p3_wr_mask = p1_wr_mask[3:0];
|
3236 |
|
|
assign mig_p5_wr_data = p1_wr_data[63 : 32];
|
3237 |
|
|
assign mig_p5_wr_mask = p1_wr_mask[7 : 4];
|
3238 |
|
|
assign mig_p2_en = p1_rd_en & !p1_rd_empty;
|
3239 |
|
|
assign mig_p4_en = p1_rd_en & !p1_rd_empty;
|
3240 |
|
|
|
3241 |
|
|
assign p1_cmd_empty = mig_p2_cmd_empty ;
|
3242 |
|
|
assign p1_cmd_full = mig_p2_cmd_full ;
|
3243 |
|
|
|
3244 |
|
|
assign p1_wr_count = mig_p5_count;
|
3245 |
|
|
assign p1_rd_count = mig_p4_count;
|
3246 |
|
|
assign p1_wr_full = mig_p5_full;
|
3247 |
|
|
assign p1_wr_error = mig_p5_error | mig_p5_error;
|
3248 |
|
|
assign p1_wr_empty = mig_p5_empty;
|
3249 |
|
|
assign p1_wr_underrun = mig_p3_underrun | mig_p5_underrun;
|
3250 |
|
|
assign p1_rd_overflow = mig_p4_overflow;
|
3251 |
|
|
assign p1_rd_error = mig_p4_error;
|
3252 |
|
|
assign p1_rd_full = mig_p4_full;
|
3253 |
|
|
assign p1_rd_empty = mig_p4_empty;
|
3254 |
|
|
|
3255 |
|
|
assign p1_rd_data = {mig_p4_rd_data , mig_p2_rd_data};
|
3256 |
|
|
|
3257 |
|
|
|
3258 |
|
|
end else
|
3259 |
|
|
begin
|
3260 |
|
|
assign mig_p2_arb_en = 'b0;
|
3261 |
|
|
// assign mig_p3_arb_en = 'b0;
|
3262 |
|
|
// assign mig_p4_arb_en = 'b0;
|
3263 |
|
|
// assign mig_p5_arb_en = 'b0;
|
3264 |
|
|
|
3265 |
|
|
assign mig_p2_cmd_clk = 'b0;
|
3266 |
|
|
assign mig_p2_cmd_en = 'b0;
|
3267 |
|
|
assign mig_p2_cmd_ra = 'b0;
|
3268 |
|
|
assign mig_p2_cmd_ba = 'b0;
|
3269 |
|
|
assign mig_p2_cmd_ca = 'b0;
|
3270 |
|
|
assign mig_p2_cmd_instr = 'b0;
|
3271 |
|
|
assign mig_p2_cmd_bl = 'b0;
|
3272 |
|
|
assign mig_p2_clk = 'b0;
|
3273 |
|
|
assign mig_p3_clk = 'b0;
|
3274 |
|
|
assign mig_p4_clk = 'b0;
|
3275 |
|
|
assign mig_p5_clk = 'b0;
|
3276 |
|
|
assign mig_p3_en = 'b0;
|
3277 |
|
|
assign mig_p5_en = 'b0;
|
3278 |
|
|
assign mig_p3_wr_data = 'b0;
|
3279 |
|
|
assign mig_p3_wr_mask = 'b0;
|
3280 |
|
|
assign mig_p5_wr_data = 'b0;
|
3281 |
|
|
assign mig_p5_wr_mask = 'b0;
|
3282 |
|
|
assign mig_p2_en = 'b0;
|
3283 |
|
|
assign mig_p4_en = 'b0;
|
3284 |
|
|
assign p1_cmd_empty = 'b0;
|
3285 |
|
|
assign p1_cmd_full = 'b0;
|
3286 |
|
|
|
3287 |
|
|
assign p1_wr_count = 'b0;
|
3288 |
|
|
assign p1_rd_count = 'b0;
|
3289 |
|
|
assign p1_wr_full = 'b0;
|
3290 |
|
|
assign p1_wr_error = 'b0;
|
3291 |
|
|
assign p1_wr_empty = 'b0;
|
3292 |
|
|
assign p1_wr_underrun = 'b0;
|
3293 |
|
|
assign p1_rd_overflow = 'b0;
|
3294 |
|
|
assign p1_rd_error = 'b0;
|
3295 |
|
|
assign p1_rd_full = 'b0;
|
3296 |
|
|
assign p1_rd_empty = 'b0;
|
3297 |
|
|
assign p1_rd_data = 'b0;
|
3298 |
|
|
|
3299 |
|
|
end
|
3300 |
|
|
|
3301 |
|
|
// unused MCB's signals in this configuration
|
3302 |
|
|
assign mig_p3_arb_en = 1'b0;
|
3303 |
|
|
assign mig_p4_arb_en = 1'b0;
|
3304 |
|
|
assign mig_p5_arb_en = 1'b0;
|
3305 |
|
|
|
3306 |
|
|
assign mig_p3_cmd_clk = 1'b0;
|
3307 |
|
|
assign mig_p3_cmd_en = 1'b0;
|
3308 |
|
|
assign mig_p3_cmd_ra = 15'd0;
|
3309 |
|
|
assign mig_p3_cmd_ba = 3'd0;
|
3310 |
|
|
assign mig_p3_cmd_ca = 12'd0;
|
3311 |
|
|
assign mig_p3_cmd_instr = 3'd0;
|
3312 |
|
|
|
3313 |
|
|
assign mig_p4_cmd_clk = 1'b0;
|
3314 |
|
|
assign mig_p4_cmd_en = 1'b0;
|
3315 |
|
|
assign mig_p4_cmd_ra = 15'd0;
|
3316 |
|
|
assign mig_p4_cmd_ba = 3'd0;
|
3317 |
|
|
assign mig_p4_cmd_ca = 12'd0;
|
3318 |
|
|
assign mig_p4_cmd_instr = 3'd0;
|
3319 |
|
|
assign mig_p4_cmd_bl = 6'd0;
|
3320 |
|
|
|
3321 |
|
|
assign mig_p5_cmd_clk = 1'b0;
|
3322 |
|
|
assign mig_p5_cmd_en = 1'b0;
|
3323 |
|
|
assign mig_p5_cmd_ra = 15'd0;
|
3324 |
|
|
assign mig_p5_cmd_ba = 3'd0;
|
3325 |
|
|
assign mig_p5_cmd_ca = 12'd0;
|
3326 |
|
|
assign mig_p5_cmd_instr = 3'd0;
|
3327 |
|
|
assign mig_p5_cmd_bl = 6'd0;
|
3328 |
|
|
|
3329 |
|
|
|
3330 |
|
|
|
3331 |
|
|
|
3332 |
|
|
end else if(C_PORT_CONFIG == "B128" ) begin : u_config_5
|
3333 |
|
|
//*******************************BEGIN OF CONFIG 5 SIGNALS ********************************
|
3334 |
|
|
|
3335 |
|
|
// Inputs from Application CMD Port
|
3336 |
|
|
|
3337 |
|
|
assign mig_p0_arb_en = p0_arb_en ;
|
3338 |
|
|
assign mig_p0_cmd_clk = p0_cmd_clk ;
|
3339 |
|
|
assign mig_p0_cmd_en = p0_cmd_en ;
|
3340 |
|
|
assign mig_p0_cmd_ra = p0_cmd_ra ;
|
3341 |
|
|
assign mig_p0_cmd_ba = p0_cmd_ba ;
|
3342 |
|
|
assign mig_p0_cmd_ca = p0_cmd_ca ;
|
3343 |
|
|
assign mig_p0_cmd_instr = p0_cmd_instr;
|
3344 |
|
|
assign mig_p0_cmd_bl = {(p0_cmd_instr[2] | p0_cmd_bl[5]),p0_cmd_bl[4:0]} ;
|
3345 |
|
|
|
3346 |
|
|
assign p0_cmd_empty = mig_p0_cmd_empty ;
|
3347 |
|
|
assign p0_cmd_full = mig_p0_cmd_full ;
|
3348 |
|
|
|
3349 |
|
|
|
3350 |
|
|
|
3351 |
|
|
// Inputs from Application User Port
|
3352 |
|
|
|
3353 |
|
|
assign mig_p0_wr_clk = p0_wr_clk;
|
3354 |
|
|
assign mig_p0_rd_clk = p0_rd_clk;
|
3355 |
|
|
assign mig_p1_wr_clk = p0_wr_clk;
|
3356 |
|
|
assign mig_p1_rd_clk = p0_rd_clk;
|
3357 |
|
|
|
3358 |
|
|
assign mig_p2_clk = p0_rd_clk;
|
3359 |
|
|
assign mig_p3_clk = p0_wr_clk;
|
3360 |
|
|
assign mig_p4_clk = p0_rd_clk;
|
3361 |
|
|
assign mig_p5_clk = p0_wr_clk;
|
3362 |
|
|
|
3363 |
|
|
|
3364 |
|
|
|
3365 |
|
|
assign mig_p0_wr_en = p0_wr_en & !p0_wr_full;
|
3366 |
|
|
assign mig_p1_wr_en = p0_wr_en & !p0_wr_full;
|
3367 |
|
|
assign mig_p3_en = p0_wr_en & !p0_wr_full;
|
3368 |
|
|
assign mig_p5_en = p0_wr_en & !p0_wr_full;
|
3369 |
|
|
|
3370 |
|
|
|
3371 |
|
|
|
3372 |
|
|
assign mig_p0_wr_data = p0_wr_data[31:0];
|
3373 |
|
|
assign mig_p0_wr_mask = p0_wr_mask[3:0];
|
3374 |
|
|
assign mig_p1_wr_data = p0_wr_data[63 : 32];
|
3375 |
|
|
assign mig_p1_wr_mask = p0_wr_mask[7 : 4];
|
3376 |
|
|
assign mig_p3_wr_data = p0_wr_data[95 : 64];
|
3377 |
|
|
assign mig_p3_wr_mask = p0_wr_mask[11 : 8];
|
3378 |
|
|
assign mig_p5_wr_data = p0_wr_data[127 : 96];
|
3379 |
|
|
assign mig_p5_wr_mask = p0_wr_mask[15 : 12];
|
3380 |
|
|
|
3381 |
|
|
assign mig_p0_rd_en = p0_rd_en & !p0_rd_empty;
|
3382 |
|
|
assign mig_p1_rd_en = p0_rd_en & !p0_rd_empty;
|
3383 |
|
|
assign mig_p2_en = p0_rd_en & !p0_rd_empty;
|
3384 |
|
|
assign mig_p4_en = p0_rd_en & !p0_rd_empty;
|
3385 |
|
|
|
3386 |
|
|
// outputs to Applications User Port
|
3387 |
|
|
assign p0_rd_data = {mig_p4_rd_data , mig_p2_rd_data , mig_p1_rd_data , mig_p0_rd_data};
|
3388 |
|
|
assign p0_rd_empty = mig_p4_empty;
|
3389 |
|
|
assign p0_rd_full = mig_p4_full;
|
3390 |
|
|
assign p0_rd_error = mig_p0_rd_error | mig_p1_rd_error | mig_p2_error | mig_p4_error;
|
3391 |
|
|
assign p0_rd_overflow = mig_p0_rd_overflow | mig_p1_rd_overflow | mig_p2_overflow | mig_p4_overflow;
|
3392 |
|
|
|
3393 |
|
|
assign p0_wr_underrun = mig_p0_wr_underrun | mig_p1_wr_underrun | mig_p3_underrun | mig_p5_underrun;
|
3394 |
|
|
assign p0_wr_empty = mig_p5_empty;
|
3395 |
|
|
assign p0_wr_full = mig_p5_full;
|
3396 |
|
|
assign p0_wr_error = mig_p0_wr_error | mig_p1_wr_error | mig_p3_error | mig_p5_error;
|
3397 |
|
|
|
3398 |
|
|
assign p0_wr_count = mig_p5_count;
|
3399 |
|
|
assign p0_rd_count = mig_p4_count;
|
3400 |
|
|
|
3401 |
|
|
|
3402 |
|
|
// unused MCB's siganls in this configuration
|
3403 |
|
|
|
3404 |
|
|
assign mig_p1_arb_en = 1'b0;
|
3405 |
|
|
assign mig_p1_cmd_clk = 1'b0;
|
3406 |
|
|
assign mig_p1_cmd_en = 1'b0;
|
3407 |
|
|
assign mig_p1_cmd_ra = 15'd0;
|
3408 |
|
|
assign mig_p1_cmd_ba = 3'd0;
|
3409 |
|
|
assign mig_p1_cmd_ca = 12'd0;
|
3410 |
|
|
|
3411 |
|
|
assign mig_p1_cmd_instr = 3'd0;
|
3412 |
|
|
assign mig_p1_cmd_bl = 6'd0;
|
3413 |
|
|
|
3414 |
|
|
assign mig_p2_arb_en = 1'b0;
|
3415 |
|
|
assign mig_p2_cmd_clk = 1'b0;
|
3416 |
|
|
assign mig_p2_cmd_en = 1'b0;
|
3417 |
|
|
assign mig_p2_cmd_ra = 15'd0;
|
3418 |
|
|
assign mig_p2_cmd_ba = 3'd0;
|
3419 |
|
|
assign mig_p2_cmd_ca = 12'd0;
|
3420 |
|
|
|
3421 |
|
|
assign mig_p2_cmd_instr = 3'd0;
|
3422 |
|
|
assign mig_p2_cmd_bl = 6'd0;
|
3423 |
|
|
|
3424 |
|
|
assign mig_p3_arb_en = 1'b0;
|
3425 |
|
|
assign mig_p3_cmd_clk = 1'b0;
|
3426 |
|
|
assign mig_p3_cmd_en = 1'b0;
|
3427 |
|
|
assign mig_p3_cmd_ra = 15'd0;
|
3428 |
|
|
assign mig_p3_cmd_ba = 3'd0;
|
3429 |
|
|
assign mig_p3_cmd_ca = 12'd0;
|
3430 |
|
|
|
3431 |
|
|
assign mig_p3_cmd_instr = 3'd0;
|
3432 |
|
|
assign mig_p3_cmd_bl = 6'd0;
|
3433 |
|
|
|
3434 |
|
|
assign mig_p4_arb_en = 1'b0;
|
3435 |
|
|
assign mig_p4_cmd_clk = 1'b0;
|
3436 |
|
|
assign mig_p4_cmd_en = 1'b0;
|
3437 |
|
|
assign mig_p4_cmd_ra = 15'd0;
|
3438 |
|
|
assign mig_p4_cmd_ba = 3'd0;
|
3439 |
|
|
assign mig_p4_cmd_ca = 12'd0;
|
3440 |
|
|
|
3441 |
|
|
assign mig_p4_cmd_instr = 3'd0;
|
3442 |
|
|
assign mig_p4_cmd_bl = 6'd0;
|
3443 |
|
|
|
3444 |
|
|
assign mig_p5_arb_en = 1'b0;
|
3445 |
|
|
assign mig_p5_cmd_clk = 1'b0;
|
3446 |
|
|
assign mig_p5_cmd_en = 1'b0;
|
3447 |
|
|
assign mig_p5_cmd_ra = 15'd0;
|
3448 |
|
|
assign mig_p5_cmd_ba = 3'd0;
|
3449 |
|
|
assign mig_p5_cmd_ca = 12'd0;
|
3450 |
|
|
|
3451 |
|
|
assign mig_p5_cmd_instr = 3'd0;
|
3452 |
|
|
assign mig_p5_cmd_bl = 6'd0;
|
3453 |
|
|
|
3454 |
|
|
//*******************************END OF CONFIG 5 SIGNALS ********************************
|
3455 |
|
|
|
3456 |
|
|
end
|
3457 |
|
|
endgenerate
|
3458 |
|
|
|
3459 |
|
|
MCB
|
3460 |
|
|
# ( .PORT_CONFIG (C_PORT_CONFIG),
|
3461 |
|
|
.MEM_WIDTH (C_NUM_DQ_PINS ),
|
3462 |
|
|
.MEM_TYPE (C_MEM_TYPE ),
|
3463 |
|
|
.MEM_BURST_LEN (C_MEM_BURST_LEN ),
|
3464 |
|
|
.MEM_ADDR_ORDER (C_MEM_ADDR_ORDER),
|
3465 |
|
|
.MEM_CAS_LATENCY (C_MEM_CAS_LATENCY),
|
3466 |
|
|
.MEM_DDR3_CAS_LATENCY (C_MEM_DDR3_CAS_LATENCY ),
|
3467 |
|
|
.MEM_DDR2_WRT_RECOVERY (C_MEM_DDR2_WRT_RECOVERY ),
|
3468 |
|
|
.MEM_DDR3_WRT_RECOVERY (C_MEM_DDR3_WRT_RECOVERY ),
|
3469 |
|
|
.MEM_MOBILE_PA_SR (C_MEM_MOBILE_PA_SR ),
|
3470 |
|
|
.MEM_DDR1_2_ODS (C_MEM_DDR1_2_ODS ),
|
3471 |
|
|
.MEM_DDR3_ODS (C_MEM_DDR3_ODS ),
|
3472 |
|
|
.MEM_DDR2_RTT (C_MEM_DDR2_RTT ),
|
3473 |
|
|
.MEM_DDR3_RTT (C_MEM_DDR3_RTT ),
|
3474 |
|
|
.MEM_DDR3_ADD_LATENCY (C_MEM_DDR3_ADD_LATENCY ),
|
3475 |
|
|
.MEM_DDR2_ADD_LATENCY (C_MEM_DDR2_ADD_LATENCY ),
|
3476 |
|
|
.MEM_MOBILE_TC_SR (C_MEM_MOBILE_TC_SR ),
|
3477 |
|
|
.MEM_MDDR_ODS (C_MEM_MDDR_ODS ),
|
3478 |
|
|
.MEM_DDR2_DIFF_DQS_EN (C_MEM_DDR2_DIFF_DQS_EN ),
|
3479 |
|
|
.MEM_DDR2_3_PA_SR (C_MEM_DDR2_3_PA_SR ),
|
3480 |
|
|
.MEM_DDR3_CAS_WR_LATENCY (C_MEM_DDR3_CAS_WR_LATENCY),
|
3481 |
|
|
.MEM_DDR3_AUTO_SR (C_MEM_DDR3_AUTO_SR ),
|
3482 |
|
|
.MEM_DDR2_3_HIGH_TEMP_SR (C_MEM_DDR2_3_HIGH_TEMP_SR),
|
3483 |
|
|
.MEM_DDR3_DYN_WRT_ODT (C_MEM_DDR3_DYN_WRT_ODT ),
|
3484 |
|
|
.MEM_RA_SIZE (C_MEM_ADDR_WIDTH ),
|
3485 |
|
|
.MEM_BA_SIZE (C_MEM_BANKADDR_WIDTH ),
|
3486 |
|
|
.MEM_CA_SIZE (C_MEM_NUM_COL_BITS ),
|
3487 |
|
|
.MEM_RAS_VAL (MEM_RAS_VAL ),
|
3488 |
|
|
.MEM_RCD_VAL (MEM_RCD_VAL ),
|
3489 |
|
|
.MEM_REFI_VAL (MEM_REFI_VAL ),
|
3490 |
|
|
.MEM_RFC_VAL (MEM_RFC_VAL ),
|
3491 |
|
|
.MEM_RP_VAL (MEM_RP_VAL ),
|
3492 |
|
|
.MEM_WR_VAL (MEM_WR_VAL ),
|
3493 |
|
|
.MEM_RTP_VAL (MEM_RTP_VAL ),
|
3494 |
|
|
.MEM_WTR_VAL (MEM_WTR_VAL ),
|
3495 |
|
|
.CAL_BYPASS (C_MC_CALIB_BYPASS),
|
3496 |
|
|
.CAL_RA (C_MC_CALIBRATION_RA),
|
3497 |
|
|
.CAL_BA (C_MC_CALIBRATION_BA ),
|
3498 |
|
|
.CAL_CA (C_MC_CALIBRATION_CA),
|
3499 |
|
|
.CAL_CLK_DIV (C_MC_CALIBRATION_CLK_DIV),
|
3500 |
|
|
.CAL_DELAY (C_MC_CALIBRATION_DELAY),
|
3501 |
|
|
.ARB_NUM_TIME_SLOTS (C_ARB_NUM_TIME_SLOTS),
|
3502 |
|
|
.ARB_TIME_SLOT_0 (arbtimeslot0 ) ,
|
3503 |
|
|
.ARB_TIME_SLOT_1 (arbtimeslot1 ) ,
|
3504 |
|
|
.ARB_TIME_SLOT_2 (arbtimeslot2 ) ,
|
3505 |
|
|
.ARB_TIME_SLOT_3 (arbtimeslot3 ) ,
|
3506 |
|
|
.ARB_TIME_SLOT_4 (arbtimeslot4 ) ,
|
3507 |
|
|
.ARB_TIME_SLOT_5 (arbtimeslot5 ) ,
|
3508 |
|
|
.ARB_TIME_SLOT_6 (arbtimeslot6 ) ,
|
3509 |
|
|
.ARB_TIME_SLOT_7 (arbtimeslot7 ) ,
|
3510 |
|
|
.ARB_TIME_SLOT_8 (arbtimeslot8 ) ,
|
3511 |
|
|
.ARB_TIME_SLOT_9 (arbtimeslot9 ) ,
|
3512 |
|
|
.ARB_TIME_SLOT_10 (arbtimeslot10) ,
|
3513 |
|
|
.ARB_TIME_SLOT_11 (arbtimeslot11)
|
3514 |
|
|
) samc_0
|
3515 |
|
|
(
|
3516 |
|
|
|
3517 |
|
|
// HIGH-SPEED PLL clock interface
|
3518 |
|
|
|
3519 |
|
|
.PLLCLK ({ioclk90,ioclk0}),
|
3520 |
|
|
.PLLCE ({pll_ce_90,pll_ce_0}) ,
|
3521 |
|
|
|
3522 |
|
|
.PLLLOCK (1'b1),
|
3523 |
|
|
|
3524 |
|
|
// DQS CLOCK NETWork interface
|
3525 |
|
|
|
3526 |
|
|
.DQSIOIN (idelay_dqs_ioi_s),
|
3527 |
|
|
.DQSIOIP (idelay_dqs_ioi_m),
|
3528 |
|
|
.UDQSIOIN (idelay_udqs_ioi_s),
|
3529 |
|
|
.UDQSIOIP (idelay_udqs_ioi_m),
|
3530 |
|
|
|
3531 |
|
|
|
3532 |
|
|
//.DQSPIN (in_pre_dqsp),
|
3533 |
|
|
.DQI (in_dq),
|
3534 |
|
|
// RESETS - GLOBAl & local
|
3535 |
|
|
.SYSRST (MCB_SYSRST ),
|
3536 |
|
|
|
3537 |
|
|
// command port 0
|
3538 |
|
|
.P0ARBEN (mig_p0_arb_en),
|
3539 |
|
|
.P0CMDCLK (mig_p0_cmd_clk),
|
3540 |
|
|
.P0CMDEN (mig_p0_cmd_en),
|
3541 |
|
|
.P0CMDRA (mig_p0_cmd_ra),
|
3542 |
|
|
.P0CMDBA (mig_p0_cmd_ba),
|
3543 |
|
|
.P0CMDCA (mig_p0_cmd_ca),
|
3544 |
|
|
|
3545 |
|
|
.P0CMDINSTR (mig_p0_cmd_instr),
|
3546 |
|
|
.P0CMDBL (mig_p0_cmd_bl),
|
3547 |
|
|
.P0CMDEMPTY (mig_p0_cmd_empty),
|
3548 |
|
|
.P0CMDFULL (mig_p0_cmd_full),
|
3549 |
|
|
|
3550 |
|
|
// command port 1
|
3551 |
|
|
|
3552 |
|
|
.P1ARBEN (mig_p1_arb_en),
|
3553 |
|
|
.P1CMDCLK (mig_p1_cmd_clk),
|
3554 |
|
|
.P1CMDEN (mig_p1_cmd_en),
|
3555 |
|
|
.P1CMDRA (mig_p1_cmd_ra),
|
3556 |
|
|
.P1CMDBA (mig_p1_cmd_ba),
|
3557 |
|
|
.P1CMDCA (mig_p1_cmd_ca),
|
3558 |
|
|
|
3559 |
|
|
.P1CMDINSTR (mig_p1_cmd_instr),
|
3560 |
|
|
.P1CMDBL (mig_p1_cmd_bl),
|
3561 |
|
|
.P1CMDEMPTY (mig_p1_cmd_empty),
|
3562 |
|
|
.P1CMDFULL (mig_p1_cmd_full),
|
3563 |
|
|
|
3564 |
|
|
// command port 2
|
3565 |
|
|
|
3566 |
|
|
.P2ARBEN (mig_p2_arb_en),
|
3567 |
|
|
.P2CMDCLK (mig_p2_cmd_clk),
|
3568 |
|
|
.P2CMDEN (mig_p2_cmd_en),
|
3569 |
|
|
.P2CMDRA (mig_p2_cmd_ra),
|
3570 |
|
|
.P2CMDBA (mig_p2_cmd_ba),
|
3571 |
|
|
.P2CMDCA (mig_p2_cmd_ca),
|
3572 |
|
|
|
3573 |
|
|
.P2CMDINSTR (mig_p2_cmd_instr),
|
3574 |
|
|
.P2CMDBL (mig_p2_cmd_bl),
|
3575 |
|
|
.P2CMDEMPTY (mig_p2_cmd_empty),
|
3576 |
|
|
.P2CMDFULL (mig_p2_cmd_full),
|
3577 |
|
|
|
3578 |
|
|
// command port 3
|
3579 |
|
|
|
3580 |
|
|
.P3ARBEN (mig_p3_arb_en),
|
3581 |
|
|
.P3CMDCLK (mig_p3_cmd_clk),
|
3582 |
|
|
.P3CMDEN (mig_p3_cmd_en),
|
3583 |
|
|
.P3CMDRA (mig_p3_cmd_ra),
|
3584 |
|
|
.P3CMDBA (mig_p3_cmd_ba),
|
3585 |
|
|
.P3CMDCA (mig_p3_cmd_ca),
|
3586 |
|
|
|
3587 |
|
|
.P3CMDINSTR (mig_p3_cmd_instr),
|
3588 |
|
|
.P3CMDBL (mig_p3_cmd_bl),
|
3589 |
|
|
.P3CMDEMPTY (mig_p3_cmd_empty),
|
3590 |
|
|
.P3CMDFULL (mig_p3_cmd_full),
|
3591 |
|
|
|
3592 |
|
|
// command port 4 // don't care in config 2
|
3593 |
|
|
|
3594 |
|
|
.P4ARBEN (mig_p4_arb_en),
|
3595 |
|
|
.P4CMDCLK (mig_p4_cmd_clk),
|
3596 |
|
|
.P4CMDEN (mig_p4_cmd_en),
|
3597 |
|
|
.P4CMDRA (mig_p4_cmd_ra),
|
3598 |
|
|
.P4CMDBA (mig_p4_cmd_ba),
|
3599 |
|
|
.P4CMDCA (mig_p4_cmd_ca),
|
3600 |
|
|
|
3601 |
|
|
.P4CMDINSTR (mig_p4_cmd_instr),
|
3602 |
|
|
.P4CMDBL (mig_p4_cmd_bl),
|
3603 |
|
|
.P4CMDEMPTY (mig_p4_cmd_empty),
|
3604 |
|
|
.P4CMDFULL (mig_p4_cmd_full),
|
3605 |
|
|
|
3606 |
|
|
// command port 5 // don't care in config 2
|
3607 |
|
|
|
3608 |
|
|
.P5ARBEN (mig_p5_arb_en),
|
3609 |
|
|
.P5CMDCLK (mig_p5_cmd_clk),
|
3610 |
|
|
.P5CMDEN (mig_p5_cmd_en),
|
3611 |
|
|
.P5CMDRA (mig_p5_cmd_ra),
|
3612 |
|
|
.P5CMDBA (mig_p5_cmd_ba),
|
3613 |
|
|
.P5CMDCA (mig_p5_cmd_ca),
|
3614 |
|
|
|
3615 |
|
|
.P5CMDINSTR (mig_p5_cmd_instr),
|
3616 |
|
|
.P5CMDBL (mig_p5_cmd_bl),
|
3617 |
|
|
.P5CMDEMPTY (mig_p5_cmd_empty),
|
3618 |
|
|
.P5CMDFULL (mig_p5_cmd_full),
|
3619 |
|
|
|
3620 |
|
|
|
3621 |
|
|
// IOI & IOB SIGNals/tristate interface
|
3622 |
|
|
|
3623 |
|
|
.DQIOWEN0 (dqIO_w_en_0),
|
3624 |
|
|
.DQSIOWEN90P (dqsIO_w_en_90_p),
|
3625 |
|
|
.DQSIOWEN90N (dqsIO_w_en_90_n),
|
3626 |
|
|
|
3627 |
|
|
|
3628 |
|
|
// IOB MEMORY INTerface signals
|
3629 |
|
|
.ADDR (address_90),
|
3630 |
|
|
.BA (ba_90 ),
|
3631 |
|
|
.RAS (ras_90 ),
|
3632 |
|
|
.CAS (cas_90 ),
|
3633 |
|
|
.WE (we_90 ),
|
3634 |
|
|
.CKE (cke_90 ),
|
3635 |
|
|
.ODT (odt_90 ),
|
3636 |
|
|
.RST (rst_90 ),
|
3637 |
|
|
|
3638 |
|
|
// CALIBRATION DRP interface
|
3639 |
|
|
.IOIDRPCLK (ioi_drp_clk ),
|
3640 |
|
|
.IOIDRPADDR (ioi_drp_addr ),
|
3641 |
|
|
.IOIDRPSDO (ioi_drp_sdo ),
|
3642 |
|
|
.IOIDRPSDI (ioi_drp_sdi ),
|
3643 |
|
|
.IOIDRPCS (ioi_drp_cs ),
|
3644 |
|
|
.IOIDRPADD (ioi_drp_add ),
|
3645 |
|
|
.IOIDRPBROADCAST (ioi_drp_broadcast ),
|
3646 |
|
|
.IOIDRPTRAIN (ioi_drp_train ),
|
3647 |
|
|
.IOIDRPUPDATE (ioi_drp_update) ,
|
3648 |
|
|
|
3649 |
|
|
// CALIBRATION DAtacapture interface
|
3650 |
|
|
//SPECIAL COMMANDs
|
3651 |
|
|
.RECAL (mcb_recal ),
|
3652 |
|
|
.UIREAD (mcb_ui_read),
|
3653 |
|
|
.UIADD (mcb_ui_add) ,
|
3654 |
|
|
.UICS (mcb_ui_cs) ,
|
3655 |
|
|
.UICLK (mcb_ui_clk) ,
|
3656 |
|
|
.UISDI (mcb_ui_sdi) ,
|
3657 |
|
|
.UIADDR (mcb_ui_addr) ,
|
3658 |
|
|
.UIBROADCAST (mcb_ui_broadcast) ,
|
3659 |
|
|
.UIDRPUPDATE (mcb_ui_drp_update) ,
|
3660 |
|
|
.UIDONECAL (mcb_ui_done_cal) ,
|
3661 |
|
|
.UICMD (mcb_ui_cmd),
|
3662 |
|
|
.UICMDIN (mcb_ui_cmd_in) ,
|
3663 |
|
|
.UICMDEN (mcb_ui_cmd_en) ,
|
3664 |
|
|
.UIDQCOUNT (mcb_ui_dqcount) ,
|
3665 |
|
|
.UIDQLOWERDEC (mcb_ui_dq_lower_dec),
|
3666 |
|
|
.UIDQLOWERINC (mcb_ui_dq_lower_inc),
|
3667 |
|
|
.UIDQUPPERDEC (mcb_ui_dq_upper_dec),
|
3668 |
|
|
.UIDQUPPERINC (mcb_ui_dq_upper_inc),
|
3669 |
|
|
.UIUDQSDEC (mcb_ui_udqs_dec),
|
3670 |
|
|
.UIUDQSINC (mcb_ui_udqs_inc),
|
3671 |
|
|
.UILDQSDEC (mcb_ui_ldqs_dec),
|
3672 |
|
|
.UILDQSINC (mcb_ui_ldqs_inc),
|
3673 |
|
|
.UODATA (uo_data),
|
3674 |
|
|
.UODATAVALID (uo_data_valid),
|
3675 |
|
|
.UODONECAL (hard_done_cal) ,
|
3676 |
|
|
.UOCMDREADYIN (uo_cmd_ready_in),
|
3677 |
|
|
.UOREFRSHFLAG (uo_refrsh_flag),
|
3678 |
|
|
.UOCALSTART (uo_cal_start) ,
|
3679 |
|
|
.UOSDO (uo_sdo),
|
3680 |
|
|
|
3681 |
|
|
//CONTROL SIGNALS
|
3682 |
|
|
.STATUS (status),
|
3683 |
|
|
.SELFREFRESHENTER (selfrefresh_mcb_enter ),
|
3684 |
|
|
.SELFREFRESHMODE (selfrefresh_mcb_mode ),
|
3685 |
|
|
////////////////////////////// //////////////////
|
3686 |
|
|
//MUIs
|
3687 |
|
|
////////////////////////////////////////////////
|
3688 |
|
|
|
3689 |
|
|
.P0RDDATA ( mig_p0_rd_data[31:0] ),
|
3690 |
|
|
.P1RDDATA ( mig_p1_rd_data[31:0] ),
|
3691 |
|
|
.P2RDDATA ( mig_p2_rd_data[31:0] ),
|
3692 |
|
|
.P3RDDATA ( mig_p3_rd_data[31:0] ),
|
3693 |
|
|
.P4RDDATA ( mig_p4_rd_data[31:0] ),
|
3694 |
|
|
.P5RDDATA ( mig_p5_rd_data[31:0] ),
|
3695 |
|
|
.LDMN ( dqnlm ),
|
3696 |
|
|
.UDMN ( dqnum ),
|
3697 |
|
|
.DQON ( dqo_n ),
|
3698 |
|
|
.DQOP ( dqo_p ),
|
3699 |
|
|
.LDMP ( dqplm ),
|
3700 |
|
|
.UDMP ( dqpum ),
|
3701 |
|
|
|
3702 |
|
|
.P0RDCOUNT ( mig_p0_rd_count ),
|
3703 |
|
|
.P0WRCOUNT ( mig_p0_wr_count ),
|
3704 |
|
|
.P1RDCOUNT ( mig_p1_rd_count ),
|
3705 |
|
|
.P1WRCOUNT ( mig_p1_wr_count ),
|
3706 |
|
|
.P2COUNT ( mig_p2_count ),
|
3707 |
|
|
.P3COUNT ( mig_p3_count ),
|
3708 |
|
|
.P4COUNT ( mig_p4_count ),
|
3709 |
|
|
.P5COUNT ( mig_p5_count ),
|
3710 |
|
|
|
3711 |
|
|
// NEW ADDED FIFo status siganls
|
3712 |
|
|
// MIG USER PORT 0
|
3713 |
|
|
.P0RDEMPTY ( mig_p0_rd_empty),
|
3714 |
|
|
.P0RDFULL ( mig_p0_rd_full),
|
3715 |
|
|
.P0RDOVERFLOW ( mig_p0_rd_overflow),
|
3716 |
|
|
.P0WREMPTY ( mig_p0_wr_empty),
|
3717 |
|
|
.P0WRFULL ( mig_p0_wr_full),
|
3718 |
|
|
.P0WRUNDERRUN ( mig_p0_wr_underrun),
|
3719 |
|
|
// MIG USER PORT 1
|
3720 |
|
|
.P1RDEMPTY ( mig_p1_rd_empty),
|
3721 |
|
|
.P1RDFULL ( mig_p1_rd_full),
|
3722 |
|
|
.P1RDOVERFLOW ( mig_p1_rd_overflow),
|
3723 |
|
|
.P1WREMPTY ( mig_p1_wr_empty),
|
3724 |
|
|
.P1WRFULL ( mig_p1_wr_full),
|
3725 |
|
|
.P1WRUNDERRUN ( mig_p1_wr_underrun),
|
3726 |
|
|
|
3727 |
|
|
// MIG USER PORT 2
|
3728 |
|
|
.P2EMPTY ( mig_p2_empty),
|
3729 |
|
|
.P2FULL ( mig_p2_full),
|
3730 |
|
|
.P2RDOVERFLOW ( mig_p2_overflow),
|
3731 |
|
|
.P2WRUNDERRUN ( mig_p2_underrun),
|
3732 |
|
|
|
3733 |
|
|
.P3EMPTY ( mig_p3_empty ),
|
3734 |
|
|
.P3FULL ( mig_p3_full ),
|
3735 |
|
|
.P3RDOVERFLOW ( mig_p3_overflow),
|
3736 |
|
|
.P3WRUNDERRUN ( mig_p3_underrun ),
|
3737 |
|
|
// MIG USER PORT 3
|
3738 |
|
|
.P4EMPTY ( mig_p4_empty),
|
3739 |
|
|
.P4FULL ( mig_p4_full),
|
3740 |
|
|
.P4RDOVERFLOW ( mig_p4_overflow),
|
3741 |
|
|
.P4WRUNDERRUN ( mig_p4_underrun),
|
3742 |
|
|
|
3743 |
|
|
.P5EMPTY ( mig_p5_empty ),
|
3744 |
|
|
.P5FULL ( mig_p5_full ),
|
3745 |
|
|
.P5RDOVERFLOW ( mig_p5_overflow),
|
3746 |
|
|
.P5WRUNDERRUN ( mig_p5_underrun),
|
3747 |
|
|
|
3748 |
|
|
////////////////////////////////////////////////////////-
|
3749 |
|
|
.P0WREN ( mig_p0_wr_en),
|
3750 |
|
|
.P0RDEN ( mig_p0_rd_en),
|
3751 |
|
|
.P1WREN ( mig_p1_wr_en),
|
3752 |
|
|
.P1RDEN ( mig_p1_rd_en),
|
3753 |
|
|
.P2EN ( mig_p2_en),
|
3754 |
|
|
.P3EN ( mig_p3_en),
|
3755 |
|
|
.P4EN ( mig_p4_en),
|
3756 |
|
|
.P5EN ( mig_p5_en),
|
3757 |
|
|
// WRITE MASK BIts connection
|
3758 |
|
|
.P0RWRMASK ( mig_p0_wr_mask[3:0]),
|
3759 |
|
|
.P1RWRMASK ( mig_p1_wr_mask[3:0]),
|
3760 |
|
|
.P2WRMASK ( mig_p2_wr_mask[3:0]),
|
3761 |
|
|
.P3WRMASK ( mig_p3_wr_mask[3:0]),
|
3762 |
|
|
.P4WRMASK ( mig_p4_wr_mask[3:0]),
|
3763 |
|
|
.P5WRMASK ( mig_p5_wr_mask[3:0]),
|
3764 |
|
|
// DATA WRITE COnnection
|
3765 |
|
|
.P0WRDATA ( mig_p0_wr_data[31:0]),
|
3766 |
|
|
.P1WRDATA ( mig_p1_wr_data[31:0]),
|
3767 |
|
|
.P2WRDATA ( mig_p2_wr_data[31:0]),
|
3768 |
|
|
.P3WRDATA ( mig_p3_wr_data[31:0]),
|
3769 |
|
|
.P4WRDATA ( mig_p4_wr_data[31:0]),
|
3770 |
|
|
.P5WRDATA ( mig_p5_wr_data[31:0]),
|
3771 |
|
|
|
3772 |
|
|
.P0WRERROR (mig_p0_wr_error),
|
3773 |
|
|
.P1WRERROR (mig_p1_wr_error),
|
3774 |
|
|
.P0RDERROR (mig_p0_rd_error),
|
3775 |
|
|
.P1RDERROR (mig_p1_rd_error),
|
3776 |
|
|
|
3777 |
|
|
.P2ERROR (mig_p2_error),
|
3778 |
|
|
.P3ERROR (mig_p3_error),
|
3779 |
|
|
.P4ERROR (mig_p4_error),
|
3780 |
|
|
.P5ERROR (mig_p5_error),
|
3781 |
|
|
|
3782 |
|
|
// USER SIDE DAta ports clock
|
3783 |
|
|
// 128 BITS CONnections
|
3784 |
|
|
.P0WRCLK ( mig_p0_wr_clk ),
|
3785 |
|
|
.P1WRCLK ( mig_p1_wr_clk ),
|
3786 |
|
|
.P0RDCLK ( mig_p0_rd_clk ),
|
3787 |
|
|
.P1RDCLK ( mig_p1_rd_clk ),
|
3788 |
|
|
.P2CLK ( mig_p2_clk ),
|
3789 |
|
|
.P3CLK ( mig_p3_clk ),
|
3790 |
|
|
.P4CLK ( mig_p4_clk ),
|
3791 |
|
|
.P5CLK ( mig_p5_clk)
|
3792 |
|
|
////////////////////////////////////////////////////////
|
3793 |
|
|
// TST MODE PINS
|
3794 |
|
|
|
3795 |
|
|
|
3796 |
|
|
|
3797 |
|
|
);
|
3798 |
|
|
|
3799 |
|
|
|
3800 |
|
|
//////////////////////////////////////////////////////
|
3801 |
|
|
// Input Termination Calibration
|
3802 |
|
|
//////////////////////////////////////////////////////
|
3803 |
|
|
wire DONE_SOFTANDHARD_CAL;
|
3804 |
|
|
|
3805 |
|
|
assign uo_done_cal = ( C_CALIB_SOFT_IP == "TRUE") ? DONE_SOFTANDHARD_CAL : hard_done_cal;
|
3806 |
|
|
generate
|
3807 |
|
|
if ( C_CALIB_SOFT_IP == "TRUE") begin: gen_term_calib
|
3808 |
|
|
|
3809 |
|
|
|
3810 |
|
|
|
3811 |
|
|
|
3812 |
|
|
|
3813 |
|
|
mcb_soft_calibration_top # (
|
3814 |
|
|
|
3815 |
|
|
.C_MEM_TZQINIT_MAXCNT (C_MEM_TZQINIT_MAXCNT),
|
3816 |
|
|
.C_MC_CALIBRATION_MODE(C_MC_CALIBRATION_MODE),
|
3817 |
|
|
.SKIP_IN_TERM_CAL (C_SKIP_IN_TERM_CAL),
|
3818 |
|
|
.SKIP_DYNAMIC_CAL (C_SKIP_DYNAMIC_CAL),
|
3819 |
|
|
.SKIP_DYN_IN_TERM (C_SKIP_DYN_IN_TERM),
|
3820 |
|
|
.C_SIMULATION (C_SIMULATION),
|
3821 |
|
|
.C_MEM_TYPE (C_MEM_TYPE)
|
3822 |
|
|
)
|
3823 |
|
|
mcb_soft_calibration_top_inst (
|
3824 |
|
|
.UI_CLK (ui_clk), //Input - global clock to be used for input_term_tuner and IODRP clock
|
3825 |
|
|
.RST (int_sys_rst), //Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for IODRP (sub)controller
|
3826 |
|
|
.IOCLK (ioclk0), //Input - IOCLK input to the IODRP's
|
3827 |
|
|
.DONE_SOFTANDHARD_CAL (DONE_SOFTANDHARD_CAL), // active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB hard calib complete)
|
3828 |
|
|
.PLL_LOCK (pll_lock),
|
3829 |
|
|
|
3830 |
|
|
.SELFREFRESH_REQ (selfrefresh_enter), // from user app
|
3831 |
|
|
.SELFREFRESH_MCB_MODE (selfrefresh_mcb_mode), // from MCB
|
3832 |
|
|
.SELFREFRESH_MCB_REQ (selfrefresh_mcb_enter),// to mcb
|
3833 |
|
|
.SELFREFRESH_MODE (selfrefresh_mode), // to user app
|
3834 |
|
|
|
3835 |
|
|
|
3836 |
|
|
|
3837 |
|
|
.MCB_UIADD (mcb_ui_add),
|
3838 |
|
|
.MCB_UISDI (mcb_ui_sdi),
|
3839 |
|
|
.MCB_UOSDO (uo_sdo), // from MCB's UOSDO port (User output SDO)
|
3840 |
|
|
.MCB_UODONECAL (hard_done_cal), // input for when MCB hard calibration process is complete
|
3841 |
|
|
.MCB_UOREFRSHFLAG (uo_refrsh_flag), //high during refresh cycle and time when MCB is innactive
|
3842 |
|
|
.MCB_UICS (mcb_ui_cs), // to MCB's UICS port (User Input CS)
|
3843 |
|
|
.MCB_UIDRPUPDATE (mcb_ui_drp_update), // MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used during IODRP2_MCB writes). Currently just trasnparent
|
3844 |
|
|
.MCB_UIBROADCAST (mcb_ui_broadcast), // to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
|
3845 |
|
|
.MCB_UIADDR (mcb_ui_addr), //to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
|
3846 |
|
|
.MCB_UICMDEN (mcb_ui_cmd_en), //set to take control of UI interface - removes control from internal calib block
|
3847 |
|
|
.MCB_UIDONECAL (mcb_ui_done_cal), //
|
3848 |
|
|
.MCB_UIDQLOWERDEC (mcb_ui_dq_lower_dec),
|
3849 |
|
|
.MCB_UIDQLOWERINC (mcb_ui_dq_lower_inc),
|
3850 |
|
|
.MCB_UIDQUPPERDEC (mcb_ui_dq_upper_dec),
|
3851 |
|
|
.MCB_UIDQUPPERINC (mcb_ui_dq_upper_inc),
|
3852 |
|
|
.MCB_UILDQSDEC (mcb_ui_ldqs_dec),
|
3853 |
|
|
.MCB_UILDQSINC (mcb_ui_ldqs_inc),
|
3854 |
|
|
.MCB_UIREAD (mcb_ui_read), //enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
|
3855 |
|
|
.MCB_UIUDQSDEC (mcb_ui_udqs_dec),
|
3856 |
|
|
.MCB_UIUDQSINC (mcb_ui_udqs_inc),
|
3857 |
|
|
.MCB_RECAL (mcb_recal),
|
3858 |
|
|
.MCB_SYSRST (MCB_SYSRST), //drives the MCB's SYSRST pin - the main reset for MCB
|
3859 |
|
|
.MCB_UICMD (mcb_ui_cmd),
|
3860 |
|
|
.MCB_UICMDIN (mcb_ui_cmd_in),
|
3861 |
|
|
.MCB_UIDQCOUNT (mcb_ui_dqcount),
|
3862 |
|
|
.MCB_UODATA (uo_data),
|
3863 |
|
|
.MCB_UODATAVALID (uo_data_valid),
|
3864 |
|
|
.MCB_UOCMDREADY (uo_cmd_ready_in),
|
3865 |
|
|
.MCB_UO_CAL_START (uo_cal_start),
|
3866 |
|
|
.RZQ_Pin (rzq),
|
3867 |
|
|
.ZIO_Pin (zio),
|
3868 |
|
|
.CKE_Train (cke_train)
|
3869 |
|
|
|
3870 |
|
|
);
|
3871 |
|
|
|
3872 |
|
|
|
3873 |
|
|
|
3874 |
|
|
|
3875 |
|
|
|
3876 |
|
|
|
3877 |
|
|
assign mcb_ui_clk = ui_clk;
|
3878 |
|
|
end
|
3879 |
|
|
endgenerate
|
3880 |
|
|
|
3881 |
|
|
generate
|
3882 |
|
|
if ( C_CALIB_SOFT_IP != "TRUE") begin: gen_no_term_calib
|
3883 |
|
|
assign DONE_SOFTANDHARD_CAL = 1'b0;
|
3884 |
|
|
assign MCB_SYSRST = int_sys_rst | (~wait_200us_counter[15]);
|
3885 |
|
|
assign mcb_recal = calib_recal;
|
3886 |
|
|
assign mcb_ui_read = ui_read;
|
3887 |
|
|
assign mcb_ui_add = ui_add;
|
3888 |
|
|
assign mcb_ui_cs = ui_cs;
|
3889 |
|
|
assign mcb_ui_clk = ui_clk;
|
3890 |
|
|
assign mcb_ui_sdi = ui_sdi;
|
3891 |
|
|
assign mcb_ui_addr = ui_addr;
|
3892 |
|
|
assign mcb_ui_broadcast = ui_broadcast;
|
3893 |
|
|
assign mcb_ui_drp_update = ui_drp_update;
|
3894 |
|
|
assign mcb_ui_done_cal = ui_done_cal;
|
3895 |
|
|
assign mcb_ui_cmd = ui_cmd;
|
3896 |
|
|
assign mcb_ui_cmd_in = ui_cmd_in;
|
3897 |
|
|
assign mcb_ui_cmd_en = ui_cmd_en;
|
3898 |
|
|
assign mcb_ui_dq_lower_dec = ui_dq_lower_dec;
|
3899 |
|
|
assign mcb_ui_dq_lower_inc = ui_dq_lower_inc;
|
3900 |
|
|
assign mcb_ui_dq_upper_dec = ui_dq_upper_dec;
|
3901 |
|
|
assign mcb_ui_dq_upper_inc = ui_dq_upper_inc;
|
3902 |
|
|
assign mcb_ui_udqs_inc = ui_udqs_inc;
|
3903 |
|
|
assign mcb_ui_udqs_dec = ui_udqs_dec;
|
3904 |
|
|
assign mcb_ui_ldqs_inc = ui_ldqs_inc;
|
3905 |
|
|
assign mcb_ui_ldqs_dec = ui_ldqs_dec;
|
3906 |
|
|
assign selfrefresh_mode = 1'b0;
|
3907 |
|
|
|
3908 |
|
|
if (C_SIMULATION == "FALSE") begin: init_sequence
|
3909 |
|
|
always @ (posedge ui_clk, posedge int_sys_rst)
|
3910 |
|
|
begin
|
3911 |
|
|
if (int_sys_rst)
|
3912 |
|
|
wait_200us_counter <= 'b0;
|
3913 |
|
|
else
|
3914 |
|
|
if (wait_200us_counter[15]) // UI_CLK maximum is up to 100 MHz.
|
3915 |
|
|
wait_200us_counter <= wait_200us_counter ;
|
3916 |
|
|
else
|
3917 |
|
|
wait_200us_counter <= wait_200us_counter + 1'b1;
|
3918 |
|
|
end
|
3919 |
|
|
end
|
3920 |
|
|
else begin: init_sequence_skip
|
3921 |
|
|
// synthesis translate_off
|
3922 |
|
|
initial
|
3923 |
|
|
begin
|
3924 |
|
|
wait_200us_counter = 16'hFFFF;
|
3925 |
|
|
$display("The 200 us wait period required before CKE goes active has been skipped in Simulation\n");
|
3926 |
|
|
end
|
3927 |
|
|
// synthesis translate_on
|
3928 |
|
|
end
|
3929 |
|
|
|
3930 |
|
|
|
3931 |
|
|
if( C_MEM_TYPE == "DDR2") begin : gen_cketrain_a
|
3932 |
|
|
|
3933 |
|
|
always @ ( posedge ui_clk)
|
3934 |
|
|
begin
|
3935 |
|
|
// When wait_200us_[13] and wait_200us_[14] are both asserted,
|
3936 |
|
|
// 200 us wait should have been passed.
|
3937 |
|
|
if (wait_200us_counter[14] && wait_200us_counter[13])
|
3938 |
|
|
wait_200us_done_r1 <= 1'b1;
|
3939 |
|
|
else
|
3940 |
|
|
wait_200us_done_r1 <= 1'b0;
|
3941 |
|
|
|
3942 |
|
|
|
3943 |
|
|
wait_200us_done_r2 <= wait_200us_done_r1;
|
3944 |
|
|
end
|
3945 |
|
|
|
3946 |
|
|
always @ ( posedge ui_clk, posedge int_sys_rst)
|
3947 |
|
|
begin
|
3948 |
|
|
if (int_sys_rst)
|
3949 |
|
|
cke_train_reg <= 1'b0;
|
3950 |
|
|
else
|
3951 |
|
|
if ( wait_200us_done_r1 && ~wait_200us_done_r2 )
|
3952 |
|
|
cke_train_reg <= 1'b1;
|
3953 |
|
|
else if ( uo_done_cal)
|
3954 |
|
|
cke_train_reg <= 1'b0;
|
3955 |
|
|
end
|
3956 |
|
|
|
3957 |
|
|
assign cke_train = cke_train_reg;
|
3958 |
|
|
end
|
3959 |
|
|
|
3960 |
|
|
if( C_MEM_TYPE != "DDR2") begin : gen_cketrain_b
|
3961 |
|
|
|
3962 |
|
|
assign cke_train = 1'b0;
|
3963 |
|
|
end
|
3964 |
|
|
|
3965 |
|
|
|
3966 |
|
|
end
|
3967 |
|
|
endgenerate
|
3968 |
|
|
|
3969 |
|
|
//////////////////////////////////////////////////////
|
3970 |
|
|
//ODDRDES2 instantiations
|
3971 |
|
|
//////////////////////////////////////////////////////
|
3972 |
|
|
|
3973 |
|
|
////////
|
3974 |
|
|
//ADDR
|
3975 |
|
|
////////
|
3976 |
|
|
|
3977 |
|
|
genvar addr_ioi;
|
3978 |
|
|
generate
|
3979 |
|
|
for(addr_ioi = 0; addr_ioi < C_MEM_ADDR_WIDTH; addr_ioi = addr_ioi + 1) begin : gen_addr_oserdes2
|
3980 |
|
|
OSERDES2 #(
|
3981 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
3982 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
3983 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
3984 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
3985 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE
|
3986 |
|
|
.DATA_WIDTH (2) // {1..8}
|
3987 |
|
|
) ioi_addr_0
|
3988 |
|
|
(
|
3989 |
|
|
.OQ(ioi_addr[addr_ioi]),
|
3990 |
|
|
.SHIFTOUT1(),
|
3991 |
|
|
.SHIFTOUT2(),
|
3992 |
|
|
.SHIFTOUT3(),
|
3993 |
|
|
.SHIFTOUT4(),
|
3994 |
|
|
.TQ(t_addr[addr_ioi]),
|
3995 |
|
|
.CLK0(ioclk0),
|
3996 |
|
|
.CLK1(),
|
3997 |
|
|
.CLKDIV(),
|
3998 |
|
|
.D1(address_90[addr_ioi]),
|
3999 |
|
|
.D2(address_90[addr_ioi]),
|
4000 |
|
|
.D3(),
|
4001 |
|
|
.D4(),
|
4002 |
|
|
.IOCE(pll_ce_0),
|
4003 |
|
|
.OCE(1'b1),
|
4004 |
|
|
.RST(int_sys_rst),
|
4005 |
|
|
.SHIFTIN1(),
|
4006 |
|
|
.SHIFTIN2(),
|
4007 |
|
|
.SHIFTIN3(),
|
4008 |
|
|
.SHIFTIN4(),
|
4009 |
|
|
.T1(1'b0),
|
4010 |
|
|
.T2(1'b0),
|
4011 |
|
|
.T3(),
|
4012 |
|
|
.T4(),
|
4013 |
|
|
.TCE(1'b1),
|
4014 |
|
|
.TRAIN(1'b0)
|
4015 |
|
|
);
|
4016 |
|
|
end
|
4017 |
|
|
endgenerate
|
4018 |
|
|
|
4019 |
|
|
////////
|
4020 |
|
|
//BA
|
4021 |
|
|
////////
|
4022 |
|
|
|
4023 |
|
|
genvar ba_ioi;
|
4024 |
|
|
generate
|
4025 |
|
|
for(ba_ioi = 0; ba_ioi < C_MEM_BANKADDR_WIDTH; ba_ioi = ba_ioi + 1) begin : gen_ba_oserdes2
|
4026 |
|
|
OSERDES2 #(
|
4027 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
4028 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
4029 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
4030 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
4031 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE
|
4032 |
|
|
.DATA_WIDTH (2) // {1..8}
|
4033 |
|
|
) ioi_ba_0
|
4034 |
|
|
(
|
4035 |
|
|
.OQ (ioi_ba[ba_ioi]),
|
4036 |
|
|
.SHIFTOUT1 (),
|
4037 |
|
|
.SHIFTOUT2 (),
|
4038 |
|
|
.SHIFTOUT3 (),
|
4039 |
|
|
.SHIFTOUT4 (),
|
4040 |
|
|
.TQ (t_ba[ba_ioi]),
|
4041 |
|
|
.CLK0 (ioclk0),
|
4042 |
|
|
.CLK1 (),
|
4043 |
|
|
.CLKDIV (),
|
4044 |
|
|
.D1 (ba_90[ba_ioi]),
|
4045 |
|
|
.D2 (ba_90[ba_ioi]),
|
4046 |
|
|
.D3 (),
|
4047 |
|
|
.D4 (),
|
4048 |
|
|
.IOCE (pll_ce_0),
|
4049 |
|
|
.OCE (1'b1),
|
4050 |
|
|
.RST (int_sys_rst),
|
4051 |
|
|
.SHIFTIN1 (),
|
4052 |
|
|
.SHIFTIN2 (),
|
4053 |
|
|
.SHIFTIN3 (),
|
4054 |
|
|
.SHIFTIN4 (),
|
4055 |
|
|
.T1(1'b0),
|
4056 |
|
|
.T2(1'b0),
|
4057 |
|
|
.T3(),
|
4058 |
|
|
.T4(),
|
4059 |
|
|
.TCE(1'b1),
|
4060 |
|
|
.TRAIN (1'b0)
|
4061 |
|
|
);
|
4062 |
|
|
end
|
4063 |
|
|
endgenerate
|
4064 |
|
|
|
4065 |
|
|
////////
|
4066 |
|
|
//CAS
|
4067 |
|
|
////////
|
4068 |
|
|
|
4069 |
|
|
OSERDES2 #(
|
4070 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
4071 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
4072 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
4073 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
4074 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE
|
4075 |
|
|
.DATA_WIDTH (2) // {1..8}
|
4076 |
|
|
) ioi_cas_0
|
4077 |
|
|
(
|
4078 |
|
|
.OQ (ioi_cas),
|
4079 |
|
|
.SHIFTOUT1 (),
|
4080 |
|
|
.SHIFTOUT2 (),
|
4081 |
|
|
.SHIFTOUT3 (),
|
4082 |
|
|
.SHIFTOUT4 (),
|
4083 |
|
|
.TQ (t_cas),
|
4084 |
|
|
.CLK0 (ioclk0),
|
4085 |
|
|
.CLK1 (),
|
4086 |
|
|
.CLKDIV (),
|
4087 |
|
|
.D1 (cas_90),
|
4088 |
|
|
.D2 (cas_90),
|
4089 |
|
|
.D3 (),
|
4090 |
|
|
.D4 (),
|
4091 |
|
|
.IOCE (pll_ce_0),
|
4092 |
|
|
.OCE (1'b1),
|
4093 |
|
|
.RST (int_sys_rst),
|
4094 |
|
|
.SHIFTIN1 (),
|
4095 |
|
|
.SHIFTIN2 (),
|
4096 |
|
|
.SHIFTIN3 (),
|
4097 |
|
|
.SHIFTIN4 (),
|
4098 |
|
|
.T1(1'b0),
|
4099 |
|
|
.T2(1'b0),
|
4100 |
|
|
.T3(),
|
4101 |
|
|
.T4(),
|
4102 |
|
|
.TCE(1'b1),
|
4103 |
|
|
.TRAIN (1'b0)
|
4104 |
|
|
);
|
4105 |
|
|
|
4106 |
|
|
////////
|
4107 |
|
|
//CKE
|
4108 |
|
|
////////
|
4109 |
|
|
|
4110 |
|
|
OSERDES2 #(
|
4111 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
4112 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
4113 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
4114 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
4115 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE
|
4116 |
|
|
.DATA_WIDTH (2) , // {1..8}
|
4117 |
|
|
.TRAIN_PATTERN (15)
|
4118 |
|
|
) ioi_cke_0
|
4119 |
|
|
(
|
4120 |
|
|
.OQ (ioi_cke),
|
4121 |
|
|
.SHIFTOUT1 (),
|
4122 |
|
|
.SHIFTOUT2 (),
|
4123 |
|
|
.SHIFTOUT3 (),
|
4124 |
|
|
.SHIFTOUT4 (),
|
4125 |
|
|
.TQ (t_cke),
|
4126 |
|
|
.CLK0 (ioclk0),
|
4127 |
|
|
.CLK1 (),
|
4128 |
|
|
.CLKDIV (),
|
4129 |
|
|
.D1 (cke_90),
|
4130 |
|
|
.D2 (cke_90),
|
4131 |
|
|
.D3 (),
|
4132 |
|
|
.D4 (),
|
4133 |
|
|
.IOCE (pll_ce_0),
|
4134 |
|
|
.OCE (1'b1),
|
4135 |
|
|
.RST (1'b0),//int_sys_rst
|
4136 |
|
|
.SHIFTIN1 (),
|
4137 |
|
|
.SHIFTIN2 (),
|
4138 |
|
|
.SHIFTIN3 (),
|
4139 |
|
|
.SHIFTIN4 (),
|
4140 |
|
|
.T1(1'b0),
|
4141 |
|
|
.T2(1'b0),
|
4142 |
|
|
.T3(),
|
4143 |
|
|
.T4(),
|
4144 |
|
|
.TCE(1'b1),
|
4145 |
|
|
.TRAIN (cke_train)
|
4146 |
|
|
);
|
4147 |
|
|
|
4148 |
|
|
////////
|
4149 |
|
|
//ODT
|
4150 |
|
|
////////
|
4151 |
|
|
generate
|
4152 |
|
|
if(C_MEM_TYPE == "DDR3" || C_MEM_TYPE == "DDR2" ) begin : gen_ioi_odt
|
4153 |
|
|
|
4154 |
|
|
OSERDES2 #(
|
4155 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
4156 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
4157 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
4158 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
4159 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE
|
4160 |
|
|
.DATA_WIDTH (2) // {1..8}
|
4161 |
|
|
) ioi_odt_0
|
4162 |
|
|
(
|
4163 |
|
|
.OQ (ioi_odt),
|
4164 |
|
|
.SHIFTOUT1 (),
|
4165 |
|
|
.SHIFTOUT2 (),
|
4166 |
|
|
.SHIFTOUT3 (),
|
4167 |
|
|
.SHIFTOUT4 (),
|
4168 |
|
|
.TQ (t_odt),
|
4169 |
|
|
.CLK0 (ioclk0),
|
4170 |
|
|
.CLK1 (),
|
4171 |
|
|
.CLKDIV (),
|
4172 |
|
|
.D1 (odt_90),
|
4173 |
|
|
.D2 (odt_90),
|
4174 |
|
|
.D3 (),
|
4175 |
|
|
.D4 (),
|
4176 |
|
|
.IOCE (pll_ce_0),
|
4177 |
|
|
.OCE (1'b1),
|
4178 |
|
|
.RST (int_sys_rst),
|
4179 |
|
|
.SHIFTIN1 (),
|
4180 |
|
|
.SHIFTIN2 (),
|
4181 |
|
|
.SHIFTIN3 (),
|
4182 |
|
|
.SHIFTIN4 (),
|
4183 |
|
|
.T1(1'b0),
|
4184 |
|
|
.T2(1'b0),
|
4185 |
|
|
.T3(),
|
4186 |
|
|
.T4(),
|
4187 |
|
|
.TCE(1'b1),
|
4188 |
|
|
.TRAIN (1'b0)
|
4189 |
|
|
);
|
4190 |
|
|
end
|
4191 |
|
|
endgenerate
|
4192 |
|
|
////////
|
4193 |
|
|
//RAS
|
4194 |
|
|
////////
|
4195 |
|
|
|
4196 |
|
|
OSERDES2 #(
|
4197 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
4198 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
4199 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
4200 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
4201 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE
|
4202 |
|
|
.DATA_WIDTH (2) // {1..8}
|
4203 |
|
|
) ioi_ras_0
|
4204 |
|
|
(
|
4205 |
|
|
.OQ (ioi_ras),
|
4206 |
|
|
.SHIFTOUT1 (),
|
4207 |
|
|
.SHIFTOUT2 (),
|
4208 |
|
|
.SHIFTOUT3 (),
|
4209 |
|
|
.SHIFTOUT4 (),
|
4210 |
|
|
.TQ (t_ras),
|
4211 |
|
|
.CLK0 (ioclk0),
|
4212 |
|
|
.CLK1 (),
|
4213 |
|
|
.CLKDIV (),
|
4214 |
|
|
.D1 (ras_90),
|
4215 |
|
|
.D2 (ras_90),
|
4216 |
|
|
.D3 (),
|
4217 |
|
|
.D4 (),
|
4218 |
|
|
.IOCE (pll_ce_0),
|
4219 |
|
|
.OCE (1'b1),
|
4220 |
|
|
.RST (int_sys_rst),
|
4221 |
|
|
.SHIFTIN1 (),
|
4222 |
|
|
.SHIFTIN2 (),
|
4223 |
|
|
.SHIFTIN3 (),
|
4224 |
|
|
.SHIFTIN4 (),
|
4225 |
|
|
.T1 (1'b0),
|
4226 |
|
|
.T2 (1'b0),
|
4227 |
|
|
.T3 (),
|
4228 |
|
|
.T4 (),
|
4229 |
|
|
.TCE (1'b1),
|
4230 |
|
|
.TRAIN (1'b0)
|
4231 |
|
|
);
|
4232 |
|
|
|
4233 |
|
|
////////
|
4234 |
|
|
//RST
|
4235 |
|
|
////////
|
4236 |
|
|
generate
|
4237 |
|
|
if (C_MEM_TYPE == "DDR3" ) begin : gen_ioi_rst
|
4238 |
|
|
|
4239 |
|
|
OSERDES2 #(
|
4240 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
4241 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
4242 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
4243 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
4244 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE
|
4245 |
|
|
.DATA_WIDTH (2) // {1..8}
|
4246 |
|
|
) ioi_rst_0
|
4247 |
|
|
(
|
4248 |
|
|
.OQ (ioi_rst),
|
4249 |
|
|
.SHIFTOUT1 (),
|
4250 |
|
|
.SHIFTOUT2 (),
|
4251 |
|
|
.SHIFTOUT3 (),
|
4252 |
|
|
.SHIFTOUT4 (),
|
4253 |
|
|
.TQ (t_rst),
|
4254 |
|
|
.CLK0 (ioclk0),
|
4255 |
|
|
.CLK1 (),
|
4256 |
|
|
.CLKDIV (),
|
4257 |
|
|
.D1 (rst_90),
|
4258 |
|
|
.D2 (rst_90),
|
4259 |
|
|
.D3 (),
|
4260 |
|
|
.D4 (),
|
4261 |
|
|
.IOCE (pll_ce_0),
|
4262 |
|
|
.OCE (1'b1),
|
4263 |
|
|
.RST (int_sys_rst),
|
4264 |
|
|
.SHIFTIN1 (),
|
4265 |
|
|
.SHIFTIN2 (),
|
4266 |
|
|
.SHIFTIN3 (),
|
4267 |
|
|
.SHIFTIN4 (),
|
4268 |
|
|
.T1(1'b0),
|
4269 |
|
|
.T2(1'b0),
|
4270 |
|
|
.T3(),
|
4271 |
|
|
.T4(),
|
4272 |
|
|
.TCE(1'b1),
|
4273 |
|
|
.TRAIN (1'b0)
|
4274 |
|
|
);
|
4275 |
|
|
end
|
4276 |
|
|
endgenerate
|
4277 |
|
|
////////
|
4278 |
|
|
//WE
|
4279 |
|
|
////////
|
4280 |
|
|
|
4281 |
|
|
OSERDES2 #(
|
4282 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
4283 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
4284 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
4285 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
4286 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE
|
4287 |
|
|
.DATA_WIDTH (2) // {1..8}
|
4288 |
|
|
) ioi_we_0
|
4289 |
|
|
(
|
4290 |
|
|
.OQ (ioi_we),
|
4291 |
|
|
.TQ (t_we),
|
4292 |
|
|
.SHIFTOUT1 (),
|
4293 |
|
|
.SHIFTOUT2 (),
|
4294 |
|
|
.SHIFTOUT3 (),
|
4295 |
|
|
.SHIFTOUT4 (),
|
4296 |
|
|
.CLK0 (ioclk0),
|
4297 |
|
|
.CLK1 (),
|
4298 |
|
|
.CLKDIV (),
|
4299 |
|
|
.D1 (we_90),
|
4300 |
|
|
.D2 (we_90),
|
4301 |
|
|
.D3 (),
|
4302 |
|
|
.D4 (),
|
4303 |
|
|
.IOCE (pll_ce_0),
|
4304 |
|
|
.OCE (1'b1),
|
4305 |
|
|
.RST (int_sys_rst),
|
4306 |
|
|
.SHIFTIN1 (),
|
4307 |
|
|
.SHIFTIN2 (),
|
4308 |
|
|
.SHIFTIN3 (),
|
4309 |
|
|
.SHIFTIN4 (),
|
4310 |
|
|
.T1(1'b0),
|
4311 |
|
|
.T2(1'b0),
|
4312 |
|
|
.T3(),
|
4313 |
|
|
.T4(),
|
4314 |
|
|
.TCE(1'b1),
|
4315 |
|
|
.TRAIN (1'b0)
|
4316 |
|
|
);
|
4317 |
|
|
|
4318 |
|
|
////////
|
4319 |
|
|
//CK
|
4320 |
|
|
////////
|
4321 |
|
|
|
4322 |
|
|
OSERDES2 #(
|
4323 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
4324 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
4325 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
4326 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
4327 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE
|
4328 |
|
|
.DATA_WIDTH (2) // {1..8}
|
4329 |
|
|
) ioi_ck_0
|
4330 |
|
|
(
|
4331 |
|
|
.OQ (ioi_ck),
|
4332 |
|
|
.SHIFTOUT1(),
|
4333 |
|
|
.SHIFTOUT2(),
|
4334 |
|
|
.SHIFTOUT3(),
|
4335 |
|
|
.SHIFTOUT4(),
|
4336 |
|
|
.TQ (t_ck),
|
4337 |
|
|
.CLK0 (ioclk0),
|
4338 |
|
|
.CLK1(),
|
4339 |
|
|
.CLKDIV(),
|
4340 |
|
|
.D1 (1'b0),
|
4341 |
|
|
.D2 (1'b1),
|
4342 |
|
|
.D3(),
|
4343 |
|
|
.D4(),
|
4344 |
|
|
.IOCE (pll_ce_0),
|
4345 |
|
|
.OCE (1'b1),
|
4346 |
|
|
.RST (1'b0),//int_sys_rst
|
4347 |
|
|
.SHIFTIN1(),
|
4348 |
|
|
.SHIFTIN2(),
|
4349 |
|
|
.SHIFTIN3 (),
|
4350 |
|
|
.SHIFTIN4 (),
|
4351 |
|
|
.T1(1'b0),
|
4352 |
|
|
.T2(1'b0),
|
4353 |
|
|
.T3(),
|
4354 |
|
|
.T4(),
|
4355 |
|
|
.TCE(1'b1),
|
4356 |
|
|
.TRAIN (1'b0)
|
4357 |
|
|
);
|
4358 |
|
|
|
4359 |
|
|
////////
|
4360 |
|
|
//CKN
|
4361 |
|
|
////////
|
4362 |
|
|
/*
|
4363 |
|
|
OSERDES2 #(
|
4364 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
4365 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
4366 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
4367 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
4368 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_SLAVE), // MASTER, SLAVE
|
4369 |
|
|
.DATA_WIDTH (2) // {1..8}
|
4370 |
|
|
) ioi_ckn_0
|
4371 |
|
|
(
|
4372 |
|
|
.OQ (ioi_ckn),
|
4373 |
|
|
.SHIFTOUT1(),
|
4374 |
|
|
.SHIFTOUT2(),
|
4375 |
|
|
.SHIFTOUT3(),
|
4376 |
|
|
.SHIFTOUT4(),
|
4377 |
|
|
.TQ (t_ckn),
|
4378 |
|
|
.CLK0 (ioclk0),
|
4379 |
|
|
.CLK1(),
|
4380 |
|
|
.CLKDIV(),
|
4381 |
|
|
.D1 (1'b1),
|
4382 |
|
|
.D2 (1'b0),
|
4383 |
|
|
.D3(),
|
4384 |
|
|
.D4(),
|
4385 |
|
|
.IOCE (pll_ce_0),
|
4386 |
|
|
.OCE (1'b1),
|
4387 |
|
|
.RST (1'b0),//int_sys_rst
|
4388 |
|
|
.SHIFTIN1 (),
|
4389 |
|
|
.SHIFTIN2 (),
|
4390 |
|
|
.SHIFTIN3(),
|
4391 |
|
|
.SHIFTIN4(),
|
4392 |
|
|
.T1(1'b0),
|
4393 |
|
|
.T2(1'b0),
|
4394 |
|
|
.T3(),
|
4395 |
|
|
.T4(),
|
4396 |
|
|
.TCE(1'b1),
|
4397 |
|
|
.TRAIN (1'b0)
|
4398 |
|
|
);
|
4399 |
|
|
*/
|
4400 |
|
|
|
4401 |
|
|
////////
|
4402 |
|
|
//UDM
|
4403 |
|
|
////////
|
4404 |
|
|
|
4405 |
|
|
wire udm_oq;
|
4406 |
|
|
wire udm_t;
|
4407 |
|
|
OSERDES2 #(
|
4408 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
4409 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
4410 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
4411 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
4412 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE
|
4413 |
|
|
.DATA_WIDTH (2) // {1..8}
|
4414 |
|
|
) ioi_udm_0
|
4415 |
|
|
(
|
4416 |
|
|
.OQ (udm_oq),
|
4417 |
|
|
.SHIFTOUT1 (),
|
4418 |
|
|
.SHIFTOUT2 (),
|
4419 |
|
|
.SHIFTOUT3 (),
|
4420 |
|
|
.SHIFTOUT4 (),
|
4421 |
|
|
.TQ (udm_t),
|
4422 |
|
|
.CLK0 (ioclk90),
|
4423 |
|
|
.CLK1 (),
|
4424 |
|
|
.CLKDIV (),
|
4425 |
|
|
.D1 (dqpum),
|
4426 |
|
|
.D2 (dqnum),
|
4427 |
|
|
.D3 (),
|
4428 |
|
|
.D4 (),
|
4429 |
|
|
.IOCE (pll_ce_90),
|
4430 |
|
|
.OCE (1'b1),
|
4431 |
|
|
.RST (int_sys_rst),
|
4432 |
|
|
.SHIFTIN1 (),
|
4433 |
|
|
.SHIFTIN2 (),
|
4434 |
|
|
.SHIFTIN3 (),
|
4435 |
|
|
.SHIFTIN4 (),
|
4436 |
|
|
.T1 (dqIO_w_en_0),
|
4437 |
|
|
.T2 (dqIO_w_en_0),
|
4438 |
|
|
.T3 (),
|
4439 |
|
|
.T4 (),
|
4440 |
|
|
.TCE (1'b1),
|
4441 |
|
|
.TRAIN (1'b0)
|
4442 |
|
|
);
|
4443 |
|
|
|
4444 |
|
|
////////
|
4445 |
|
|
//LDM
|
4446 |
|
|
////////
|
4447 |
|
|
wire ldm_oq;
|
4448 |
|
|
wire ldm_t;
|
4449 |
|
|
OSERDES2 #(
|
4450 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
4451 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
4452 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
4453 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
4454 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE
|
4455 |
|
|
.DATA_WIDTH (2) // {1..8}
|
4456 |
|
|
) ioi_ldm_0
|
4457 |
|
|
(
|
4458 |
|
|
.OQ (ldm_oq),
|
4459 |
|
|
.SHIFTOUT1 (),
|
4460 |
|
|
.SHIFTOUT2 (),
|
4461 |
|
|
.SHIFTOUT3 (),
|
4462 |
|
|
.SHIFTOUT4 (),
|
4463 |
|
|
.TQ (ldm_t),
|
4464 |
|
|
.CLK0 (ioclk90),
|
4465 |
|
|
.CLK1 (),
|
4466 |
|
|
.CLKDIV (),
|
4467 |
|
|
.D1 (dqplm),
|
4468 |
|
|
.D2 (dqnlm),
|
4469 |
|
|
.D3 (),
|
4470 |
|
|
.D4 (),
|
4471 |
|
|
.IOCE (pll_ce_90),
|
4472 |
|
|
.OCE (1'b1),
|
4473 |
|
|
.RST (int_sys_rst),
|
4474 |
|
|
.SHIFTIN1 (),
|
4475 |
|
|
.SHIFTIN2 (),
|
4476 |
|
|
.SHIFTIN3 (),
|
4477 |
|
|
.SHIFTIN4 (),
|
4478 |
|
|
.T1 (dqIO_w_en_0),
|
4479 |
|
|
.T2 (dqIO_w_en_0),
|
4480 |
|
|
.T3 (),
|
4481 |
|
|
.T4 (),
|
4482 |
|
|
.TCE (1'b1),
|
4483 |
|
|
.TRAIN (1'b0)
|
4484 |
|
|
);
|
4485 |
|
|
|
4486 |
|
|
////////
|
4487 |
|
|
//DQ
|
4488 |
|
|
////////
|
4489 |
|
|
|
4490 |
|
|
wire dq_oq [C_NUM_DQ_PINS-1:0];
|
4491 |
|
|
wire dq_tq [C_NUM_DQ_PINS-1:0];
|
4492 |
|
|
|
4493 |
|
|
genvar dq;
|
4494 |
|
|
generate
|
4495 |
|
|
for(dq = 0; dq < C_NUM_DQ_PINS; dq = dq + 1) begin : gen_dq
|
4496 |
|
|
|
4497 |
|
|
OSERDES2 #(
|
4498 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
4499 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
4500 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
4501 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
4502 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE
|
4503 |
|
|
.DATA_WIDTH (2), // {1..8}
|
4504 |
|
|
.TRAIN_PATTERN (5) // {0..15}
|
4505 |
|
|
) oserdes2_dq_0
|
4506 |
|
|
(
|
4507 |
|
|
.OQ (dq_oq[dq]),
|
4508 |
|
|
.SHIFTOUT1 (),
|
4509 |
|
|
.SHIFTOUT2 (),
|
4510 |
|
|
.SHIFTOUT3 (),
|
4511 |
|
|
.SHIFTOUT4 (),
|
4512 |
|
|
.TQ (dq_tq[dq]),
|
4513 |
|
|
.CLK0 (ioclk90),
|
4514 |
|
|
.CLK1 (),
|
4515 |
|
|
.CLKDIV (),
|
4516 |
|
|
.D1 (dqo_p[dq]),
|
4517 |
|
|
.D2 (dqo_n[dq]),
|
4518 |
|
|
.D3 (),
|
4519 |
|
|
.D4 (),
|
4520 |
|
|
.IOCE (pll_ce_90),
|
4521 |
|
|
.OCE (1'b1),
|
4522 |
|
|
.RST (int_sys_rst),
|
4523 |
|
|
.SHIFTIN1 (),
|
4524 |
|
|
.SHIFTIN2 (),
|
4525 |
|
|
.SHIFTIN3 (),
|
4526 |
|
|
.SHIFTIN4 (),
|
4527 |
|
|
.T1 (dqIO_w_en_0),
|
4528 |
|
|
.T2 (dqIO_w_en_0),
|
4529 |
|
|
.T3 (),
|
4530 |
|
|
.T4 (),
|
4531 |
|
|
.TCE (1'b1),
|
4532 |
|
|
.TRAIN (ioi_drp_train)
|
4533 |
|
|
);
|
4534 |
|
|
|
4535 |
|
|
end
|
4536 |
|
|
endgenerate
|
4537 |
|
|
|
4538 |
|
|
////////
|
4539 |
|
|
//DQSP
|
4540 |
|
|
////////
|
4541 |
|
|
|
4542 |
|
|
wire dqsp_oq ;
|
4543 |
|
|
wire dqsp_tq ;
|
4544 |
|
|
|
4545 |
|
|
OSERDES2 #(
|
4546 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
4547 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
4548 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
4549 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
4550 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE
|
4551 |
|
|
.DATA_WIDTH (2) // {1..8}
|
4552 |
|
|
) oserdes2_dqsp_0
|
4553 |
|
|
(
|
4554 |
|
|
.OQ (dqsp_oq),
|
4555 |
|
|
.SHIFTOUT1(),
|
4556 |
|
|
.SHIFTOUT2(),
|
4557 |
|
|
.SHIFTOUT3(),
|
4558 |
|
|
.SHIFTOUT4(),
|
4559 |
|
|
.TQ (dqsp_tq),
|
4560 |
|
|
.CLK0 (ioclk0),
|
4561 |
|
|
.CLK1(),
|
4562 |
|
|
.CLKDIV(),
|
4563 |
|
|
.D1 (1'b0),
|
4564 |
|
|
.D2 (1'b1),
|
4565 |
|
|
.D3(),
|
4566 |
|
|
.D4(),
|
4567 |
|
|
.IOCE (pll_ce_0),
|
4568 |
|
|
.OCE (1'b1),
|
4569 |
|
|
.RST (int_sys_rst),
|
4570 |
|
|
.SHIFTIN1(),
|
4571 |
|
|
.SHIFTIN2(),
|
4572 |
|
|
.SHIFTIN3 (),
|
4573 |
|
|
.SHIFTIN4 (),
|
4574 |
|
|
.T1 (dqsIO_w_en_90_n),
|
4575 |
|
|
.T2 (dqsIO_w_en_90_p),
|
4576 |
|
|
.T3(),
|
4577 |
|
|
.T4(),
|
4578 |
|
|
.TCE (1'b1),
|
4579 |
|
|
.TRAIN (1'b0)
|
4580 |
|
|
);
|
4581 |
|
|
|
4582 |
|
|
////////
|
4583 |
|
|
//DQSN
|
4584 |
|
|
////////
|
4585 |
|
|
|
4586 |
|
|
wire dqsn_oq ;
|
4587 |
|
|
wire dqsn_tq ;
|
4588 |
|
|
|
4589 |
|
|
|
4590 |
|
|
|
4591 |
|
|
OSERDES2 #(
|
4592 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
4593 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
4594 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
4595 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
4596 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_SLAVE), // MASTER, SLAVE
|
4597 |
|
|
.DATA_WIDTH (2) // {1..8}
|
4598 |
|
|
) oserdes2_dqsn_0
|
4599 |
|
|
(
|
4600 |
|
|
.OQ (dqsn_oq),
|
4601 |
|
|
.SHIFTOUT1(),
|
4602 |
|
|
.SHIFTOUT2(),
|
4603 |
|
|
.SHIFTOUT3(),
|
4604 |
|
|
.SHIFTOUT4(),
|
4605 |
|
|
.TQ (dqsn_tq),
|
4606 |
|
|
.CLK0 (ioclk0),
|
4607 |
|
|
.CLK1(),
|
4608 |
|
|
.CLKDIV(),
|
4609 |
|
|
.D1 (1'b1),
|
4610 |
|
|
.D2 (1'b0),
|
4611 |
|
|
.D3(),
|
4612 |
|
|
.D4(),
|
4613 |
|
|
.IOCE (pll_ce_0),
|
4614 |
|
|
.OCE (1'b1),
|
4615 |
|
|
.RST (int_sys_rst),
|
4616 |
|
|
.SHIFTIN1 (),
|
4617 |
|
|
.SHIFTIN2 (),
|
4618 |
|
|
.SHIFTIN3(),
|
4619 |
|
|
.SHIFTIN4(),
|
4620 |
|
|
.T1 (dqsIO_w_en_90_n),
|
4621 |
|
|
.T2 (dqsIO_w_en_90_p),
|
4622 |
|
|
.T3(),
|
4623 |
|
|
.T4(),
|
4624 |
|
|
.TCE (1'b1),
|
4625 |
|
|
.TRAIN (1'b0)
|
4626 |
|
|
);
|
4627 |
|
|
|
4628 |
|
|
////////
|
4629 |
|
|
//UDQSP
|
4630 |
|
|
////////
|
4631 |
|
|
|
4632 |
|
|
wire udqsp_oq ;
|
4633 |
|
|
wire udqsp_tq ;
|
4634 |
|
|
|
4635 |
|
|
|
4636 |
|
|
OSERDES2 #(
|
4637 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
4638 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
4639 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
4640 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
4641 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE
|
4642 |
|
|
.DATA_WIDTH (2) // {1..8}
|
4643 |
|
|
) oserdes2_udqsp_0
|
4644 |
|
|
(
|
4645 |
|
|
.OQ (udqsp_oq),
|
4646 |
|
|
.SHIFTOUT1(),
|
4647 |
|
|
.SHIFTOUT2(),
|
4648 |
|
|
.SHIFTOUT3(),
|
4649 |
|
|
.SHIFTOUT4(),
|
4650 |
|
|
.TQ (udqsp_tq),
|
4651 |
|
|
.CLK0 (ioclk0),
|
4652 |
|
|
.CLK1(),
|
4653 |
|
|
.CLKDIV(),
|
4654 |
|
|
.D1 (1'b0),
|
4655 |
|
|
.D2 (1'b1),
|
4656 |
|
|
.D3(),
|
4657 |
|
|
.D4(),
|
4658 |
|
|
.IOCE (pll_ce_0),
|
4659 |
|
|
.OCE (1'b1),
|
4660 |
|
|
.RST (int_sys_rst),
|
4661 |
|
|
.SHIFTIN1(),
|
4662 |
|
|
.SHIFTIN2(),
|
4663 |
|
|
.SHIFTIN3 (),
|
4664 |
|
|
.SHIFTIN4 (),
|
4665 |
|
|
.T1 (dqsIO_w_en_90_n),
|
4666 |
|
|
.T2 (dqsIO_w_en_90_p),
|
4667 |
|
|
.T3(),
|
4668 |
|
|
.T4(),
|
4669 |
|
|
.TCE (1'b1),
|
4670 |
|
|
.TRAIN (1'b0)
|
4671 |
|
|
);
|
4672 |
|
|
|
4673 |
|
|
////////
|
4674 |
|
|
//UDQSN
|
4675 |
|
|
////////
|
4676 |
|
|
|
4677 |
|
|
wire udqsn_oq ;
|
4678 |
|
|
wire udqsn_tq ;
|
4679 |
|
|
|
4680 |
|
|
OSERDES2 #(
|
4681 |
|
|
.BYPASS_GCLK_FF ("TRUE"),
|
4682 |
|
|
.DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting
|
4683 |
|
|
.DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
|
4684 |
|
|
.OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL
|
4685 |
|
|
.SERDES_MODE (C_OSERDES2_SERDES_MODE_SLAVE), // MASTER, SLAVE
|
4686 |
|
|
.DATA_WIDTH (2) // {1..8}
|
4687 |
|
|
) oserdes2_udqsn_0
|
4688 |
|
|
(
|
4689 |
|
|
.OQ (udqsn_oq),
|
4690 |
|
|
.SHIFTOUT1(),
|
4691 |
|
|
.SHIFTOUT2(),
|
4692 |
|
|
.SHIFTOUT3(),
|
4693 |
|
|
.SHIFTOUT4(),
|
4694 |
|
|
.TQ (udqsn_tq),
|
4695 |
|
|
.CLK0 (ioclk0),
|
4696 |
|
|
.CLK1(),
|
4697 |
|
|
.CLKDIV(),
|
4698 |
|
|
.D1 (1'b1),
|
4699 |
|
|
.D2 (1'b0),
|
4700 |
|
|
.D3(),
|
4701 |
|
|
.D4(),
|
4702 |
|
|
.IOCE (pll_ce_0),
|
4703 |
|
|
.OCE (1'b1),
|
4704 |
|
|
.RST (int_sys_rst),
|
4705 |
|
|
.SHIFTIN1 (),
|
4706 |
|
|
.SHIFTIN2 (),
|
4707 |
|
|
.SHIFTIN3(),
|
4708 |
|
|
.SHIFTIN4(),
|
4709 |
|
|
.T1 (dqsIO_w_en_90_n),
|
4710 |
|
|
.T2 (dqsIO_w_en_90_p),
|
4711 |
|
|
.T3(),
|
4712 |
|
|
.T4(),
|
4713 |
|
|
.TCE (1'b1),
|
4714 |
|
|
.TRAIN (1'b0)
|
4715 |
|
|
);
|
4716 |
|
|
|
4717 |
|
|
////////////////////////////////////////////////////////
|
4718 |
|
|
//OSDDRES2 instantiations end
|
4719 |
|
|
///////////////////////////////////////////////////////
|
4720 |
|
|
|
4721 |
|
|
wire aux_sdi_out_udqsp;
|
4722 |
|
|
wire aux_sdi_out_10;
|
4723 |
|
|
wire aux_sdi_out_11;
|
4724 |
|
|
wire aux_sdi_out_12;
|
4725 |
|
|
wire aux_sdi_out_14;
|
4726 |
|
|
wire aux_sdi_out_15;
|
4727 |
|
|
|
4728 |
|
|
////////////////////////////////////////////////
|
4729 |
|
|
//IODRP2 instantiations
|
4730 |
|
|
////////////////////////////////////////////////
|
4731 |
|
|
generate
|
4732 |
|
|
if(C_NUM_DQ_PINS == 16 ) begin : dq_15_0_data
|
4733 |
|
|
////////////////////////////////////////////////
|
4734 |
|
|
//IODRP2 instantiations
|
4735 |
|
|
////////////////////////////////////////////////
|
4736 |
|
|
|
4737 |
|
|
wire aux_sdi_out_14;
|
4738 |
|
|
wire aux_sdi_out_15;
|
4739 |
|
|
////////////////////////////////////////////////
|
4740 |
|
|
//DQ14
|
4741 |
|
|
////////////////////////////////////////////////
|
4742 |
|
|
IODRP2_MCB #(
|
4743 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
4744 |
|
|
.IDELAY_VALUE (DQ14_TAP_DELAY_VAL), // 0 to 255 inclusive
|
4745 |
|
|
.MCB_ADDRESS (7), // 0 to 15
|
4746 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
4747 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
4748 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
4749 |
|
|
)
|
4750 |
|
|
iodrp2_dq_14
|
4751 |
|
|
(
|
4752 |
|
|
.AUXSDO (aux_sdi_out_14),
|
4753 |
|
|
.DATAOUT(),
|
4754 |
|
|
.DATAOUT2(),
|
4755 |
|
|
.DOUT (ioi_dq[14]),
|
4756 |
|
|
.DQSOUTN(),
|
4757 |
|
|
.DQSOUTP (in_dq[14]),
|
4758 |
|
|
.SDO(),
|
4759 |
|
|
.TOUT (t_dq[14]),
|
4760 |
|
|
.ADD (ioi_drp_add),
|
4761 |
|
|
.AUXADDR (ioi_drp_addr),
|
4762 |
|
|
.AUXSDOIN (aux_sdi_out_15),
|
4763 |
|
|
.BKST (ioi_drp_broadcast),
|
4764 |
|
|
.CLK (ioi_drp_clk),
|
4765 |
|
|
.CS (ioi_drp_cs),
|
4766 |
|
|
.IDATAIN (in_pre_dq[14]),
|
4767 |
|
|
.IOCLK0 (ioclk90),
|
4768 |
|
|
.IOCLK1(),
|
4769 |
|
|
.MEMUPDATE (ioi_drp_update),
|
4770 |
|
|
.ODATAIN (dq_oq[14]),
|
4771 |
|
|
.SDI (ioi_drp_sdo),
|
4772 |
|
|
.T (dq_tq[14])
|
4773 |
|
|
);
|
4774 |
|
|
|
4775 |
|
|
|
4776 |
|
|
/////////////////////////////////////////////////
|
4777 |
|
|
//DQ15
|
4778 |
|
|
////////////////////////////////////////////////
|
4779 |
|
|
IODRP2_MCB #(
|
4780 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
4781 |
|
|
.IDELAY_VALUE (DQ15_TAP_DELAY_VAL), // 0 to 255 inclusive
|
4782 |
|
|
.MCB_ADDRESS (7), // 0 to 15
|
4783 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
4784 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
4785 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
4786 |
|
|
|
4787 |
|
|
)
|
4788 |
|
|
iodrp2_dq_15
|
4789 |
|
|
(
|
4790 |
|
|
.AUXSDO (aux_sdi_out_15),
|
4791 |
|
|
.DATAOUT(),
|
4792 |
|
|
.DATAOUT2(),
|
4793 |
|
|
.DOUT (ioi_dq[15]),
|
4794 |
|
|
.DQSOUTN(),
|
4795 |
|
|
.DQSOUTP (in_dq[15]),
|
4796 |
|
|
.SDO(),
|
4797 |
|
|
.TOUT (t_dq[15]),
|
4798 |
|
|
.ADD (ioi_drp_add),
|
4799 |
|
|
.AUXADDR (ioi_drp_addr),
|
4800 |
|
|
.AUXSDOIN (1'b0),
|
4801 |
|
|
.BKST (ioi_drp_broadcast),
|
4802 |
|
|
.CLK (ioi_drp_clk),
|
4803 |
|
|
.CS (ioi_drp_cs),
|
4804 |
|
|
.IDATAIN (in_pre_dq[15]),
|
4805 |
|
|
.IOCLK0 (ioclk90),
|
4806 |
|
|
.IOCLK1(),
|
4807 |
|
|
.MEMUPDATE (ioi_drp_update),
|
4808 |
|
|
.ODATAIN (dq_oq[15]),
|
4809 |
|
|
.SDI (ioi_drp_sdo),
|
4810 |
|
|
.T (dq_tq[15])
|
4811 |
|
|
);
|
4812 |
|
|
|
4813 |
|
|
|
4814 |
|
|
|
4815 |
|
|
wire aux_sdi_out_12;
|
4816 |
|
|
wire aux_sdi_out_13;
|
4817 |
|
|
/////////////////////////////////////////////////
|
4818 |
|
|
//DQ12
|
4819 |
|
|
////////////////////////////////////////////////
|
4820 |
|
|
IODRP2_MCB #(
|
4821 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
4822 |
|
|
.IDELAY_VALUE (DQ12_TAP_DELAY_VAL), // 0 to 255 inclusive
|
4823 |
|
|
.MCB_ADDRESS (6), // 0 to 15
|
4824 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
4825 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
4826 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
4827 |
|
|
|
4828 |
|
|
)
|
4829 |
|
|
iodrp2_dq_12
|
4830 |
|
|
(
|
4831 |
|
|
.AUXSDO (aux_sdi_out_12),
|
4832 |
|
|
.DATAOUT(),
|
4833 |
|
|
.DATAOUT2(),
|
4834 |
|
|
.DOUT (ioi_dq[12]),
|
4835 |
|
|
.DQSOUTN(),
|
4836 |
|
|
.DQSOUTP (in_dq[12]),
|
4837 |
|
|
.SDO(),
|
4838 |
|
|
.TOUT (t_dq[12]),
|
4839 |
|
|
.ADD (ioi_drp_add),
|
4840 |
|
|
.AUXADDR (ioi_drp_addr),
|
4841 |
|
|
.AUXSDOIN (aux_sdi_out_13),
|
4842 |
|
|
.BKST (ioi_drp_broadcast),
|
4843 |
|
|
.CLK (ioi_drp_clk),
|
4844 |
|
|
.CS (ioi_drp_cs),
|
4845 |
|
|
.IDATAIN (in_pre_dq[12]),
|
4846 |
|
|
.IOCLK0 (ioclk90),
|
4847 |
|
|
.IOCLK1(),
|
4848 |
|
|
.MEMUPDATE (ioi_drp_update),
|
4849 |
|
|
.ODATAIN (dq_oq[12]),
|
4850 |
|
|
.SDI (ioi_drp_sdo),
|
4851 |
|
|
.T (dq_tq[12])
|
4852 |
|
|
);
|
4853 |
|
|
|
4854 |
|
|
|
4855 |
|
|
|
4856 |
|
|
/////////////////////////////////////////////////
|
4857 |
|
|
//DQ13
|
4858 |
|
|
////////////////////////////////////////////////
|
4859 |
|
|
IODRP2_MCB #(
|
4860 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
4861 |
|
|
.IDELAY_VALUE (DQ13_TAP_DELAY_VAL), // 0 to 255 inclusive
|
4862 |
|
|
.MCB_ADDRESS (6), // 0 to 15
|
4863 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
4864 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
4865 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
4866 |
|
|
|
4867 |
|
|
)
|
4868 |
|
|
iodrp2_dq_13
|
4869 |
|
|
(
|
4870 |
|
|
.AUXSDO (aux_sdi_out_13),
|
4871 |
|
|
.DATAOUT(),
|
4872 |
|
|
.DATAOUT2(),
|
4873 |
|
|
.DOUT (ioi_dq[13]),
|
4874 |
|
|
.DQSOUTN(),
|
4875 |
|
|
.DQSOUTP (in_dq[13]),
|
4876 |
|
|
.SDO(),
|
4877 |
|
|
.TOUT (t_dq[13]),
|
4878 |
|
|
.ADD (ioi_drp_add),
|
4879 |
|
|
.AUXADDR (ioi_drp_addr),
|
4880 |
|
|
.AUXSDOIN (aux_sdi_out_14),
|
4881 |
|
|
.BKST (ioi_drp_broadcast),
|
4882 |
|
|
.CLK (ioi_drp_clk),
|
4883 |
|
|
.CS (ioi_drp_cs),
|
4884 |
|
|
.IDATAIN (in_pre_dq[13]),
|
4885 |
|
|
.IOCLK0 (ioclk90),
|
4886 |
|
|
.IOCLK1(),
|
4887 |
|
|
.MEMUPDATE (ioi_drp_update),
|
4888 |
|
|
.ODATAIN (dq_oq[13]),
|
4889 |
|
|
.SDI (ioi_drp_sdo),
|
4890 |
|
|
.T (dq_tq[13])
|
4891 |
|
|
);
|
4892 |
|
|
|
4893 |
|
|
|
4894 |
|
|
wire aux_sdi_out_udqsp;
|
4895 |
|
|
wire aux_sdi_out_udqsn;
|
4896 |
|
|
/////////
|
4897 |
|
|
//UDQSP
|
4898 |
|
|
/////////
|
4899 |
|
|
IODRP2_MCB #(
|
4900 |
|
|
.DATA_RATE (C_DQS_IODRP2_DATA_RATE), // "SDR", "DDR"
|
4901 |
|
|
.IDELAY_VALUE (UDQSP_TAP_DELAY_VAL), // 0 to 255 inclusive
|
4902 |
|
|
.MCB_ADDRESS (14), // 0 to 15
|
4903 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
4904 |
|
|
.SERDES_MODE (C_DQS_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
4905 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
4906 |
|
|
|
4907 |
|
|
)
|
4908 |
|
|
iodrp2_udqsp_0
|
4909 |
|
|
(
|
4910 |
|
|
.AUXSDO (aux_sdi_out_udqsp),
|
4911 |
|
|
.DATAOUT(),
|
4912 |
|
|
.DATAOUT2(),
|
4913 |
|
|
.DOUT (ioi_udqs),
|
4914 |
|
|
.DQSOUTN(),
|
4915 |
|
|
.DQSOUTP (idelay_udqs_ioi_m),
|
4916 |
|
|
.SDO(),
|
4917 |
|
|
.TOUT (t_udqs),
|
4918 |
|
|
.ADD (ioi_drp_add),
|
4919 |
|
|
.AUXADDR (ioi_drp_addr),
|
4920 |
|
|
.AUXSDOIN (aux_sdi_out_udqsn),
|
4921 |
|
|
.BKST (ioi_drp_broadcast),
|
4922 |
|
|
.CLK (ioi_drp_clk),
|
4923 |
|
|
.CS (ioi_drp_cs),
|
4924 |
|
|
.IDATAIN (in_pre_udqsp),
|
4925 |
|
|
.IOCLK0 (ioclk0),
|
4926 |
|
|
.IOCLK1(),
|
4927 |
|
|
.MEMUPDATE (ioi_drp_update),
|
4928 |
|
|
.ODATAIN (udqsp_oq),
|
4929 |
|
|
.SDI (ioi_drp_sdo),
|
4930 |
|
|
.T (udqsp_tq)
|
4931 |
|
|
);
|
4932 |
|
|
|
4933 |
|
|
/////////
|
4934 |
|
|
//UDQSN
|
4935 |
|
|
/////////
|
4936 |
|
|
IODRP2_MCB #(
|
4937 |
|
|
.DATA_RATE (C_DQS_IODRP2_DATA_RATE), // "SDR", "DDR"
|
4938 |
|
|
.IDELAY_VALUE (UDQSN_TAP_DELAY_VAL), // 0 to 255 inclusive
|
4939 |
|
|
.MCB_ADDRESS (14), // 0 to 15
|
4940 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
4941 |
|
|
.SERDES_MODE (C_DQS_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
4942 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
4943 |
|
|
|
4944 |
|
|
)
|
4945 |
|
|
iodrp2_udqsn_0
|
4946 |
|
|
(
|
4947 |
|
|
.AUXSDO (aux_sdi_out_udqsn),
|
4948 |
|
|
.DATAOUT(),
|
4949 |
|
|
.DATAOUT2(),
|
4950 |
|
|
.DOUT (ioi_udqsn),
|
4951 |
|
|
.DQSOUTN(),
|
4952 |
|
|
.DQSOUTP (idelay_udqs_ioi_s),
|
4953 |
|
|
.SDO(),
|
4954 |
|
|
.TOUT (t_udqsn),
|
4955 |
|
|
.ADD (ioi_drp_add),
|
4956 |
|
|
.AUXADDR (ioi_drp_addr),
|
4957 |
|
|
.AUXSDOIN (aux_sdi_out_12),
|
4958 |
|
|
.BKST (ioi_drp_broadcast),
|
4959 |
|
|
.CLK (ioi_drp_clk),
|
4960 |
|
|
.CS (ioi_drp_cs),
|
4961 |
|
|
.IDATAIN (in_pre_udqsp),
|
4962 |
|
|
.IOCLK0 (ioclk0),
|
4963 |
|
|
.IOCLK1(),
|
4964 |
|
|
.MEMUPDATE (ioi_drp_update),
|
4965 |
|
|
.ODATAIN (udqsn_oq),
|
4966 |
|
|
.SDI (ioi_drp_sdo),
|
4967 |
|
|
.T (udqsn_tq)
|
4968 |
|
|
);
|
4969 |
|
|
|
4970 |
|
|
|
4971 |
|
|
wire aux_sdi_out_10;
|
4972 |
|
|
wire aux_sdi_out_11;
|
4973 |
|
|
/////////////////////////////////////////////////
|
4974 |
|
|
//DQ10
|
4975 |
|
|
////////////////////////////////////////////////
|
4976 |
|
|
IODRP2_MCB #(
|
4977 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
4978 |
|
|
.IDELAY_VALUE (DQ10_TAP_DELAY_VAL), // 0 to 255 inclusive
|
4979 |
|
|
.MCB_ADDRESS (5), // 0 to 15
|
4980 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
4981 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
4982 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
4983 |
|
|
|
4984 |
|
|
)
|
4985 |
|
|
iodrp2_dq_10
|
4986 |
|
|
(
|
4987 |
|
|
.AUXSDO (aux_sdi_out_10),
|
4988 |
|
|
.DATAOUT(),
|
4989 |
|
|
.DATAOUT2(),
|
4990 |
|
|
.DOUT (ioi_dq[10]),
|
4991 |
|
|
.DQSOUTN(),
|
4992 |
|
|
.DQSOUTP (in_dq[10]),
|
4993 |
|
|
.SDO(),
|
4994 |
|
|
.TOUT (t_dq[10]),
|
4995 |
|
|
.ADD (ioi_drp_add),
|
4996 |
|
|
.AUXADDR (ioi_drp_addr),
|
4997 |
|
|
.AUXSDOIN (aux_sdi_out_11),
|
4998 |
|
|
.BKST (ioi_drp_broadcast),
|
4999 |
|
|
.CLK (ioi_drp_clk),
|
5000 |
|
|
.CS (ioi_drp_cs),
|
5001 |
|
|
.IDATAIN (in_pre_dq[10]),
|
5002 |
|
|
.IOCLK0 (ioclk90),
|
5003 |
|
|
.IOCLK1(),
|
5004 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5005 |
|
|
.ODATAIN (dq_oq[10]),
|
5006 |
|
|
.SDI (ioi_drp_sdo),
|
5007 |
|
|
.T (dq_tq[10])
|
5008 |
|
|
);
|
5009 |
|
|
|
5010 |
|
|
|
5011 |
|
|
/////////////////////////////////////////////////
|
5012 |
|
|
//DQ11
|
5013 |
|
|
////////////////////////////////////////////////
|
5014 |
|
|
IODRP2_MCB #(
|
5015 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5016 |
|
|
.IDELAY_VALUE (DQ11_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5017 |
|
|
.MCB_ADDRESS (5), // 0 to 15
|
5018 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5019 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
5020 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5021 |
|
|
|
5022 |
|
|
)
|
5023 |
|
|
iodrp2_dq_11
|
5024 |
|
|
(
|
5025 |
|
|
.AUXSDO (aux_sdi_out_11),
|
5026 |
|
|
.DATAOUT(),
|
5027 |
|
|
.DATAOUT2(),
|
5028 |
|
|
.DOUT (ioi_dq[11]),
|
5029 |
|
|
.DQSOUTN(),
|
5030 |
|
|
.DQSOUTP (in_dq[11]),
|
5031 |
|
|
.SDO(),
|
5032 |
|
|
.TOUT (t_dq[11]),
|
5033 |
|
|
.ADD (ioi_drp_add),
|
5034 |
|
|
.AUXADDR (ioi_drp_addr),
|
5035 |
|
|
.AUXSDOIN (aux_sdi_out_udqsp),
|
5036 |
|
|
.BKST (ioi_drp_broadcast),
|
5037 |
|
|
.CLK (ioi_drp_clk),
|
5038 |
|
|
.CS (ioi_drp_cs),
|
5039 |
|
|
.IDATAIN (in_pre_dq[11]),
|
5040 |
|
|
.IOCLK0 (ioclk90),
|
5041 |
|
|
.IOCLK1(),
|
5042 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5043 |
|
|
.ODATAIN (dq_oq[11]),
|
5044 |
|
|
.SDI (ioi_drp_sdo),
|
5045 |
|
|
.T (dq_tq[11])
|
5046 |
|
|
);
|
5047 |
|
|
|
5048 |
|
|
|
5049 |
|
|
|
5050 |
|
|
wire aux_sdi_out_8;
|
5051 |
|
|
wire aux_sdi_out_9;
|
5052 |
|
|
/////////////////////////////////////////////////
|
5053 |
|
|
//DQ8
|
5054 |
|
|
////////////////////////////////////////////////
|
5055 |
|
|
IODRP2_MCB #(
|
5056 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5057 |
|
|
.IDELAY_VALUE (DQ8_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5058 |
|
|
.MCB_ADDRESS (4), // 0 to 15
|
5059 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5060 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
5061 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5062 |
|
|
|
5063 |
|
|
)
|
5064 |
|
|
iodrp2_dq_8
|
5065 |
|
|
(
|
5066 |
|
|
.AUXSDO (aux_sdi_out_8),
|
5067 |
|
|
.DATAOUT(),
|
5068 |
|
|
.DATAOUT2(),
|
5069 |
|
|
.DOUT (ioi_dq[8]),
|
5070 |
|
|
.DQSOUTN(),
|
5071 |
|
|
.DQSOUTP (in_dq[8]),
|
5072 |
|
|
.SDO(),
|
5073 |
|
|
.TOUT (t_dq[8]),
|
5074 |
|
|
.ADD (ioi_drp_add),
|
5075 |
|
|
.AUXADDR (ioi_drp_addr),
|
5076 |
|
|
.AUXSDOIN (aux_sdi_out_9),
|
5077 |
|
|
.BKST (ioi_drp_broadcast),
|
5078 |
|
|
.CLK (ioi_drp_clk),
|
5079 |
|
|
.CS (ioi_drp_cs),
|
5080 |
|
|
.IDATAIN (in_pre_dq[8]),
|
5081 |
|
|
.IOCLK0 (ioclk90),
|
5082 |
|
|
.IOCLK1(),
|
5083 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5084 |
|
|
.ODATAIN (dq_oq[8]),
|
5085 |
|
|
.SDI (ioi_drp_sdo),
|
5086 |
|
|
.T (dq_tq[8])
|
5087 |
|
|
);
|
5088 |
|
|
|
5089 |
|
|
|
5090 |
|
|
/////////////////////////////////////////////////
|
5091 |
|
|
//DQ9
|
5092 |
|
|
////////////////////////////////////////////////
|
5093 |
|
|
IODRP2_MCB #(
|
5094 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5095 |
|
|
.IDELAY_VALUE (DQ9_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5096 |
|
|
.MCB_ADDRESS (4), // 0 to 15
|
5097 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5098 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
5099 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5100 |
|
|
|
5101 |
|
|
)
|
5102 |
|
|
iodrp2_dq_9
|
5103 |
|
|
(
|
5104 |
|
|
.AUXSDO (aux_sdi_out_9),
|
5105 |
|
|
.DATAOUT(),
|
5106 |
|
|
.DATAOUT2(),
|
5107 |
|
|
.DOUT (ioi_dq[9]),
|
5108 |
|
|
.DQSOUTN(),
|
5109 |
|
|
.DQSOUTP (in_dq[9]),
|
5110 |
|
|
.SDO(),
|
5111 |
|
|
.TOUT (t_dq[9]),
|
5112 |
|
|
.ADD (ioi_drp_add),
|
5113 |
|
|
.AUXADDR (ioi_drp_addr),
|
5114 |
|
|
.AUXSDOIN (aux_sdi_out_10),
|
5115 |
|
|
.BKST (ioi_drp_broadcast),
|
5116 |
|
|
.CLK (ioi_drp_clk),
|
5117 |
|
|
.CS (ioi_drp_cs),
|
5118 |
|
|
.IDATAIN (in_pre_dq[9]),
|
5119 |
|
|
.IOCLK0 (ioclk90),
|
5120 |
|
|
.IOCLK1(),
|
5121 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5122 |
|
|
.ODATAIN (dq_oq[9]),
|
5123 |
|
|
.SDI (ioi_drp_sdo),
|
5124 |
|
|
.T (dq_tq[9])
|
5125 |
|
|
);
|
5126 |
|
|
|
5127 |
|
|
|
5128 |
|
|
wire aux_sdi_out_0;
|
5129 |
|
|
wire aux_sdi_out_1;
|
5130 |
|
|
/////////////////////////////////////////////////
|
5131 |
|
|
//DQ0
|
5132 |
|
|
////////////////////////////////////////////////
|
5133 |
|
|
IODRP2_MCB #(
|
5134 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5135 |
|
|
.IDELAY_VALUE (DQ0_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5136 |
|
|
.MCB_ADDRESS (0), // 0 to 15
|
5137 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5138 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
5139 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5140 |
|
|
|
5141 |
|
|
)
|
5142 |
|
|
iodrp2_dq_0
|
5143 |
|
|
(
|
5144 |
|
|
.AUXSDO (aux_sdi_out_0),
|
5145 |
|
|
.DATAOUT(),
|
5146 |
|
|
.DATAOUT2(),
|
5147 |
|
|
.DOUT (ioi_dq[0]),
|
5148 |
|
|
.DQSOUTN(),
|
5149 |
|
|
.DQSOUTP (in_dq[0]),
|
5150 |
|
|
.SDO(),
|
5151 |
|
|
.TOUT (t_dq[0]),
|
5152 |
|
|
.ADD (ioi_drp_add),
|
5153 |
|
|
.AUXADDR (ioi_drp_addr),
|
5154 |
|
|
.AUXSDOIN (aux_sdi_out_1),
|
5155 |
|
|
.BKST (ioi_drp_broadcast),
|
5156 |
|
|
.CLK (ioi_drp_clk),
|
5157 |
|
|
.CS (ioi_drp_cs),
|
5158 |
|
|
.IDATAIN (in_pre_dq[0]),
|
5159 |
|
|
.IOCLK0 (ioclk90),
|
5160 |
|
|
.IOCLK1(),
|
5161 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5162 |
|
|
.ODATAIN (dq_oq[0]),
|
5163 |
|
|
.SDI (ioi_drp_sdo),
|
5164 |
|
|
.T (dq_tq[0])
|
5165 |
|
|
);
|
5166 |
|
|
|
5167 |
|
|
|
5168 |
|
|
/////////////////////////////////////////////////
|
5169 |
|
|
//DQ1
|
5170 |
|
|
////////////////////////////////////////////////
|
5171 |
|
|
IODRP2_MCB #(
|
5172 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5173 |
|
|
.IDELAY_VALUE (DQ1_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5174 |
|
|
.MCB_ADDRESS (0), // 0 to 15
|
5175 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5176 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
5177 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5178 |
|
|
|
5179 |
|
|
)
|
5180 |
|
|
iodrp2_dq_1
|
5181 |
|
|
(
|
5182 |
|
|
.AUXSDO (aux_sdi_out_1),
|
5183 |
|
|
.DATAOUT(),
|
5184 |
|
|
.DATAOUT2(),
|
5185 |
|
|
.DOUT (ioi_dq[1]),
|
5186 |
|
|
.DQSOUTN(),
|
5187 |
|
|
.DQSOUTP (in_dq[1]),
|
5188 |
|
|
.SDO(),
|
5189 |
|
|
.TOUT (t_dq[1]),
|
5190 |
|
|
.ADD (ioi_drp_add),
|
5191 |
|
|
.AUXADDR (ioi_drp_addr),
|
5192 |
|
|
.AUXSDOIN (aux_sdi_out_8),
|
5193 |
|
|
.BKST (ioi_drp_broadcast),
|
5194 |
|
|
.CLK (ioi_drp_clk),
|
5195 |
|
|
.CS (ioi_drp_cs),
|
5196 |
|
|
.IDATAIN (in_pre_dq[1]),
|
5197 |
|
|
.IOCLK0 (ioclk90),
|
5198 |
|
|
.IOCLK1(),
|
5199 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5200 |
|
|
.ODATAIN (dq_oq[1]),
|
5201 |
|
|
.SDI (ioi_drp_sdo),
|
5202 |
|
|
.T (dq_tq[1])
|
5203 |
|
|
);
|
5204 |
|
|
|
5205 |
|
|
|
5206 |
|
|
wire aux_sdi_out_2;
|
5207 |
|
|
wire aux_sdi_out_3;
|
5208 |
|
|
/////////////////////////////////////////////////
|
5209 |
|
|
//DQ2
|
5210 |
|
|
////////////////////////////////////////////////
|
5211 |
|
|
IODRP2_MCB #(
|
5212 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5213 |
|
|
.IDELAY_VALUE (DQ2_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5214 |
|
|
.MCB_ADDRESS (1), // 0 to 15
|
5215 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5216 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
5217 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5218 |
|
|
|
5219 |
|
|
)
|
5220 |
|
|
iodrp2_dq_2
|
5221 |
|
|
(
|
5222 |
|
|
.AUXSDO (aux_sdi_out_2),
|
5223 |
|
|
.DATAOUT(),
|
5224 |
|
|
.DATAOUT2(),
|
5225 |
|
|
.DOUT (ioi_dq[2]),
|
5226 |
|
|
.DQSOUTN(),
|
5227 |
|
|
.DQSOUTP (in_dq[2]),
|
5228 |
|
|
.SDO(),
|
5229 |
|
|
.TOUT (t_dq[2]),
|
5230 |
|
|
.ADD (ioi_drp_add),
|
5231 |
|
|
.AUXADDR (ioi_drp_addr),
|
5232 |
|
|
.AUXSDOIN (aux_sdi_out_3),
|
5233 |
|
|
.BKST (ioi_drp_broadcast),
|
5234 |
|
|
.CLK (ioi_drp_clk),
|
5235 |
|
|
.CS (ioi_drp_cs),
|
5236 |
|
|
.IDATAIN (in_pre_dq[2]),
|
5237 |
|
|
.IOCLK0 (ioclk90),
|
5238 |
|
|
.IOCLK1(),
|
5239 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5240 |
|
|
.ODATAIN (dq_oq[2]),
|
5241 |
|
|
.SDI (ioi_drp_sdo),
|
5242 |
|
|
.T (dq_tq[2])
|
5243 |
|
|
);
|
5244 |
|
|
|
5245 |
|
|
|
5246 |
|
|
/////////////////////////////////////////////////
|
5247 |
|
|
//DQ3
|
5248 |
|
|
////////////////////////////////////////////////
|
5249 |
|
|
IODRP2_MCB #(
|
5250 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5251 |
|
|
.IDELAY_VALUE (DQ3_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5252 |
|
|
.MCB_ADDRESS (1), // 0 to 15
|
5253 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5254 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
5255 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5256 |
|
|
|
5257 |
|
|
)
|
5258 |
|
|
iodrp2_dq_3
|
5259 |
|
|
(
|
5260 |
|
|
.AUXSDO (aux_sdi_out_3),
|
5261 |
|
|
.DATAOUT(),
|
5262 |
|
|
.DATAOUT2(),
|
5263 |
|
|
.DOUT (ioi_dq[3]),
|
5264 |
|
|
.DQSOUTN(),
|
5265 |
|
|
.DQSOUTP (in_dq[3]),
|
5266 |
|
|
.SDO(),
|
5267 |
|
|
.TOUT (t_dq[3]),
|
5268 |
|
|
.ADD (ioi_drp_add),
|
5269 |
|
|
.AUXADDR (ioi_drp_addr),
|
5270 |
|
|
.AUXSDOIN (aux_sdi_out_0),
|
5271 |
|
|
.BKST (ioi_drp_broadcast),
|
5272 |
|
|
.CLK (ioi_drp_clk),
|
5273 |
|
|
.CS (ioi_drp_cs),
|
5274 |
|
|
.IDATAIN (in_pre_dq[3]),
|
5275 |
|
|
.IOCLK0 (ioclk90),
|
5276 |
|
|
.IOCLK1(),
|
5277 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5278 |
|
|
.ODATAIN (dq_oq[3]),
|
5279 |
|
|
.SDI (ioi_drp_sdo),
|
5280 |
|
|
.T (dq_tq[3])
|
5281 |
|
|
);
|
5282 |
|
|
|
5283 |
|
|
|
5284 |
|
|
wire aux_sdi_out_dqsp;
|
5285 |
|
|
wire aux_sdi_out_dqsn;
|
5286 |
|
|
/////////
|
5287 |
|
|
//DQSP
|
5288 |
|
|
/////////
|
5289 |
|
|
IODRP2_MCB #(
|
5290 |
|
|
.DATA_RATE (C_DQS_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5291 |
|
|
.IDELAY_VALUE (LDQSP_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5292 |
|
|
.MCB_ADDRESS (15), // 0 to 15
|
5293 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5294 |
|
|
.SERDES_MODE (C_DQS_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
5295 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5296 |
|
|
|
5297 |
|
|
)
|
5298 |
|
|
iodrp2_dqsp_0
|
5299 |
|
|
(
|
5300 |
|
|
.AUXSDO (aux_sdi_out_dqsp),
|
5301 |
|
|
.DATAOUT(),
|
5302 |
|
|
.DATAOUT2(),
|
5303 |
|
|
.DOUT (ioi_dqs),
|
5304 |
|
|
.DQSOUTN(),
|
5305 |
|
|
.DQSOUTP (idelay_dqs_ioi_m),
|
5306 |
|
|
.SDO(),
|
5307 |
|
|
.TOUT (t_dqs),
|
5308 |
|
|
.ADD (ioi_drp_add),
|
5309 |
|
|
.AUXADDR (ioi_drp_addr),
|
5310 |
|
|
.AUXSDOIN (aux_sdi_out_dqsn),
|
5311 |
|
|
.BKST (ioi_drp_broadcast),
|
5312 |
|
|
.CLK (ioi_drp_clk),
|
5313 |
|
|
.CS (ioi_drp_cs),
|
5314 |
|
|
.IDATAIN (in_pre_dqsp),
|
5315 |
|
|
.IOCLK0 (ioclk0),
|
5316 |
|
|
.IOCLK1(),
|
5317 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5318 |
|
|
.ODATAIN (dqsp_oq),
|
5319 |
|
|
.SDI (ioi_drp_sdo),
|
5320 |
|
|
.T (dqsp_tq)
|
5321 |
|
|
);
|
5322 |
|
|
|
5323 |
|
|
/////////
|
5324 |
|
|
//DQSN
|
5325 |
|
|
/////////
|
5326 |
|
|
IODRP2_MCB #(
|
5327 |
|
|
.DATA_RATE (C_DQS_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5328 |
|
|
.IDELAY_VALUE (LDQSN_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5329 |
|
|
.MCB_ADDRESS (15), // 0 to 15
|
5330 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5331 |
|
|
.SERDES_MODE (C_DQS_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
5332 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5333 |
|
|
|
5334 |
|
|
)
|
5335 |
|
|
iodrp2_dqsn_0
|
5336 |
|
|
(
|
5337 |
|
|
.AUXSDO (aux_sdi_out_dqsn),
|
5338 |
|
|
.DATAOUT(),
|
5339 |
|
|
.DATAOUT2(),
|
5340 |
|
|
.DOUT (ioi_dqsn),
|
5341 |
|
|
.DQSOUTN(),
|
5342 |
|
|
.DQSOUTP (idelay_dqs_ioi_s),
|
5343 |
|
|
.SDO(),
|
5344 |
|
|
.TOUT (t_dqsn),
|
5345 |
|
|
.ADD (ioi_drp_add),
|
5346 |
|
|
.AUXADDR (ioi_drp_addr),
|
5347 |
|
|
.AUXSDOIN (aux_sdi_out_2),
|
5348 |
|
|
.BKST (ioi_drp_broadcast),
|
5349 |
|
|
.CLK (ioi_drp_clk),
|
5350 |
|
|
.CS (ioi_drp_cs),
|
5351 |
|
|
.IDATAIN (in_pre_dqsp),
|
5352 |
|
|
.IOCLK0 (ioclk0),
|
5353 |
|
|
.IOCLK1(),
|
5354 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5355 |
|
|
.ODATAIN (dqsn_oq),
|
5356 |
|
|
.SDI (ioi_drp_sdo),
|
5357 |
|
|
.T (dqsn_tq)
|
5358 |
|
|
);
|
5359 |
|
|
|
5360 |
|
|
wire aux_sdi_out_6;
|
5361 |
|
|
wire aux_sdi_out_7;
|
5362 |
|
|
/////////////////////////////////////////////////
|
5363 |
|
|
//DQ6
|
5364 |
|
|
////////////////////////////////////////////////
|
5365 |
|
|
IODRP2_MCB #(
|
5366 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5367 |
|
|
.IDELAY_VALUE (DQ6_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5368 |
|
|
.MCB_ADDRESS (3), // 0 to 15
|
5369 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5370 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
5371 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5372 |
|
|
|
5373 |
|
|
)
|
5374 |
|
|
iodrp2_dq_6
|
5375 |
|
|
(
|
5376 |
|
|
.AUXSDO (aux_sdi_out_6),
|
5377 |
|
|
.DATAOUT(),
|
5378 |
|
|
.DATAOUT2(),
|
5379 |
|
|
.DOUT (ioi_dq[6]),
|
5380 |
|
|
.DQSOUTN(),
|
5381 |
|
|
.DQSOUTP (in_dq[6]),
|
5382 |
|
|
.SDO(),
|
5383 |
|
|
.TOUT (t_dq[6]),
|
5384 |
|
|
.ADD (ioi_drp_add),
|
5385 |
|
|
.AUXADDR (ioi_drp_addr),
|
5386 |
|
|
.AUXSDOIN (aux_sdi_out_7),
|
5387 |
|
|
.BKST (ioi_drp_broadcast),
|
5388 |
|
|
.CLK (ioi_drp_clk),
|
5389 |
|
|
.CS (ioi_drp_cs),
|
5390 |
|
|
.IDATAIN (in_pre_dq[6]),
|
5391 |
|
|
.IOCLK0 (ioclk90),
|
5392 |
|
|
.IOCLK1(),
|
5393 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5394 |
|
|
.ODATAIN (dq_oq[6]),
|
5395 |
|
|
.SDI (ioi_drp_sdo),
|
5396 |
|
|
.T (dq_tq[6])
|
5397 |
|
|
);
|
5398 |
|
|
|
5399 |
|
|
/////////////////////////////////////////////////
|
5400 |
|
|
//DQ7
|
5401 |
|
|
////////////////////////////////////////////////
|
5402 |
|
|
IODRP2_MCB #(
|
5403 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5404 |
|
|
.IDELAY_VALUE (DQ7_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5405 |
|
|
.MCB_ADDRESS (3), // 0 to 15
|
5406 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5407 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
5408 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5409 |
|
|
|
5410 |
|
|
)
|
5411 |
|
|
iodrp2_dq_7
|
5412 |
|
|
(
|
5413 |
|
|
.AUXSDO (aux_sdi_out_7),
|
5414 |
|
|
.DATAOUT(),
|
5415 |
|
|
.DATAOUT2(),
|
5416 |
|
|
.DOUT (ioi_dq[7]),
|
5417 |
|
|
.DQSOUTN(),
|
5418 |
|
|
.DQSOUTP (in_dq[7]),
|
5419 |
|
|
.SDO(),
|
5420 |
|
|
.TOUT (t_dq[7]),
|
5421 |
|
|
.ADD (ioi_drp_add),
|
5422 |
|
|
.AUXADDR (ioi_drp_addr),
|
5423 |
|
|
.AUXSDOIN (aux_sdi_out_dqsp),
|
5424 |
|
|
.BKST (ioi_drp_broadcast),
|
5425 |
|
|
.CLK (ioi_drp_clk),
|
5426 |
|
|
.CS (ioi_drp_cs),
|
5427 |
|
|
.IDATAIN (in_pre_dq[7]),
|
5428 |
|
|
.IOCLK0 (ioclk90),
|
5429 |
|
|
.IOCLK1(),
|
5430 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5431 |
|
|
.ODATAIN (dq_oq[7]),
|
5432 |
|
|
.SDI (ioi_drp_sdo),
|
5433 |
|
|
.T (dq_tq[7])
|
5434 |
|
|
);
|
5435 |
|
|
|
5436 |
|
|
|
5437 |
|
|
|
5438 |
|
|
wire aux_sdi_out_4;
|
5439 |
|
|
wire aux_sdi_out_5;
|
5440 |
|
|
/////////////////////////////////////////////////
|
5441 |
|
|
//DQ4
|
5442 |
|
|
////////////////////////////////////////////////
|
5443 |
|
|
IODRP2_MCB #(
|
5444 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5445 |
|
|
.IDELAY_VALUE (DQ4_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5446 |
|
|
.MCB_ADDRESS (2), // 0 to 15
|
5447 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5448 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
5449 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5450 |
|
|
|
5451 |
|
|
)
|
5452 |
|
|
iodrp2_dq_4
|
5453 |
|
|
(
|
5454 |
|
|
.AUXSDO (aux_sdi_out_4),
|
5455 |
|
|
.DATAOUT(),
|
5456 |
|
|
.DATAOUT2(),
|
5457 |
|
|
.DOUT (ioi_dq[4]),
|
5458 |
|
|
.DQSOUTN(),
|
5459 |
|
|
.DQSOUTP (in_dq[4]),
|
5460 |
|
|
.SDO(),
|
5461 |
|
|
.TOUT (t_dq[4]),
|
5462 |
|
|
.ADD (ioi_drp_add),
|
5463 |
|
|
.AUXADDR (ioi_drp_addr),
|
5464 |
|
|
.AUXSDOIN (aux_sdi_out_5),
|
5465 |
|
|
.BKST (ioi_drp_broadcast),
|
5466 |
|
|
.CLK (ioi_drp_clk),
|
5467 |
|
|
.CS (ioi_drp_cs),
|
5468 |
|
|
.IDATAIN (in_pre_dq[4]),
|
5469 |
|
|
.IOCLK0 (ioclk90),
|
5470 |
|
|
.IOCLK1(),
|
5471 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5472 |
|
|
.ODATAIN (dq_oq[4]),
|
5473 |
|
|
.SDI (ioi_drp_sdo),
|
5474 |
|
|
.T (dq_tq[4])
|
5475 |
|
|
);
|
5476 |
|
|
|
5477 |
|
|
/////////////////////////////////////////////////
|
5478 |
|
|
//DQ5
|
5479 |
|
|
////////////////////////////////////////////////
|
5480 |
|
|
IODRP2_MCB #(
|
5481 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5482 |
|
|
.IDELAY_VALUE (DQ5_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5483 |
|
|
.MCB_ADDRESS (2), // 0 to 15
|
5484 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5485 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
5486 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5487 |
|
|
|
5488 |
|
|
)
|
5489 |
|
|
iodrp2_dq_5
|
5490 |
|
|
(
|
5491 |
|
|
.AUXSDO (aux_sdi_out_5),
|
5492 |
|
|
.DATAOUT(),
|
5493 |
|
|
.DATAOUT2(),
|
5494 |
|
|
.DOUT (ioi_dq[5]),
|
5495 |
|
|
.DQSOUTN(),
|
5496 |
|
|
.DQSOUTP (in_dq[5]),
|
5497 |
|
|
.SDO(),
|
5498 |
|
|
.TOUT (t_dq[5]),
|
5499 |
|
|
.ADD (ioi_drp_add),
|
5500 |
|
|
.AUXADDR (ioi_drp_addr),
|
5501 |
|
|
.AUXSDOIN (aux_sdi_out_6),
|
5502 |
|
|
.BKST (ioi_drp_broadcast),
|
5503 |
|
|
.CLK (ioi_drp_clk),
|
5504 |
|
|
.CS (ioi_drp_cs),
|
5505 |
|
|
.IDATAIN (in_pre_dq[5]),
|
5506 |
|
|
.IOCLK0 (ioclk90),
|
5507 |
|
|
.IOCLK1(),
|
5508 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5509 |
|
|
.ODATAIN (dq_oq[5]),
|
5510 |
|
|
.SDI (ioi_drp_sdo),
|
5511 |
|
|
.T (dq_tq[5])
|
5512 |
|
|
);
|
5513 |
|
|
|
5514 |
|
|
|
5515 |
|
|
//wire aux_sdi_out_udm;
|
5516 |
|
|
wire aux_sdi_out_ldm;
|
5517 |
|
|
/////////////////////////////////////////////////
|
5518 |
|
|
//UDM
|
5519 |
|
|
////////////////////////////////////////////////
|
5520 |
|
|
IODRP2_MCB #(
|
5521 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5522 |
|
|
.IDELAY_VALUE (0), // 0 to 255 inclusive
|
5523 |
|
|
.MCB_ADDRESS (8), // 0 to 15
|
5524 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5525 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
5526 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5527 |
|
|
|
5528 |
|
|
)
|
5529 |
|
|
iodrp2_dq_udm
|
5530 |
|
|
(
|
5531 |
|
|
.AUXSDO (ioi_drp_sdi),
|
5532 |
|
|
.DATAOUT(),
|
5533 |
|
|
.DATAOUT2(),
|
5534 |
|
|
.DOUT (ioi_udm),
|
5535 |
|
|
.DQSOUTN(),
|
5536 |
|
|
.DQSOUTP(),
|
5537 |
|
|
.SDO(),
|
5538 |
|
|
.TOUT (t_udm),
|
5539 |
|
|
.ADD (ioi_drp_add),
|
5540 |
|
|
.AUXADDR (ioi_drp_addr),
|
5541 |
|
|
.AUXSDOIN (aux_sdi_out_ldm),
|
5542 |
|
|
.BKST (ioi_drp_broadcast),
|
5543 |
|
|
.CLK (ioi_drp_clk),
|
5544 |
|
|
.CS (ioi_drp_cs),
|
5545 |
|
|
.IDATAIN(),
|
5546 |
|
|
.IOCLK0 (ioclk90),
|
5547 |
|
|
.IOCLK1(),
|
5548 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5549 |
|
|
.ODATAIN (udm_oq),
|
5550 |
|
|
.SDI (ioi_drp_sdo),
|
5551 |
|
|
.T (udm_t)
|
5552 |
|
|
);
|
5553 |
|
|
|
5554 |
|
|
|
5555 |
|
|
/////////////////////////////////////////////////
|
5556 |
|
|
//LDM
|
5557 |
|
|
////////////////////////////////////////////////
|
5558 |
|
|
IODRP2_MCB #(
|
5559 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5560 |
|
|
.IDELAY_VALUE (0), // 0 to 255 inclusive
|
5561 |
|
|
.MCB_ADDRESS (8), // 0 to 15
|
5562 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5563 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
5564 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5565 |
|
|
|
5566 |
|
|
)
|
5567 |
|
|
iodrp2_dq_ldm
|
5568 |
|
|
(
|
5569 |
|
|
.AUXSDO (aux_sdi_out_ldm),
|
5570 |
|
|
.DATAOUT(),
|
5571 |
|
|
.DATAOUT2(),
|
5572 |
|
|
.DOUT (ioi_ldm),
|
5573 |
|
|
.DQSOUTN(),
|
5574 |
|
|
.DQSOUTP(),
|
5575 |
|
|
.SDO(),
|
5576 |
|
|
.TOUT (t_ldm),
|
5577 |
|
|
.ADD (ioi_drp_add),
|
5578 |
|
|
.AUXADDR (ioi_drp_addr),
|
5579 |
|
|
.AUXSDOIN (aux_sdi_out_4),
|
5580 |
|
|
.BKST (ioi_drp_broadcast),
|
5581 |
|
|
.CLK (ioi_drp_clk),
|
5582 |
|
|
.CS (ioi_drp_cs),
|
5583 |
|
|
.IDATAIN(),
|
5584 |
|
|
.IOCLK0 (ioclk90),
|
5585 |
|
|
.IOCLK1(),
|
5586 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5587 |
|
|
.ODATAIN (ldm_oq),
|
5588 |
|
|
.SDI (ioi_drp_sdo),
|
5589 |
|
|
.T (ldm_t)
|
5590 |
|
|
);
|
5591 |
|
|
end
|
5592 |
|
|
endgenerate
|
5593 |
|
|
|
5594 |
|
|
generate
|
5595 |
|
|
if(C_NUM_DQ_PINS == 8 ) begin : dq_7_0_data
|
5596 |
|
|
wire aux_sdi_out_0;
|
5597 |
|
|
wire aux_sdi_out_1;
|
5598 |
|
|
/////////////////////////////////////////////////
|
5599 |
|
|
//DQ0
|
5600 |
|
|
////////////////////////////////////////////////
|
5601 |
|
|
IODRP2_MCB #(
|
5602 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5603 |
|
|
.IDELAY_VALUE (DQ0_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5604 |
|
|
.MCB_ADDRESS (0), // 0 to 15
|
5605 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5606 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
5607 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5608 |
|
|
|
5609 |
|
|
)
|
5610 |
|
|
iodrp2_dq_0
|
5611 |
|
|
(
|
5612 |
|
|
.AUXSDO (aux_sdi_out_0),
|
5613 |
|
|
.DATAOUT(),
|
5614 |
|
|
.DATAOUT2(),
|
5615 |
|
|
.DOUT (ioi_dq[0]),
|
5616 |
|
|
.DQSOUTN(),
|
5617 |
|
|
.DQSOUTP (in_dq[0]),
|
5618 |
|
|
.SDO(),
|
5619 |
|
|
.TOUT (t_dq[0]),
|
5620 |
|
|
.ADD (ioi_drp_add),
|
5621 |
|
|
.AUXADDR (ioi_drp_addr),
|
5622 |
|
|
.AUXSDOIN (aux_sdi_out_1),
|
5623 |
|
|
.BKST (ioi_drp_broadcast),
|
5624 |
|
|
.CLK (ioi_drp_clk),
|
5625 |
|
|
.CS (ioi_drp_cs),
|
5626 |
|
|
.IDATAIN (in_pre_dq[0]),
|
5627 |
|
|
.IOCLK0 (ioclk90),
|
5628 |
|
|
.IOCLK1(),
|
5629 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5630 |
|
|
.ODATAIN (dq_oq[0]),
|
5631 |
|
|
.SDI (ioi_drp_sdo),
|
5632 |
|
|
.T (dq_tq[0])
|
5633 |
|
|
);
|
5634 |
|
|
|
5635 |
|
|
|
5636 |
|
|
/////////////////////////////////////////////////
|
5637 |
|
|
//DQ1
|
5638 |
|
|
////////////////////////////////////////////////
|
5639 |
|
|
IODRP2_MCB #(
|
5640 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5641 |
|
|
.IDELAY_VALUE (DQ1_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5642 |
|
|
.MCB_ADDRESS (0), // 0 to 15
|
5643 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5644 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
5645 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5646 |
|
|
|
5647 |
|
|
)
|
5648 |
|
|
iodrp2_dq_1
|
5649 |
|
|
(
|
5650 |
|
|
.AUXSDO (aux_sdi_out_1),
|
5651 |
|
|
.DATAOUT(),
|
5652 |
|
|
.DATAOUT2(),
|
5653 |
|
|
.DOUT (ioi_dq[1]),
|
5654 |
|
|
.DQSOUTN(),
|
5655 |
|
|
.DQSOUTP (in_dq[1]),
|
5656 |
|
|
.SDO(),
|
5657 |
|
|
.TOUT (t_dq[1]),
|
5658 |
|
|
.ADD (ioi_drp_add),
|
5659 |
|
|
.AUXADDR (ioi_drp_addr),
|
5660 |
|
|
.AUXSDOIN (1'b0),
|
5661 |
|
|
.BKST (ioi_drp_broadcast),
|
5662 |
|
|
.CLK (ioi_drp_clk),
|
5663 |
|
|
.CS (ioi_drp_cs),
|
5664 |
|
|
.IDATAIN (in_pre_dq[1]),
|
5665 |
|
|
.IOCLK0 (ioclk90),
|
5666 |
|
|
.IOCLK1(),
|
5667 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5668 |
|
|
.ODATAIN (dq_oq[1]),
|
5669 |
|
|
.SDI (ioi_drp_sdo),
|
5670 |
|
|
.T (dq_tq[1])
|
5671 |
|
|
);
|
5672 |
|
|
|
5673 |
|
|
|
5674 |
|
|
wire aux_sdi_out_2;
|
5675 |
|
|
wire aux_sdi_out_3;
|
5676 |
|
|
/////////////////////////////////////////////////
|
5677 |
|
|
//DQ2
|
5678 |
|
|
////////////////////////////////////////////////
|
5679 |
|
|
IODRP2_MCB #(
|
5680 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5681 |
|
|
.IDELAY_VALUE (DQ2_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5682 |
|
|
.MCB_ADDRESS (1), // 0 to 15
|
5683 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5684 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
5685 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5686 |
|
|
|
5687 |
|
|
)
|
5688 |
|
|
iodrp2_dq_2
|
5689 |
|
|
(
|
5690 |
|
|
.AUXSDO (aux_sdi_out_2),
|
5691 |
|
|
.DATAOUT(),
|
5692 |
|
|
.DATAOUT2(),
|
5693 |
|
|
.DOUT (ioi_dq[2]),
|
5694 |
|
|
.DQSOUTN(),
|
5695 |
|
|
.DQSOUTP (in_dq[2]),
|
5696 |
|
|
.SDO(),
|
5697 |
|
|
.TOUT (t_dq[2]),
|
5698 |
|
|
.ADD (ioi_drp_add),
|
5699 |
|
|
.AUXADDR (ioi_drp_addr),
|
5700 |
|
|
.AUXSDOIN (aux_sdi_out_3),
|
5701 |
|
|
.BKST (ioi_drp_broadcast),
|
5702 |
|
|
.CLK (ioi_drp_clk),
|
5703 |
|
|
.CS (ioi_drp_cs),
|
5704 |
|
|
.IDATAIN (in_pre_dq[2]),
|
5705 |
|
|
.IOCLK0 (ioclk90),
|
5706 |
|
|
.IOCLK1(),
|
5707 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5708 |
|
|
.ODATAIN (dq_oq[2]),
|
5709 |
|
|
.SDI (ioi_drp_sdo),
|
5710 |
|
|
.T (dq_tq[2])
|
5711 |
|
|
);
|
5712 |
|
|
|
5713 |
|
|
|
5714 |
|
|
/////////////////////////////////////////////////
|
5715 |
|
|
//DQ3
|
5716 |
|
|
////////////////////////////////////////////////
|
5717 |
|
|
IODRP2_MCB #(
|
5718 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5719 |
|
|
.IDELAY_VALUE (DQ3_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5720 |
|
|
.MCB_ADDRESS (1), // 0 to 15
|
5721 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5722 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
5723 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5724 |
|
|
|
5725 |
|
|
)
|
5726 |
|
|
iodrp2_dq_3
|
5727 |
|
|
(
|
5728 |
|
|
.AUXSDO (aux_sdi_out_3),
|
5729 |
|
|
.DATAOUT(),
|
5730 |
|
|
.DATAOUT2(),
|
5731 |
|
|
.DOUT (ioi_dq[3]),
|
5732 |
|
|
.DQSOUTN(),
|
5733 |
|
|
.DQSOUTP (in_dq[3]),
|
5734 |
|
|
.SDO(),
|
5735 |
|
|
.TOUT (t_dq[3]),
|
5736 |
|
|
.ADD (ioi_drp_add),
|
5737 |
|
|
.AUXADDR (ioi_drp_addr),
|
5738 |
|
|
.AUXSDOIN (aux_sdi_out_0),
|
5739 |
|
|
.BKST (ioi_drp_broadcast),
|
5740 |
|
|
.CLK (ioi_drp_clk),
|
5741 |
|
|
.CS (ioi_drp_cs),
|
5742 |
|
|
.IDATAIN (in_pre_dq[3]),
|
5743 |
|
|
.IOCLK0 (ioclk90),
|
5744 |
|
|
.IOCLK1(),
|
5745 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5746 |
|
|
.ODATAIN (dq_oq[3]),
|
5747 |
|
|
.SDI (ioi_drp_sdo),
|
5748 |
|
|
.T (dq_tq[3])
|
5749 |
|
|
);
|
5750 |
|
|
|
5751 |
|
|
|
5752 |
|
|
wire aux_sdi_out_dqsp;
|
5753 |
|
|
wire aux_sdi_out_dqsn;
|
5754 |
|
|
/////////
|
5755 |
|
|
//DQSP
|
5756 |
|
|
/////////
|
5757 |
|
|
IODRP2_MCB #(
|
5758 |
|
|
.DATA_RATE (C_DQS_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5759 |
|
|
.IDELAY_VALUE (LDQSP_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5760 |
|
|
.MCB_ADDRESS (15), // 0 to 15
|
5761 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5762 |
|
|
.SERDES_MODE (C_DQS_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
5763 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5764 |
|
|
|
5765 |
|
|
)
|
5766 |
|
|
iodrp2_dqsp_0
|
5767 |
|
|
(
|
5768 |
|
|
.AUXSDO (aux_sdi_out_dqsp),
|
5769 |
|
|
.DATAOUT(),
|
5770 |
|
|
.DATAOUT2(),
|
5771 |
|
|
.DOUT (ioi_dqs),
|
5772 |
|
|
.DQSOUTN(),
|
5773 |
|
|
.DQSOUTP (idelay_dqs_ioi_m),
|
5774 |
|
|
.SDO(),
|
5775 |
|
|
.TOUT (t_dqs),
|
5776 |
|
|
.ADD (ioi_drp_add),
|
5777 |
|
|
.AUXADDR (ioi_drp_addr),
|
5778 |
|
|
.AUXSDOIN (aux_sdi_out_dqsn),
|
5779 |
|
|
.BKST (ioi_drp_broadcast),
|
5780 |
|
|
.CLK (ioi_drp_clk),
|
5781 |
|
|
.CS (ioi_drp_cs),
|
5782 |
|
|
.IDATAIN (in_pre_dqsp),
|
5783 |
|
|
.IOCLK0 (ioclk0),
|
5784 |
|
|
.IOCLK1(),
|
5785 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5786 |
|
|
.ODATAIN (dqsp_oq),
|
5787 |
|
|
.SDI (ioi_drp_sdo),
|
5788 |
|
|
.T (dqsp_tq)
|
5789 |
|
|
);
|
5790 |
|
|
|
5791 |
|
|
/////////
|
5792 |
|
|
//DQSN
|
5793 |
|
|
/////////
|
5794 |
|
|
IODRP2_MCB #(
|
5795 |
|
|
.DATA_RATE (C_DQS_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5796 |
|
|
.IDELAY_VALUE (LDQSN_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5797 |
|
|
.MCB_ADDRESS (15), // 0 to 15
|
5798 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5799 |
|
|
.SERDES_MODE (C_DQS_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
5800 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5801 |
|
|
|
5802 |
|
|
)
|
5803 |
|
|
iodrp2_dqsn_0
|
5804 |
|
|
(
|
5805 |
|
|
.AUXSDO (aux_sdi_out_dqsn),
|
5806 |
|
|
.DATAOUT(),
|
5807 |
|
|
.DATAOUT2(),
|
5808 |
|
|
.DOUT (ioi_dqsn),
|
5809 |
|
|
.DQSOUTN(),
|
5810 |
|
|
.DQSOUTP (idelay_dqs_ioi_s),
|
5811 |
|
|
.SDO(),
|
5812 |
|
|
.TOUT (t_dqsn),
|
5813 |
|
|
.ADD (ioi_drp_add),
|
5814 |
|
|
.AUXADDR (ioi_drp_addr),
|
5815 |
|
|
.AUXSDOIN (aux_sdi_out_2),
|
5816 |
|
|
.BKST (ioi_drp_broadcast),
|
5817 |
|
|
.CLK (ioi_drp_clk),
|
5818 |
|
|
.CS (ioi_drp_cs),
|
5819 |
|
|
.IDATAIN (in_pre_dqsp),
|
5820 |
|
|
.IOCLK0 (ioclk0),
|
5821 |
|
|
.IOCLK1(),
|
5822 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5823 |
|
|
.ODATAIN (dqsn_oq),
|
5824 |
|
|
.SDI (ioi_drp_sdo),
|
5825 |
|
|
.T (dqsn_tq)
|
5826 |
|
|
);
|
5827 |
|
|
|
5828 |
|
|
wire aux_sdi_out_6;
|
5829 |
|
|
wire aux_sdi_out_7;
|
5830 |
|
|
/////////////////////////////////////////////////
|
5831 |
|
|
//DQ6
|
5832 |
|
|
////////////////////////////////////////////////
|
5833 |
|
|
IODRP2_MCB #(
|
5834 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5835 |
|
|
.IDELAY_VALUE (DQ6_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5836 |
|
|
.MCB_ADDRESS (3), // 0 to 15
|
5837 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5838 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
5839 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5840 |
|
|
|
5841 |
|
|
)
|
5842 |
|
|
iodrp2_dq_6
|
5843 |
|
|
(
|
5844 |
|
|
.AUXSDO (aux_sdi_out_6),
|
5845 |
|
|
.DATAOUT(),
|
5846 |
|
|
.DATAOUT2(),
|
5847 |
|
|
.DOUT (ioi_dq[6]),
|
5848 |
|
|
.DQSOUTN(),
|
5849 |
|
|
.DQSOUTP (in_dq[6]),
|
5850 |
|
|
.SDO(),
|
5851 |
|
|
.TOUT (t_dq[6]),
|
5852 |
|
|
.ADD (ioi_drp_add),
|
5853 |
|
|
.AUXADDR (ioi_drp_addr),
|
5854 |
|
|
.AUXSDOIN (aux_sdi_out_7),
|
5855 |
|
|
.BKST (ioi_drp_broadcast),
|
5856 |
|
|
.CLK (ioi_drp_clk),
|
5857 |
|
|
.CS (ioi_drp_cs),
|
5858 |
|
|
.IDATAIN (in_pre_dq[6]),
|
5859 |
|
|
.IOCLK0 (ioclk90),
|
5860 |
|
|
.IOCLK1(),
|
5861 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5862 |
|
|
.ODATAIN (dq_oq[6]),
|
5863 |
|
|
.SDI (ioi_drp_sdo),
|
5864 |
|
|
.T (dq_tq[6])
|
5865 |
|
|
);
|
5866 |
|
|
|
5867 |
|
|
/////////////////////////////////////////////////
|
5868 |
|
|
//DQ7
|
5869 |
|
|
////////////////////////////////////////////////
|
5870 |
|
|
IODRP2_MCB #(
|
5871 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5872 |
|
|
.IDELAY_VALUE (DQ7_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5873 |
|
|
.MCB_ADDRESS (3), // 0 to 15
|
5874 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5875 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
5876 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5877 |
|
|
|
5878 |
|
|
)
|
5879 |
|
|
iodrp2_dq_7
|
5880 |
|
|
(
|
5881 |
|
|
.AUXSDO (aux_sdi_out_7),
|
5882 |
|
|
.DATAOUT(),
|
5883 |
|
|
.DATAOUT2(),
|
5884 |
|
|
.DOUT (ioi_dq[7]),
|
5885 |
|
|
.DQSOUTN(),
|
5886 |
|
|
.DQSOUTP (in_dq[7]),
|
5887 |
|
|
.SDO(),
|
5888 |
|
|
.TOUT (t_dq[7]),
|
5889 |
|
|
.ADD (ioi_drp_add),
|
5890 |
|
|
.AUXADDR (ioi_drp_addr),
|
5891 |
|
|
.AUXSDOIN (aux_sdi_out_dqsp),
|
5892 |
|
|
.BKST (ioi_drp_broadcast),
|
5893 |
|
|
.CLK (ioi_drp_clk),
|
5894 |
|
|
.CS (ioi_drp_cs),
|
5895 |
|
|
.IDATAIN (in_pre_dq[7]),
|
5896 |
|
|
.IOCLK0 (ioclk90),
|
5897 |
|
|
.IOCLK1(),
|
5898 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5899 |
|
|
.ODATAIN (dq_oq[7]),
|
5900 |
|
|
.SDI (ioi_drp_sdo),
|
5901 |
|
|
.T (dq_tq[7])
|
5902 |
|
|
);
|
5903 |
|
|
|
5904 |
|
|
|
5905 |
|
|
|
5906 |
|
|
wire aux_sdi_out_4;
|
5907 |
|
|
wire aux_sdi_out_5;
|
5908 |
|
|
/////////////////////////////////////////////////
|
5909 |
|
|
//DQ4
|
5910 |
|
|
////////////////////////////////////////////////
|
5911 |
|
|
IODRP2_MCB #(
|
5912 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5913 |
|
|
.IDELAY_VALUE (DQ4_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5914 |
|
|
.MCB_ADDRESS (2), // 0 to 15
|
5915 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5916 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
5917 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5918 |
|
|
|
5919 |
|
|
)
|
5920 |
|
|
iodrp2_dq_4
|
5921 |
|
|
(
|
5922 |
|
|
.AUXSDO (aux_sdi_out_4),
|
5923 |
|
|
.DATAOUT(),
|
5924 |
|
|
.DATAOUT2(),
|
5925 |
|
|
.DOUT (ioi_dq[4]),
|
5926 |
|
|
.DQSOUTN(),
|
5927 |
|
|
.DQSOUTP (in_dq[4]),
|
5928 |
|
|
.SDO(),
|
5929 |
|
|
.TOUT (t_dq[4]),
|
5930 |
|
|
.ADD (ioi_drp_add),
|
5931 |
|
|
.AUXADDR (ioi_drp_addr),
|
5932 |
|
|
.AUXSDOIN (aux_sdi_out_5),
|
5933 |
|
|
.BKST (ioi_drp_broadcast),
|
5934 |
|
|
.CLK (ioi_drp_clk),
|
5935 |
|
|
.CS (ioi_drp_cs),
|
5936 |
|
|
.IDATAIN (in_pre_dq[4]),
|
5937 |
|
|
.IOCLK0 (ioclk90),
|
5938 |
|
|
.IOCLK1(),
|
5939 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5940 |
|
|
.ODATAIN (dq_oq[4]),
|
5941 |
|
|
.SDI (ioi_drp_sdo),
|
5942 |
|
|
.T (dq_tq[4])
|
5943 |
|
|
);
|
5944 |
|
|
|
5945 |
|
|
/////////////////////////////////////////////////
|
5946 |
|
|
//DQ5
|
5947 |
|
|
////////////////////////////////////////////////
|
5948 |
|
|
IODRP2_MCB #(
|
5949 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5950 |
|
|
.IDELAY_VALUE (DQ5_TAP_DELAY_VAL), // 0 to 255 inclusive
|
5951 |
|
|
.MCB_ADDRESS (2), // 0 to 15
|
5952 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5953 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
5954 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5955 |
|
|
|
5956 |
|
|
)
|
5957 |
|
|
iodrp2_dq_5
|
5958 |
|
|
(
|
5959 |
|
|
.AUXSDO (aux_sdi_out_5),
|
5960 |
|
|
.DATAOUT(),
|
5961 |
|
|
.DATAOUT2(),
|
5962 |
|
|
.DOUT (ioi_dq[5]),
|
5963 |
|
|
.DQSOUTN(),
|
5964 |
|
|
.DQSOUTP (in_dq[5]),
|
5965 |
|
|
.SDO(),
|
5966 |
|
|
.TOUT (t_dq[5]),
|
5967 |
|
|
.ADD (ioi_drp_add),
|
5968 |
|
|
.AUXADDR (ioi_drp_addr),
|
5969 |
|
|
.AUXSDOIN (aux_sdi_out_6),
|
5970 |
|
|
.BKST (ioi_drp_broadcast),
|
5971 |
|
|
.CLK (ioi_drp_clk),
|
5972 |
|
|
.CS (ioi_drp_cs),
|
5973 |
|
|
.IDATAIN (in_pre_dq[5]),
|
5974 |
|
|
.IOCLK0 (ioclk90),
|
5975 |
|
|
.IOCLK1(),
|
5976 |
|
|
.MEMUPDATE (ioi_drp_update),
|
5977 |
|
|
.ODATAIN (dq_oq[5]),
|
5978 |
|
|
.SDI (ioi_drp_sdo),
|
5979 |
|
|
.T (dq_tq[5])
|
5980 |
|
|
);
|
5981 |
|
|
|
5982 |
|
|
//NEED TO GENERATE UDM so that user won't instantiate in this location
|
5983 |
|
|
//wire aux_sdi_out_udm;
|
5984 |
|
|
wire aux_sdi_out_ldm;
|
5985 |
|
|
/////////////////////////////////////////////////
|
5986 |
|
|
//UDM
|
5987 |
|
|
////////////////////////////////////////////////
|
5988 |
|
|
IODRP2_MCB #(
|
5989 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
5990 |
|
|
.IDELAY_VALUE (0), // 0 to 255 inclusive
|
5991 |
|
|
.MCB_ADDRESS (8), // 0 to 15
|
5992 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
5993 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
5994 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
5995 |
|
|
|
5996 |
|
|
)
|
5997 |
|
|
iodrp2_dq_udm
|
5998 |
|
|
(
|
5999 |
|
|
.AUXSDO (ioi_drp_sdi),
|
6000 |
|
|
.DATAOUT(),
|
6001 |
|
|
.DATAOUT2(),
|
6002 |
|
|
.DOUT (ioi_udm),
|
6003 |
|
|
.DQSOUTN(),
|
6004 |
|
|
.DQSOUTP(),
|
6005 |
|
|
.SDO(),
|
6006 |
|
|
.TOUT (t_udm),
|
6007 |
|
|
.ADD (ioi_drp_add),
|
6008 |
|
|
.AUXADDR (ioi_drp_addr),
|
6009 |
|
|
.AUXSDOIN (aux_sdi_out_ldm),
|
6010 |
|
|
.BKST (ioi_drp_broadcast),
|
6011 |
|
|
.CLK (ioi_drp_clk),
|
6012 |
|
|
.CS (ioi_drp_cs),
|
6013 |
|
|
.IDATAIN(),
|
6014 |
|
|
.IOCLK0 (ioclk90),
|
6015 |
|
|
.IOCLK1(),
|
6016 |
|
|
.MEMUPDATE (ioi_drp_update),
|
6017 |
|
|
.ODATAIN (udm_oq),
|
6018 |
|
|
.SDI (ioi_drp_sdo),
|
6019 |
|
|
.T (udm_t)
|
6020 |
|
|
);
|
6021 |
|
|
|
6022 |
|
|
|
6023 |
|
|
/////////////////////////////////////////////////
|
6024 |
|
|
//LDM
|
6025 |
|
|
////////////////////////////////////////////////
|
6026 |
|
|
IODRP2_MCB #(
|
6027 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
6028 |
|
|
.IDELAY_VALUE (0), // 0 to 255 inclusive
|
6029 |
|
|
.MCB_ADDRESS (8), // 0 to 15
|
6030 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
6031 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
6032 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
6033 |
|
|
|
6034 |
|
|
)
|
6035 |
|
|
iodrp2_dq_ldm
|
6036 |
|
|
(
|
6037 |
|
|
.AUXSDO (aux_sdi_out_ldm),
|
6038 |
|
|
.DATAOUT(),
|
6039 |
|
|
.DATAOUT2(),
|
6040 |
|
|
.DOUT (ioi_ldm),
|
6041 |
|
|
.DQSOUTN(),
|
6042 |
|
|
.DQSOUTP(),
|
6043 |
|
|
.SDO(),
|
6044 |
|
|
.TOUT (t_ldm),
|
6045 |
|
|
.ADD (ioi_drp_add),
|
6046 |
|
|
.AUXADDR (ioi_drp_addr),
|
6047 |
|
|
.AUXSDOIN (aux_sdi_out_4),
|
6048 |
|
|
.BKST (ioi_drp_broadcast),
|
6049 |
|
|
.CLK (ioi_drp_clk),
|
6050 |
|
|
.CS (ioi_drp_cs),
|
6051 |
|
|
.IDATAIN(),
|
6052 |
|
|
.IOCLK0 (ioclk90),
|
6053 |
|
|
.IOCLK1(),
|
6054 |
|
|
.MEMUPDATE (ioi_drp_update),
|
6055 |
|
|
.ODATAIN (ldm_oq),
|
6056 |
|
|
.SDI (ioi_drp_sdo),
|
6057 |
|
|
.T (ldm_t)
|
6058 |
|
|
);
|
6059 |
|
|
end
|
6060 |
|
|
endgenerate
|
6061 |
|
|
|
6062 |
|
|
generate
|
6063 |
|
|
if(C_NUM_DQ_PINS == 4 ) begin : dq_3_0_data
|
6064 |
|
|
|
6065 |
|
|
wire aux_sdi_out_0;
|
6066 |
|
|
wire aux_sdi_out_1;
|
6067 |
|
|
/////////////////////////////////////////////////
|
6068 |
|
|
//DQ0
|
6069 |
|
|
////////////////////////////////////////////////
|
6070 |
|
|
IODRP2_MCB #(
|
6071 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
6072 |
|
|
.IDELAY_VALUE (DQ0_TAP_DELAY_VAL), // 0 to 255 inclusive
|
6073 |
|
|
.MCB_ADDRESS (0), // 0 to 15
|
6074 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
6075 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
6076 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
6077 |
|
|
|
6078 |
|
|
)
|
6079 |
|
|
iodrp2_dq_0
|
6080 |
|
|
(
|
6081 |
|
|
.AUXSDO (aux_sdi_out_0),
|
6082 |
|
|
.DATAOUT(),
|
6083 |
|
|
.DATAOUT2(),
|
6084 |
|
|
.DOUT (ioi_dq[0]),
|
6085 |
|
|
.DQSOUTN(),
|
6086 |
|
|
.DQSOUTP (in_dq[0]),
|
6087 |
|
|
.SDO(),
|
6088 |
|
|
.TOUT (t_dq[0]),
|
6089 |
|
|
.ADD (ioi_drp_add),
|
6090 |
|
|
.AUXADDR (ioi_drp_addr),
|
6091 |
|
|
.AUXSDOIN (aux_sdi_out_1),
|
6092 |
|
|
.BKST (ioi_drp_broadcast),
|
6093 |
|
|
.CLK (ioi_drp_clk),
|
6094 |
|
|
.CS (ioi_drp_cs),
|
6095 |
|
|
.IDATAIN (in_pre_dq[0]),
|
6096 |
|
|
.IOCLK0 (ioclk90),
|
6097 |
|
|
.IOCLK1(),
|
6098 |
|
|
.MEMUPDATE (ioi_drp_update),
|
6099 |
|
|
.ODATAIN (dq_oq[0]),
|
6100 |
|
|
.SDI (ioi_drp_sdo),
|
6101 |
|
|
.T (dq_tq[0])
|
6102 |
|
|
);
|
6103 |
|
|
|
6104 |
|
|
|
6105 |
|
|
/////////////////////////////////////////////////
|
6106 |
|
|
//DQ1
|
6107 |
|
|
////////////////////////////////////////////////
|
6108 |
|
|
IODRP2_MCB #(
|
6109 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
6110 |
|
|
.IDELAY_VALUE (DQ1_TAP_DELAY_VAL), // 0 to 255 inclusive
|
6111 |
|
|
.MCB_ADDRESS (0), // 0 to 15
|
6112 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
6113 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
6114 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
6115 |
|
|
|
6116 |
|
|
)
|
6117 |
|
|
iodrp2_dq_1
|
6118 |
|
|
(
|
6119 |
|
|
.AUXSDO (aux_sdi_out_1),
|
6120 |
|
|
.DATAOUT(),
|
6121 |
|
|
.DATAOUT2(),
|
6122 |
|
|
.DOUT (ioi_dq[1]),
|
6123 |
|
|
.DQSOUTN(),
|
6124 |
|
|
.DQSOUTP (in_dq[1]),
|
6125 |
|
|
.SDO(),
|
6126 |
|
|
.TOUT (t_dq[1]),
|
6127 |
|
|
.ADD (ioi_drp_add),
|
6128 |
|
|
.AUXADDR (ioi_drp_addr),
|
6129 |
|
|
.AUXSDOIN (1'b0),
|
6130 |
|
|
.BKST (ioi_drp_broadcast),
|
6131 |
|
|
.CLK (ioi_drp_clk),
|
6132 |
|
|
.CS (ioi_drp_cs),
|
6133 |
|
|
.IDATAIN (in_pre_dq[1]),
|
6134 |
|
|
.IOCLK0 (ioclk90),
|
6135 |
|
|
.IOCLK1(),
|
6136 |
|
|
.MEMUPDATE (ioi_drp_update),
|
6137 |
|
|
.ODATAIN (dq_oq[1]),
|
6138 |
|
|
.SDI (ioi_drp_sdo),
|
6139 |
|
|
.T (dq_tq[1])
|
6140 |
|
|
);
|
6141 |
|
|
|
6142 |
|
|
|
6143 |
|
|
wire aux_sdi_out_2;
|
6144 |
|
|
wire aux_sdi_out_3;
|
6145 |
|
|
/////////////////////////////////////////////////
|
6146 |
|
|
//DQ2
|
6147 |
|
|
////////////////////////////////////////////////
|
6148 |
|
|
IODRP2_MCB #(
|
6149 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
6150 |
|
|
.IDELAY_VALUE (DQ2_TAP_DELAY_VAL), // 0 to 255 inclusive
|
6151 |
|
|
.MCB_ADDRESS (1), // 0 to 15
|
6152 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
6153 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
6154 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
6155 |
|
|
|
6156 |
|
|
)
|
6157 |
|
|
iodrp2_dq_2
|
6158 |
|
|
(
|
6159 |
|
|
.AUXSDO (aux_sdi_out_2),
|
6160 |
|
|
.DATAOUT(),
|
6161 |
|
|
.DATAOUT2(),
|
6162 |
|
|
.DOUT (ioi_dq[2]),
|
6163 |
|
|
.DQSOUTN(),
|
6164 |
|
|
.DQSOUTP (in_dq[2]),
|
6165 |
|
|
.SDO(),
|
6166 |
|
|
.TOUT (t_dq[2]),
|
6167 |
|
|
.ADD (ioi_drp_add),
|
6168 |
|
|
.AUXADDR (ioi_drp_addr),
|
6169 |
|
|
.AUXSDOIN (aux_sdi_out_3),
|
6170 |
|
|
.BKST (ioi_drp_broadcast),
|
6171 |
|
|
.CLK (ioi_drp_clk),
|
6172 |
|
|
.CS (ioi_drp_cs),
|
6173 |
|
|
.IDATAIN (in_pre_dq[2]),
|
6174 |
|
|
.IOCLK0 (ioclk90),
|
6175 |
|
|
.IOCLK1(),
|
6176 |
|
|
.MEMUPDATE (ioi_drp_update),
|
6177 |
|
|
.ODATAIN (dq_oq[2]),
|
6178 |
|
|
.SDI (ioi_drp_sdo),
|
6179 |
|
|
.T (dq_tq[2])
|
6180 |
|
|
);
|
6181 |
|
|
|
6182 |
|
|
|
6183 |
|
|
/////////////////////////////////////////////////
|
6184 |
|
|
//DQ3
|
6185 |
|
|
////////////////////////////////////////////////
|
6186 |
|
|
IODRP2_MCB #(
|
6187 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
6188 |
|
|
.IDELAY_VALUE (DQ3_TAP_DELAY_VAL), // 0 to 255 inclusive
|
6189 |
|
|
.MCB_ADDRESS (1), // 0 to 15
|
6190 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
6191 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
6192 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
6193 |
|
|
|
6194 |
|
|
)
|
6195 |
|
|
iodrp2_dq_3
|
6196 |
|
|
(
|
6197 |
|
|
.AUXSDO (aux_sdi_out_3),
|
6198 |
|
|
.DATAOUT(),
|
6199 |
|
|
.DATAOUT2(),
|
6200 |
|
|
.DOUT (ioi_dq[3]),
|
6201 |
|
|
.DQSOUTN(),
|
6202 |
|
|
.DQSOUTP (in_dq[3]),
|
6203 |
|
|
.SDO(),
|
6204 |
|
|
.TOUT (t_dq[3]),
|
6205 |
|
|
.ADD (ioi_drp_add),
|
6206 |
|
|
.AUXADDR (ioi_drp_addr),
|
6207 |
|
|
.AUXSDOIN (aux_sdi_out_0),
|
6208 |
|
|
.BKST (ioi_drp_broadcast),
|
6209 |
|
|
.CLK (ioi_drp_clk),
|
6210 |
|
|
.CS (ioi_drp_cs),
|
6211 |
|
|
.IDATAIN (in_pre_dq[3]),
|
6212 |
|
|
.IOCLK0 (ioclk90),
|
6213 |
|
|
.IOCLK1(),
|
6214 |
|
|
.MEMUPDATE (ioi_drp_update),
|
6215 |
|
|
.ODATAIN (dq_oq[3]),
|
6216 |
|
|
.SDI (ioi_drp_sdo),
|
6217 |
|
|
.T (dq_tq[3])
|
6218 |
|
|
);
|
6219 |
|
|
|
6220 |
|
|
|
6221 |
|
|
wire aux_sdi_out_dqsp;
|
6222 |
|
|
wire aux_sdi_out_dqsn;
|
6223 |
|
|
/////////
|
6224 |
|
|
//DQSP
|
6225 |
|
|
/////////
|
6226 |
|
|
IODRP2_MCB #(
|
6227 |
|
|
.DATA_RATE (C_DQS_IODRP2_DATA_RATE), // "SDR", "DDR"
|
6228 |
|
|
.IDELAY_VALUE (LDQSP_TAP_DELAY_VAL), // 0 to 255 inclusive
|
6229 |
|
|
.MCB_ADDRESS (15), // 0 to 15
|
6230 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
6231 |
|
|
.SERDES_MODE (C_DQS_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
6232 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
6233 |
|
|
|
6234 |
|
|
)
|
6235 |
|
|
iodrp2_dqsp_0
|
6236 |
|
|
(
|
6237 |
|
|
.AUXSDO (aux_sdi_out_dqsp),
|
6238 |
|
|
.DATAOUT(),
|
6239 |
|
|
.DATAOUT2(),
|
6240 |
|
|
.DOUT (ioi_dqs),
|
6241 |
|
|
.DQSOUTN(),
|
6242 |
|
|
.DQSOUTP (idelay_dqs_ioi_m),
|
6243 |
|
|
.SDO(),
|
6244 |
|
|
.TOUT (t_dqs),
|
6245 |
|
|
.ADD (ioi_drp_add),
|
6246 |
|
|
.AUXADDR (ioi_drp_addr),
|
6247 |
|
|
.AUXSDOIN (aux_sdi_out_dqsn),
|
6248 |
|
|
.BKST (ioi_drp_broadcast),
|
6249 |
|
|
.CLK (ioi_drp_clk),
|
6250 |
|
|
.CS (ioi_drp_cs),
|
6251 |
|
|
.IDATAIN (in_pre_dqsp),
|
6252 |
|
|
.IOCLK0 (ioclk0),
|
6253 |
|
|
.IOCLK1(),
|
6254 |
|
|
.MEMUPDATE (ioi_drp_update),
|
6255 |
|
|
.ODATAIN (dqsp_oq),
|
6256 |
|
|
.SDI (ioi_drp_sdo),
|
6257 |
|
|
.T (dqsp_tq)
|
6258 |
|
|
);
|
6259 |
|
|
|
6260 |
|
|
/////////
|
6261 |
|
|
//DQSN
|
6262 |
|
|
/////////
|
6263 |
|
|
IODRP2_MCB #(
|
6264 |
|
|
.DATA_RATE (C_DQS_IODRP2_DATA_RATE), // "SDR", "DDR"
|
6265 |
|
|
.IDELAY_VALUE (LDQSN_TAP_DELAY_VAL), // 0 to 255 inclusive
|
6266 |
|
|
.MCB_ADDRESS (15), // 0 to 15
|
6267 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
6268 |
|
|
.SERDES_MODE (C_DQS_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
6269 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
6270 |
|
|
|
6271 |
|
|
)
|
6272 |
|
|
iodrp2_dqsn_0
|
6273 |
|
|
(
|
6274 |
|
|
.AUXSDO (aux_sdi_out_dqsn),
|
6275 |
|
|
.DATAOUT(),
|
6276 |
|
|
.DATAOUT2(),
|
6277 |
|
|
.DOUT (ioi_dqsn),
|
6278 |
|
|
.DQSOUTN(),
|
6279 |
|
|
.DQSOUTP (idelay_dqs_ioi_s),
|
6280 |
|
|
.SDO(),
|
6281 |
|
|
.TOUT (t_dqsn),
|
6282 |
|
|
.ADD (ioi_drp_add),
|
6283 |
|
|
.AUXADDR (ioi_drp_addr),
|
6284 |
|
|
.AUXSDOIN (aux_sdi_out_2),
|
6285 |
|
|
.BKST (ioi_drp_broadcast),
|
6286 |
|
|
.CLK (ioi_drp_clk),
|
6287 |
|
|
.CS (ioi_drp_cs),
|
6288 |
|
|
.IDATAIN (in_pre_dqsp),
|
6289 |
|
|
.IOCLK0 (ioclk0),
|
6290 |
|
|
.IOCLK1(),
|
6291 |
|
|
.MEMUPDATE (ioi_drp_update),
|
6292 |
|
|
.ODATAIN (dqsn_oq),
|
6293 |
|
|
.SDI (ioi_drp_sdo),
|
6294 |
|
|
.T (dqsn_tq)
|
6295 |
|
|
);
|
6296 |
|
|
|
6297 |
|
|
//NEED TO GENERATE UDM so that user won't instantiate in this location
|
6298 |
|
|
//wire aux_sdi_out_udm;
|
6299 |
|
|
wire aux_sdi_out_ldm;
|
6300 |
|
|
/////////////////////////////////////////////////
|
6301 |
|
|
//UDM
|
6302 |
|
|
////////////////////////////////////////////////
|
6303 |
|
|
IODRP2_MCB #(
|
6304 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
6305 |
|
|
.IDELAY_VALUE (0), // 0 to 255 inclusive
|
6306 |
|
|
.MCB_ADDRESS (8), // 0 to 15
|
6307 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
6308 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE"
|
6309 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
6310 |
|
|
|
6311 |
|
|
)
|
6312 |
|
|
iodrp2_dq_udm
|
6313 |
|
|
(
|
6314 |
|
|
.AUXSDO (ioi_drp_sdi),
|
6315 |
|
|
.DATAOUT(),
|
6316 |
|
|
.DATAOUT2(),
|
6317 |
|
|
.DOUT (ioi_udm),
|
6318 |
|
|
.DQSOUTN(),
|
6319 |
|
|
.DQSOUTP(),
|
6320 |
|
|
.SDO(),
|
6321 |
|
|
.TOUT (t_udm),
|
6322 |
|
|
.ADD (ioi_drp_add),
|
6323 |
|
|
.AUXADDR (ioi_drp_addr),
|
6324 |
|
|
.AUXSDOIN (aux_sdi_out_ldm),
|
6325 |
|
|
.BKST (ioi_drp_broadcast),
|
6326 |
|
|
.CLK (ioi_drp_clk),
|
6327 |
|
|
.CS (ioi_drp_cs),
|
6328 |
|
|
.IDATAIN(),
|
6329 |
|
|
.IOCLK0 (ioclk90),
|
6330 |
|
|
.IOCLK1(),
|
6331 |
|
|
.MEMUPDATE (ioi_drp_update),
|
6332 |
|
|
.ODATAIN (udm_oq),
|
6333 |
|
|
.SDI (ioi_drp_sdo),
|
6334 |
|
|
.T (udm_t)
|
6335 |
|
|
);
|
6336 |
|
|
|
6337 |
|
|
|
6338 |
|
|
/////////////////////////////////////////////////
|
6339 |
|
|
//LDM
|
6340 |
|
|
////////////////////////////////////////////////
|
6341 |
|
|
IODRP2_MCB #(
|
6342 |
|
|
.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR"
|
6343 |
|
|
.IDELAY_VALUE (0), // 0 to 255 inclusive
|
6344 |
|
|
.MCB_ADDRESS (8), // 0 to 15
|
6345 |
|
|
.ODELAY_VALUE (0), // 0 to 255 inclusive
|
6346 |
|
|
.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE"
|
6347 |
|
|
.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive
|
6348 |
|
|
|
6349 |
|
|
)
|
6350 |
|
|
iodrp2_dq_ldm
|
6351 |
|
|
(
|
6352 |
|
|
.AUXSDO (aux_sdi_out_ldm),
|
6353 |
|
|
.DATAOUT(),
|
6354 |
|
|
.DATAOUT2(),
|
6355 |
|
|
.DOUT (ioi_ldm),
|
6356 |
|
|
.DQSOUTN(),
|
6357 |
|
|
.DQSOUTP(),
|
6358 |
|
|
.SDO(),
|
6359 |
|
|
.TOUT (t_ldm),
|
6360 |
|
|
.ADD (ioi_drp_add),
|
6361 |
|
|
.AUXADDR (ioi_drp_addr),
|
6362 |
|
|
.AUXSDOIN (aux_sdi_out_4),
|
6363 |
|
|
.BKST (ioi_drp_broadcast),
|
6364 |
|
|
.CLK (ioi_drp_clk),
|
6365 |
|
|
.CS (ioi_drp_cs),
|
6366 |
|
|
.IDATAIN(),
|
6367 |
|
|
.IOCLK0 (ioclk90),
|
6368 |
|
|
.IOCLK1(),
|
6369 |
|
|
.MEMUPDATE (ioi_drp_update),
|
6370 |
|
|
.ODATAIN (ldm_oq),
|
6371 |
|
|
.SDI (ioi_drp_sdo),
|
6372 |
|
|
.T (ldm_t)
|
6373 |
|
|
);
|
6374 |
|
|
|
6375 |
|
|
end
|
6376 |
|
|
endgenerate
|
6377 |
|
|
|
6378 |
|
|
////////////////////////////////////////////////
|
6379 |
|
|
//IOBs instantiations
|
6380 |
|
|
// this part need more inputs from design team
|
6381 |
|
|
// for now just use as listed in fpga.v
|
6382 |
|
|
////////////////////////////////////////////////
|
6383 |
|
|
|
6384 |
|
|
|
6385 |
|
|
//// Address
|
6386 |
|
|
|
6387 |
|
|
genvar addr_i;
|
6388 |
|
|
generate
|
6389 |
|
|
for(addr_i = 0; addr_i < C_MEM_ADDR_WIDTH; addr_i = addr_i + 1) begin : gen_addr_obuft
|
6390 |
|
|
OBUFT iob_addr_inst
|
6391 |
|
|
(.I ( ioi_addr[addr_i]),
|
6392 |
|
|
.T ( t_addr[addr_i]),
|
6393 |
|
|
.O ( mcbx_dram_addr[addr_i])
|
6394 |
|
|
);
|
6395 |
|
|
end
|
6396 |
|
|
endgenerate
|
6397 |
|
|
|
6398 |
|
|
genvar ba_i;
|
6399 |
|
|
generate
|
6400 |
|
|
for(ba_i = 0; ba_i < C_MEM_BANKADDR_WIDTH; ba_i = ba_i + 1) begin : gen_ba_obuft
|
6401 |
|
|
OBUFT iob_ba_inst
|
6402 |
|
|
(.I ( ioi_ba[ba_i]),
|
6403 |
|
|
.T ( t_ba[ba_i]),
|
6404 |
|
|
.O ( mcbx_dram_ba[ba_i])
|
6405 |
|
|
);
|
6406 |
|
|
end
|
6407 |
|
|
endgenerate
|
6408 |
|
|
|
6409 |
|
|
|
6410 |
|
|
|
6411 |
|
|
// DRAM Control
|
6412 |
|
|
OBUFT iob_ras (.O(mcbx_dram_ras_n),.I(ioi_ras),.T(t_ras));
|
6413 |
|
|
OBUFT iob_cas (.O(mcbx_dram_cas_n),.I(ioi_cas),.T(t_cas));
|
6414 |
|
|
OBUFT iob_we (.O(mcbx_dram_we_n ),.I(ioi_we ),.T(t_we ));
|
6415 |
|
|
OBUFT iob_cke (.O(mcbx_dram_cke),.I(ioi_cke),.T(t_cke));
|
6416 |
|
|
|
6417 |
|
|
generate
|
6418 |
|
|
if (C_MEM_TYPE == "DDR3") begin : gen_ddr3_rst
|
6419 |
|
|
OBUFT iob_rst (.O(mcbx_dram_ddr3_rst),.I(ioi_rst),.T(t_rst));
|
6420 |
|
|
end
|
6421 |
|
|
endgenerate
|
6422 |
|
|
generate
|
6423 |
|
|
if((C_MEM_TYPE == "DDR3" && (C_MEM_DDR3_RTT != "OFF" || C_MEM_DDR3_DYN_WRT_ODT != "OFF"))
|
6424 |
|
|
||(C_MEM_TYPE == "DDR2" && C_MEM_DDR2_RTT != "OFF") ) begin : gen_dram_odt
|
6425 |
|
|
OBUFT iob_odt (.O(mcbx_dram_odt),.I(ioi_odt),.T(t_odt));
|
6426 |
|
|
end
|
6427 |
|
|
endgenerate
|
6428 |
|
|
|
6429 |
|
|
// Clock
|
6430 |
|
|
OBUFTDS iob_clk (.I(ioi_ck), .T(t_ck), .O(mcbx_dram_clk), .OB(mcbx_dram_clk_n));
|
6431 |
|
|
|
6432 |
|
|
//DQ
|
6433 |
|
|
genvar dq_i;
|
6434 |
|
|
generate
|
6435 |
|
|
for(dq_i = 0; dq_i < C_NUM_DQ_PINS; dq_i = dq_i + 1) begin : gen_dq_iobuft
|
6436 |
|
|
IOBUF gen_iob_dq_inst (.IO(mcbx_dram_dq[dq_i]),.I(ioi_dq[dq_i]),.T(t_dq[dq_i]),.O(in_pre_dq[dq_i]));
|
6437 |
|
|
end
|
6438 |
|
|
endgenerate
|
6439 |
|
|
|
6440 |
|
|
|
6441 |
|
|
// DQS
|
6442 |
|
|
generate
|
6443 |
|
|
if(C_MEM_TYPE == "DDR" || C_MEM_TYPE =="MDDR" || (C_MEM_TYPE == "DDR2" && (C_MEM_DDR2_DIFF_DQS_EN == "NO"))) begin: gen_dqs_iobuf
|
6444 |
|
|
IOBUF iob_dqs (.IO(mcbx_dram_dqs), .I(ioi_dqs),.T(t_dqs),.O(in_pre_dqsp));
|
6445 |
|
|
end else begin: gen_dqs_iobufds
|
6446 |
|
|
IOBUFDS iob_dqs (.IO(mcbx_dram_dqs),.IOB(mcbx_dram_dqs_n), .I(ioi_dqs),.T(t_dqs),.O(in_pre_dqsp));
|
6447 |
|
|
|
6448 |
|
|
end
|
6449 |
|
|
endgenerate
|
6450 |
|
|
|
6451 |
|
|
generate
|
6452 |
|
|
if((C_MEM_TYPE == "DDR" || C_MEM_TYPE =="MDDR" || (C_MEM_TYPE == "DDR2" && (C_MEM_DDR2_DIFF_DQS_EN == "NO"))) && C_NUM_DQ_PINS == 16) begin: gen_udqs_iobuf
|
6453 |
|
|
IOBUF iob_udqs (.IO(mcbx_dram_udqs), .I(ioi_udqs),.T(t_udqs),.O(in_pre_udqsp));
|
6454 |
|
|
end else if(C_NUM_DQ_PINS == 16) begin: gen_udqs_iobufds
|
6455 |
|
|
IOBUFDS iob_udqs (.IO(mcbx_dram_udqs),.IOB(mcbx_dram_udqs_n), .I(ioi_udqs),.T(t_udqs),.O(in_pre_udqsp));
|
6456 |
|
|
|
6457 |
|
|
end
|
6458 |
|
|
endgenerate
|
6459 |
|
|
|
6460 |
|
|
// DQS PULLDWON
|
6461 |
|
|
generate
|
6462 |
|
|
if(C_MEM_TYPE == "DDR" || C_MEM_TYPE =="MDDR" || (C_MEM_TYPE == "DDR2" && (C_MEM_DDR2_DIFF_DQS_EN == "NO"))) begin: gen_dqs_pullupdn
|
6463 |
|
|
PULLDOWN dqs_pulldown (.O(mcbx_dram_dqs));
|
6464 |
|
|
end else begin: gen_dqs_pullupdn_ds
|
6465 |
|
|
PULLDOWN dqs_pulldown (.O(mcbx_dram_dqs));
|
6466 |
|
|
PULLUP dqs_n_pullup (.O(mcbx_dram_dqs_n));
|
6467 |
|
|
|
6468 |
|
|
end
|
6469 |
|
|
endgenerate
|
6470 |
|
|
|
6471 |
|
|
// DQSN PULLUP
|
6472 |
|
|
generate
|
6473 |
|
|
if((C_MEM_TYPE == "DDR" || C_MEM_TYPE =="MDDR" || (C_MEM_TYPE == "DDR2" && (C_MEM_DDR2_DIFF_DQS_EN == "NO"))) && C_NUM_DQ_PINS == 16) begin: gen_udqs_pullupdn
|
6474 |
|
|
PULLDOWN udqs_pulldown (.O(mcbx_dram_udqs));
|
6475 |
|
|
end else if(C_NUM_DQ_PINS == 16) begin: gen_udqs_pullupdn_ds
|
6476 |
|
|
PULLDOWN udqs_pulldown (.O(mcbx_dram_udqs));
|
6477 |
|
|
PULLUP udqs_n_pullup (.O(mcbx_dram_udqs_n));
|
6478 |
|
|
|
6479 |
|
|
end
|
6480 |
|
|
endgenerate
|
6481 |
|
|
|
6482 |
|
|
|
6483 |
|
|
|
6484 |
|
|
|
6485 |
|
|
//DM
|
6486 |
|
|
// datamask generation
|
6487 |
|
|
generate
|
6488 |
|
|
if( C_NUM_DQ_PINS == 16) begin : gen_udm
|
6489 |
|
|
OBUFT iob_udm (.I(ioi_udm), .T(t_udm), .O(mcbx_dram_udm));
|
6490 |
|
|
end
|
6491 |
|
|
endgenerate
|
6492 |
|
|
|
6493 |
|
|
OBUFT iob_ldm (.I(ioi_ldm), .T(t_ldm), .O(mcbx_dram_ldm));
|
6494 |
|
|
|
6495 |
|
|
endmodule
|
6496 |
|
|
|