OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [rtl/] [verilog/] [xilinx_ddr2/] [mcb_ui_top.v] - Blame information for rev 667

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 627 stekern 
//*****************************************************************************
2 
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
3 
//
4 
// This file contains confidential and proprietary information
5 
// of Xilinx, Inc. and is protected under U.S. and
6 
// international copyright and other intellectual property
7 
// laws.
8 
//
9 
// DISCLAIMER
10 
// This disclaimer is not a license and does not grant any
11 
// rights to the materials distributed herewith. Except as
12 
// otherwise provided in a valid license issued to you by
13 
// Xilinx, and to the maximum extent permitted by applicable
14 
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
15 
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
16 
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
17 
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
18 
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
19 
// (2) Xilinx shall not be liable (whether in contract or tort,
20 
// including negligence, or under any other theory of
21 
// liability) for any loss or damage of any kind or nature
22 
// related to, arising under or in connection with these
23 
// materials, including for any direct, or any indirect,
24 
// special, incidental, or consequential loss or damage
25 
// (including loss of data, profits, goodwill, or any type of
26 
// loss or damage suffered as a result of any action brought
27 
// by a third party) even if such damage or loss was
28 
// reasonably foreseeable or Xilinx had been advised of the
29 
// possibility of the same.
30 
//
31 
// CRITICAL APPLICATIONS
32 
// Xilinx products are not designed or intended to be fail-
33 
// safe, or for use in any application requiring fail-safe
34 
// performance, such as life-support or safety devices or
35 
// systems, Class III medical devices, nuclear facilities,
36 
// applications related to the deployment of airbags, or any
37 
// other applications that could lead to death, personal
38 
// injury, or severe property or environmental damage
39 
// (individually and collectively, "Critical
40 
// Applications"). Customer assumes the sole risk and
41 
// liability of any use of Xilinx products in Critical
42 
// Applications, subject only to applicable laws and
43 
// regulations governing limitations on product liability.
44 
//
45 
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
46 
// PART OF THIS FILE AT ALL TIMES.
47 
//
48 
//*****************************************************************************
49 
//Device: Spartan6
50 
//Design Name: DDR/DDR2/DDR3/LPDDR
51 
//Purpose:
52 
//Reference:
53 
//   This module instantiates the AXI bridges
54 
//
55 
//*****************************************************************************
56 
`timescale 1ps / 1ps
57 
 
58 
module mcb_ui_top #
59 
   (
60 
///////////////////////////////////////////////////////////////////////////////
61 
// Parameter Definitions
62 
///////////////////////////////////////////////////////////////////////////////
63 
   // Raw Wrapper Parameters
64 
   parameter         C_MEMCLK_PERIOD           = 2500,
65 
   parameter         C_PORT_ENABLE             = 6'b111111,
66 
   parameter         C_MEM_ADDR_ORDER          = "BANK_ROW_COLUMN",
67 
   parameter         C_ARB_ALGORITHM           = 0,
68 
   parameter         C_ARB_NUM_TIME_SLOTS      = 12,
69 
   parameter         C_ARB_TIME_SLOT_0         = 18'o012345,
70 
   parameter         C_ARB_TIME_SLOT_1         = 18'o123450,
71 
   parameter         C_ARB_TIME_SLOT_2         = 18'o234501,
72 
   parameter         C_ARB_TIME_SLOT_3         = 18'o345012,
73 
   parameter         C_ARB_TIME_SLOT_4         = 18'o450123,
74 
   parameter         C_ARB_TIME_SLOT_5         = 18'o501234,
75 
   parameter         C_ARB_TIME_SLOT_6         = 18'o012345,
76 
   parameter         C_ARB_TIME_SLOT_7         = 18'o123450,
77 
   parameter         C_ARB_TIME_SLOT_8         = 18'o234501,
78 
   parameter         C_ARB_TIME_SLOT_9         = 18'o345012,
79 
   parameter         C_ARB_TIME_SLOT_10        = 18'o450123,
80 
   parameter         C_ARB_TIME_SLOT_11        = 18'o501234,
81 
   parameter         C_PORT_CONFIG             = "B128",
82 
   parameter         C_MEM_TRAS                = 45000,
83 
   parameter         C_MEM_TRCD                = 12500,
84 
   parameter         C_MEM_TREFI               = 7800,
85 
   parameter         C_MEM_TRFC                = 127500,
86 
   parameter         C_MEM_TRP                 = 12500,
87 
   parameter         C_MEM_TWR                 = 15000,
88 
   parameter         C_MEM_TRTP                = 7500,
89 
   parameter         C_MEM_TWTR                = 7500,
90 
   parameter         C_NUM_DQ_PINS             = 8,
91 
   parameter         C_MEM_TYPE                = "DDR3",
92 
   parameter         C_MEM_DENSITY             = "512M",
93 
   parameter         C_MEM_BURST_LEN           = 8,
94 
   parameter         C_MEM_CAS_LATENCY         = 4,
95 
   parameter         C_MEM_ADDR_WIDTH          = 13,
96 
   parameter         C_MEM_BANKADDR_WIDTH      = 3,
97 
   parameter         C_MEM_NUM_COL_BITS        = 11,
98 
   parameter         C_MEM_DDR3_CAS_LATENCY    = 7,
99 
   parameter         C_MEM_MOBILE_PA_SR        = "FULL",
100 
   parameter         C_MEM_DDR1_2_ODS          = "FULL",
101 
   parameter         C_MEM_DDR3_ODS            = "DIV6",
102 
   parameter         C_MEM_DDR2_RTT            = "50OHMS",
103 
   parameter         C_MEM_DDR3_RTT            = "DIV2",
104 
   parameter         C_MEM_MDDR_ODS            = "FULL",
105 
   parameter         C_MEM_DDR2_DIFF_DQS_EN    = "YES",
106 
   parameter         C_MEM_DDR2_3_PA_SR        = "OFF",
107 
   parameter         C_MEM_DDR3_CAS_WR_LATENCY = 5,
108 
   parameter         C_MEM_DDR3_AUTO_SR        = "ENABLED",
109 
   parameter         C_MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL",
110 
   parameter         C_MEM_DDR3_DYN_WRT_ODT    = "OFF",
111 
   parameter         C_MEM_TZQINIT_MAXCNT      = 10'd512,
112 
   parameter         C_MC_CALIB_BYPASS         = "NO",
113 
   parameter         C_MC_CALIBRATION_RA       = 15'h0000,
114 
   parameter         C_MC_CALIBRATION_BA       = 3'h0,
115 
   parameter         C_CALIB_SOFT_IP           = "TRUE",
116 
   parameter         C_SKIP_IN_TERM_CAL        = 1'b0,
117 
   parameter         C_SKIP_DYNAMIC_CAL        = 1'b0,
118 
   parameter         C_SKIP_DYN_IN_TERM        = 1'b1,
119 
   parameter         LDQSP_TAP_DELAY_VAL       = 0,
120 
   parameter         UDQSP_TAP_DELAY_VAL       = 0,
121 
   parameter         LDQSN_TAP_DELAY_VAL       = 0,
122 
   parameter         UDQSN_TAP_DELAY_VAL       = 0,
123 
   parameter         DQ0_TAP_DELAY_VAL         = 0,
124 
   parameter         DQ1_TAP_DELAY_VAL         = 0,
125 
   parameter         DQ2_TAP_DELAY_VAL         = 0,
126 
   parameter         DQ3_TAP_DELAY_VAL         = 0,
127 
   parameter         DQ4_TAP_DELAY_VAL         = 0,
128 
   parameter         DQ5_TAP_DELAY_VAL         = 0,
129 
   parameter         DQ6_TAP_DELAY_VAL         = 0,
130 
   parameter         DQ7_TAP_DELAY_VAL         = 0,
131 
   parameter         DQ8_TAP_DELAY_VAL         = 0,
132 
   parameter         DQ9_TAP_DELAY_VAL         = 0,
133 
   parameter         DQ10_TAP_DELAY_VAL        = 0,
134 
   parameter         DQ11_TAP_DELAY_VAL        = 0,
135 
   parameter         DQ12_TAP_DELAY_VAL        = 0,
136 
   parameter         DQ13_TAP_DELAY_VAL        = 0,
137 
   parameter         DQ14_TAP_DELAY_VAL        = 0,
138 
   parameter         DQ15_TAP_DELAY_VAL        = 0,
139 
   parameter         C_MC_CALIBRATION_CA       = 12'h000,
140 
   parameter         C_MC_CALIBRATION_CLK_DIV  = 1,
141 
   parameter         C_MC_CALIBRATION_MODE     = "CALIBRATION",
142 
   parameter         C_MC_CALIBRATION_DELAY    = "HALF",
143 
   parameter         C_SIMULATION              = "FALSE",
144 
   parameter         C_P0_MASK_SIZE            = 4,
145 
   parameter         C_P0_DATA_PORT_SIZE       = 32,
146 
   parameter         C_P1_MASK_SIZE            = 4,
147 
   parameter         C_P1_DATA_PORT_SIZE       = 32,
148 
   parameter integer C_MCB_USE_EXTERNAL_BUFPLL = 1,
149 
   // AXI Parameters
150 
   parameter         C_S0_AXI_BASEADDR         = 32'h00000000,
151 
   parameter         C_S0_AXI_HIGHADDR         = 32'h00000000,
152 
   parameter integer C_S0_AXI_ENABLE           = 0,
153 
   parameter integer C_S0_AXI_ID_WIDTH         = 4,
154 
   parameter integer C_S0_AXI_ADDR_WIDTH       = 64,
155 
   parameter integer C_S0_AXI_DATA_WIDTH       = 32,
156 
   parameter integer C_S0_AXI_SUPPORTS_READ    = 1,
157 
   parameter integer C_S0_AXI_SUPPORTS_WRITE   = 1,
158 
   parameter integer C_S0_AXI_SUPPORTS_NARROW_BURST  = 1,
159 
   parameter         C_S0_AXI_REG_EN0          = 20'h00000,
160 
   parameter         C_S0_AXI_REG_EN1          = 20'h01000,
161 
   parameter integer C_S0_AXI_STRICT_COHERENCY = 1,
162 
   parameter integer C_S0_AXI_ENABLE_AP        = 0,
163 
   parameter         C_S1_AXI_BASEADDR         = 32'h00000000,
164 
   parameter         C_S1_AXI_HIGHADDR         = 32'h00000000,
165 
   parameter integer C_S1_AXI_ENABLE           = 0,
166 
   parameter integer C_S1_AXI_ID_WIDTH         = 4,
167 
   parameter integer C_S1_AXI_ADDR_WIDTH       = 64,
168 
   parameter integer C_S1_AXI_DATA_WIDTH       = 32,
169 
   parameter integer C_S1_AXI_SUPPORTS_READ    = 1,
170 
   parameter integer C_S1_AXI_SUPPORTS_WRITE   = 1,
171 
   parameter integer C_S1_AXI_SUPPORTS_NARROW_BURST  = 1,
172 
   parameter         C_S1_AXI_REG_EN0          = 20'h00000,
173 
   parameter         C_S1_AXI_REG_EN1          = 20'h01000,
174 
   parameter integer C_S1_AXI_STRICT_COHERENCY = 1,
175 
   parameter integer C_S1_AXI_ENABLE_AP        = 0,
176 
   parameter         C_S2_AXI_BASEADDR         = 32'h00000000,
177 
   parameter         C_S2_AXI_HIGHADDR         = 32'h00000000,
178 
   parameter integer C_S2_AXI_ENABLE           = 0,
179 
   parameter integer C_S2_AXI_ID_WIDTH         = 4,
180 
   parameter integer C_S2_AXI_ADDR_WIDTH       = 64,
181 
   parameter integer C_S2_AXI_DATA_WIDTH       = 32,
182 
   parameter integer C_S2_AXI_SUPPORTS_READ    = 1,
183 
   parameter integer C_S2_AXI_SUPPORTS_WRITE   = 1,
184 
   parameter integer C_S2_AXI_SUPPORTS_NARROW_BURST  = 1,
185 
   parameter         C_S2_AXI_REG_EN0          = 20'h00000,
186 
   parameter         C_S2_AXI_REG_EN1          = 20'h01000,
187 
   parameter integer C_S2_AXI_STRICT_COHERENCY = 1,
188 
   parameter integer C_S2_AXI_ENABLE_AP        = 0,
189 
   parameter         C_S3_AXI_BASEADDR         = 32'h00000000,
190 
   parameter         C_S3_AXI_HIGHADDR         = 32'h00000000,
191 
   parameter integer C_S3_AXI_ENABLE           = 0,
192 
   parameter integer C_S3_AXI_ID_WIDTH         = 4,
193 
   parameter integer C_S3_AXI_ADDR_WIDTH       = 64,
194 
   parameter integer C_S3_AXI_DATA_WIDTH       = 32,
195 
   parameter integer C_S3_AXI_SUPPORTS_READ    = 1,
196 
   parameter integer C_S3_AXI_SUPPORTS_WRITE   = 1,
197 
   parameter integer C_S3_AXI_SUPPORTS_NARROW_BURST  = 1,
198 
   parameter         C_S3_AXI_REG_EN0          = 20'h00000,
199 
   parameter         C_S3_AXI_REG_EN1          = 20'h01000,
200 
   parameter integer C_S3_AXI_STRICT_COHERENCY = 1,
201 
   parameter integer C_S3_AXI_ENABLE_AP        = 0,
202 
   parameter         C_S4_AXI_BASEADDR         = 32'h00000000,
203 
   parameter         C_S4_AXI_HIGHADDR         = 32'h00000000,
204 
   parameter integer C_S4_AXI_ENABLE           = 0,
205 
   parameter integer C_S4_AXI_ID_WIDTH         = 4,
206 
   parameter integer C_S4_AXI_ADDR_WIDTH       = 64,
207 
   parameter integer C_S4_AXI_DATA_WIDTH       = 32,
208 
   parameter integer C_S4_AXI_SUPPORTS_READ    = 1,
209 
   parameter integer C_S4_AXI_SUPPORTS_WRITE   = 1,
210 
   parameter integer C_S4_AXI_SUPPORTS_NARROW_BURST  = 1,
211 
   parameter         C_S4_AXI_REG_EN0          = 20'h00000,
212 
   parameter         C_S4_AXI_REG_EN1          = 20'h01000,
213 
   parameter integer C_S4_AXI_STRICT_COHERENCY = 1,
214 
   parameter integer C_S4_AXI_ENABLE_AP        = 0,
215 
   parameter         C_S5_AXI_BASEADDR         = 32'h00000000,
216 
   parameter         C_S5_AXI_HIGHADDR         = 32'h00000000,
217 
   parameter integer C_S5_AXI_ENABLE           = 0,
218 
   parameter integer C_S5_AXI_ID_WIDTH         = 4,
219 
   parameter integer C_S5_AXI_ADDR_WIDTH       = 64,
220 
   parameter integer C_S5_AXI_DATA_WIDTH       = 32,
221 
   parameter integer C_S5_AXI_SUPPORTS_READ    = 1,
222 
   parameter integer C_S5_AXI_SUPPORTS_WRITE   = 1,
223 
   parameter integer C_S5_AXI_SUPPORTS_NARROW_BURST  = 1,
224 
   parameter         C_S5_AXI_REG_EN0          = 20'h00000,
225 
   parameter         C_S5_AXI_REG_EN1          = 20'h01000,
226 
   parameter integer C_S5_AXI_STRICT_COHERENCY = 1,
227 
   parameter integer C_S5_AXI_ENABLE_AP        = 0
228 
   )
229 
   (
230 
///////////////////////////////////////////////////////////////////////////////
231 
// Port Declarations
232 
///////////////////////////////////////////////////////////////////////////////
233 
   // Raw Wrapper Signals
234 
   input                                     sysclk_2x          ,
235 
   input                                     sysclk_2x_180      ,
236 
   input                                     pll_ce_0           ,
237 
   input                                     pll_ce_90          ,
238 
   output                                    sysclk_2x_bufpll_o ,
239 
   output                                    sysclk_2x_180_bufpll_o,
240 
   output                                    pll_ce_0_bufpll_o  ,
241 
   output                                    pll_ce_90_bufpll_o ,
242 
   output                                    pll_lock_bufpll_o  ,
243 
   input                                     pll_lock           ,
244 
   input                                     sys_rst            ,
245 
   input                                     p0_arb_en          ,
246 
   input                                     p0_cmd_clk         ,
247 
   input                                     p0_cmd_en          ,
248 
   input       [2:0]                         p0_cmd_instr       ,
249 
   input       [5:0]                         p0_cmd_bl          ,
250 
   input       [29:0]                        p0_cmd_byte_addr   ,
251 
   output                                    p0_cmd_empty       ,
252 
   output                                    p0_cmd_full        ,
253 
   input                                     p0_wr_clk          ,
254 
   input                                     p0_wr_en           ,
255 
   input       [C_P0_MASK_SIZE-1:0]          p0_wr_mask         ,
256 
   input       [C_P0_DATA_PORT_SIZE-1:0]     p0_wr_data         ,
257 
   output                                    p0_wr_full         ,
258 
   output                                    p0_wr_empty        ,
259 
   output      [6:0]                         p0_wr_count        ,
260 
   output                                    p0_wr_underrun     ,
261 
   output                                    p0_wr_error        ,
262 
   input                                     p0_rd_clk          ,
263 
   input                                     p0_rd_en           ,
264 
   output      [C_P0_DATA_PORT_SIZE-1:0]     p0_rd_data         ,
265 
   output                                    p0_rd_full         ,
266 
   output                                    p0_rd_empty        ,
267 
   output      [6:0]                         p0_rd_count        ,
268 
   output                                    p0_rd_overflow     ,
269 
   output                                    p0_rd_error        ,
270 
   input                                     p1_arb_en          ,
271 
   input                                     p1_cmd_clk         ,
272 
   input                                     p1_cmd_en          ,
273 
   input       [2:0]                         p1_cmd_instr       ,
274 
   input       [5:0]                         p1_cmd_bl          ,
275 
   input       [29:0]                        p1_cmd_byte_addr   ,
276 
   output                                    p1_cmd_empty       ,
277 
   output                                    p1_cmd_full        ,
278 
   input                                     p1_wr_clk          ,
279 
   input                                     p1_wr_en           ,
280 
   input       [C_P1_MASK_SIZE-1:0]          p1_wr_mask         ,
281 
   input       [C_P1_DATA_PORT_SIZE-1:0]     p1_wr_data         ,
282 
   output                                    p1_wr_full         ,
283 
   output                                    p1_wr_empty        ,
284 
   output      [6:0]                         p1_wr_count        ,
285 
   output                                    p1_wr_underrun     ,
286 
   output                                    p1_wr_error        ,
287 
   input                                     p1_rd_clk          ,
288 
   input                                     p1_rd_en           ,
289 
   output      [C_P1_DATA_PORT_SIZE-1:0]     p1_rd_data         ,
290 
   output                                    p1_rd_full         ,
291 
   output                                    p1_rd_empty        ,
292 
   output      [6:0]                         p1_rd_count        ,
293 
   output                                    p1_rd_overflow     ,
294 
   output                                    p1_rd_error        ,
295 
   input                                     p2_arb_en          ,
296 
   input                                     p2_cmd_clk         ,
297 
   input                                     p2_cmd_en          ,
298 
   input       [2:0]                         p2_cmd_instr       ,
299 
   input       [5:0]                         p2_cmd_bl          ,
300 
   input       [29:0]                        p2_cmd_byte_addr   ,
301 
   output                                    p2_cmd_empty       ,
302 
   output                                    p2_cmd_full        ,
303 
   input                                     p2_wr_clk          ,
304 
   input                                     p2_wr_en           ,
305 
   input       [3:0]                         p2_wr_mask         ,
306 
   input       [31:0]                        p2_wr_data         ,
307 
   output                                    p2_wr_full         ,
308 
   output                                    p2_wr_empty        ,
309 
   output      [6:0]                         p2_wr_count        ,
310 
   output                                    p2_wr_underrun     ,
311 
   output                                    p2_wr_error        ,
312 
   input                                     p2_rd_clk          ,
313 
   input                                     p2_rd_en           ,
314 
   output      [31:0]                        p2_rd_data         ,
315 
   output                                    p2_rd_full         ,
316 
   output                                    p2_rd_empty        ,
317 
   output      [6:0]                         p2_rd_count        ,
318 
   output                                    p2_rd_overflow     ,
319 
   output                                    p2_rd_error        ,
320 
   input                                     p3_arb_en          ,
321 
   input                                     p3_cmd_clk         ,
322 
   input                                     p3_cmd_en          ,
323 
   input       [2:0]                         p3_cmd_instr       ,
324 
   input       [5:0]                         p3_cmd_bl          ,
325 
   input       [29:0]                        p3_cmd_byte_addr   ,
326 
   output                                    p3_cmd_empty       ,
327 
   output                                    p3_cmd_full        ,
328 
   input                                     p3_wr_clk          ,
329 
   input                                     p3_wr_en           ,
330 
   input       [3:0]                         p3_wr_mask         ,
331 
   input       [31:0]                        p3_wr_data         ,
332 
   output                                    p3_wr_full         ,
333 
   output                                    p3_wr_empty        ,
334 
   output      [6:0]                         p3_wr_count        ,
335 
   output                                    p3_wr_underrun     ,
336 
   output                                    p3_wr_error        ,
337 
   input                                     p3_rd_clk          ,
338 
   input                                     p3_rd_en           ,
339 
   output      [31:0]                        p3_rd_data         ,
340 
   output                                    p3_rd_full         ,
341 
   output                                    p3_rd_empty        ,
342 
   output      [6:0]                         p3_rd_count        ,
343 
   output                                    p3_rd_overflow     ,
344 
   output                                    p3_rd_error        ,
345 
   input                                     p4_arb_en          ,
346 
   input                                     p4_cmd_clk         ,
347 
   input                                     p4_cmd_en          ,
348 
   input       [2:0]                         p4_cmd_instr       ,
349 
   input       [5:0]                         p4_cmd_bl          ,
350 
   input       [29:0]                        p4_cmd_byte_addr   ,
351 
   output                                    p4_cmd_empty       ,
352 
   output                                    p4_cmd_full        ,
353 
   input                                     p4_wr_clk          ,
354 
   input                                     p4_wr_en           ,
355 
   input       [3:0]                         p4_wr_mask         ,
356 
   input       [31:0]                        p4_wr_data         ,
357 
   output                                    p4_wr_full         ,
358 
   output                                    p4_wr_empty        ,
359 
   output      [6:0]                         p4_wr_count        ,
360 
   output                                    p4_wr_underrun     ,
361 
   output                                    p4_wr_error        ,
362 
   input                                     p4_rd_clk          ,
363 
   input                                     p4_rd_en           ,
364 
   output      [31:0]                        p4_rd_data         ,
365 
   output                                    p4_rd_full         ,
366 
   output                                    p4_rd_empty        ,
367 
   output      [6:0]                         p4_rd_count        ,
368 
   output                                    p4_rd_overflow     ,
369 
   output                                    p4_rd_error        ,
370 
   input                                     p5_arb_en          ,
371 
   input                                     p5_cmd_clk         ,
372 
   input                                     p5_cmd_en          ,
373 
   input       [2:0]                         p5_cmd_instr       ,
374 
   input       [5:0]                         p5_cmd_bl          ,
375 
   input       [29:0]                        p5_cmd_byte_addr   ,
376 
   output                                    p5_cmd_empty       ,
377 
   output                                    p5_cmd_full        ,
378 
   input                                     p5_wr_clk          ,
379 
   input                                     p5_wr_en           ,
380 
   input       [3:0]                         p5_wr_mask         ,
381 
   input       [31:0]                        p5_wr_data         ,
382 
   output                                    p5_wr_full         ,
383 
   output                                    p5_wr_empty        ,
384 
   output      [6:0]                         p5_wr_count        ,
385 
   output                                    p5_wr_underrun     ,
386 
   output                                    p5_wr_error        ,
387 
   input                                     p5_rd_clk          ,
388 
   input                                     p5_rd_en           ,
389 
   output      [31:0]                        p5_rd_data         ,
390 
   output                                    p5_rd_full         ,
391 
   output                                    p5_rd_empty        ,
392 
   output      [6:0]                         p5_rd_count        ,
393 
   output                                    p5_rd_overflow     ,
394 
   output                                    p5_rd_error        ,
395 
   output      [C_MEM_ADDR_WIDTH-1:0]        mcbx_dram_addr     ,
396 
   output      [C_MEM_BANKADDR_WIDTH-1:0]    mcbx_dram_ba       ,
397 
   output                                    mcbx_dram_ras_n    ,
398 
   output                                    mcbx_dram_cas_n    ,
399 
   output                                    mcbx_dram_we_n     ,
400 
   output                                    mcbx_dram_cke      ,
401 
   output                                    mcbx_dram_clk      ,
402 
   output                                    mcbx_dram_clk_n    ,
403 
   inout       [C_NUM_DQ_PINS-1:0]           mcbx_dram_dq       ,
404 
   inout                                     mcbx_dram_dqs      ,
405 
   inout                                     mcbx_dram_dqs_n    ,
406 
   inout                                     mcbx_dram_udqs     ,
407 
   inout                                     mcbx_dram_udqs_n   ,
408 
   output                                    mcbx_dram_udm      ,
409 
   output                                    mcbx_dram_ldm      ,
410 
   output                                    mcbx_dram_odt      ,
411 
   output                                    mcbx_dram_ddr3_rst ,
412 
   input                                     calib_recal        ,
413 
   inout                                     rzq                ,
414 
   inout                                     zio                ,
415 
   input                                     ui_read            ,
416 
   input                                     ui_add             ,
417 
   input                                     ui_cs              ,
418 
   input                                     ui_clk             ,
419 
   input                                     ui_sdi             ,
420 
   input       [4:0]                         ui_addr            ,
421 
   input                                     ui_broadcast       ,
422 
   input                                     ui_drp_update      ,
423 
   input                                     ui_done_cal        ,
424 
   input                                     ui_cmd             ,
425 
   input                                     ui_cmd_in          ,
426 
   input                                     ui_cmd_en          ,
427 
   input       [3:0]                         ui_dqcount         ,
428 
   input                                     ui_dq_lower_dec    ,
429 
   input                                     ui_dq_lower_inc    ,
430 
   input                                     ui_dq_upper_dec    ,
431 
   input                                     ui_dq_upper_inc    ,
432 
   input                                     ui_udqs_inc        ,
433 
   input                                     ui_udqs_dec        ,
434 
   input                                     ui_ldqs_inc        ,
435 
   input                                     ui_ldqs_dec        ,
436 
   output      [7:0]                         uo_data            ,
437 
   output                                    uo_data_valid      ,
438 
   output                                    uo_done_cal        ,
439 
   output                                    uo_cmd_ready_in    ,
440 
   output                                    uo_refrsh_flag     ,
441 
   output                                    uo_cal_start       ,
442 
   output                                    uo_sdo             ,
443 
   output      [31:0]                        status             ,
444 
   input                                     selfrefresh_enter  ,
445 
   output                                    selfrefresh_mode   ,
446 
   // AXI Signals
447 
   input  wire                               s0_axi_aclk        ,
448 
   input  wire                               s0_axi_aresetn     ,
449 
   input  wire [C_S0_AXI_ID_WIDTH-1:0]       s0_axi_awid        ,
450 
   input  wire [C_S0_AXI_ADDR_WIDTH-1:0]     s0_axi_awaddr      ,
451 
   input  wire [7:0]                         s0_axi_awlen       ,
452 
   input  wire [2:0]                         s0_axi_awsize      ,
453 
   input  wire [1:0]                         s0_axi_awburst     ,
454 
   input  wire [0:0]                         s0_axi_awlock      ,
455 
   input  wire [3:0]                         s0_axi_awcache     ,
456 
   input  wire [2:0]                         s0_axi_awprot      ,
457 
   input  wire [3:0]                         s0_axi_awqos       ,
458 
   input  wire                               s0_axi_awvalid     ,
459 
   output wire                               s0_axi_awready     ,
460 
   input  wire [C_S0_AXI_DATA_WIDTH-1:0]     s0_axi_wdata       ,
461 
   input  wire [C_S0_AXI_DATA_WIDTH/8-1:0]   s0_axi_wstrb       ,
462 
   input  wire                               s0_axi_wlast       ,
463 
   input  wire                               s0_axi_wvalid      ,
464 
   output wire                               s0_axi_wready      ,
465 
   output wire [C_S0_AXI_ID_WIDTH-1:0]       s0_axi_bid         ,
466 
   output wire [1:0]                         s0_axi_bresp       ,
467 
   output wire                               s0_axi_bvalid      ,
468 
   input  wire                               s0_axi_bready      ,
469 
   input  wire [C_S0_AXI_ID_WIDTH-1:0]       s0_axi_arid        ,
470 
   input  wire [C_S0_AXI_ADDR_WIDTH-1:0]     s0_axi_araddr      ,
471 
   input  wire [7:0]                         s0_axi_arlen       ,
472 
   input  wire [2:0]                         s0_axi_arsize      ,
473 
   input  wire [1:0]                         s0_axi_arburst     ,
474 
   input  wire [0:0]                         s0_axi_arlock      ,
475 
   input  wire [3:0]                         s0_axi_arcache     ,
476 
   input  wire [2:0]                         s0_axi_arprot      ,
477 
   input  wire [3:0]                         s0_axi_arqos       ,
478 
   input  wire                               s0_axi_arvalid     ,
479 
   output wire                               s0_axi_arready     ,
480 
   output wire [C_S0_AXI_ID_WIDTH-1:0]       s0_axi_rid         ,
481 
   output wire [C_S0_AXI_DATA_WIDTH-1:0]     s0_axi_rdata       ,
482 
   output wire [1:0]                         s0_axi_rresp       ,
483 
   output wire                               s0_axi_rlast       ,
484 
   output wire                               s0_axi_rvalid      ,
485 
   input  wire                               s0_axi_rready      ,
486 
 
487 
   input  wire                               s1_axi_aclk        ,
488 
   input  wire                               s1_axi_aresetn     ,
489 
   input  wire [C_S1_AXI_ID_WIDTH-1:0]       s1_axi_awid        ,
490 
   input  wire [C_S1_AXI_ADDR_WIDTH-1:0]     s1_axi_awaddr      ,
491 
   input  wire [7:0]                         s1_axi_awlen       ,
492 
   input  wire [2:0]                         s1_axi_awsize      ,
493 
   input  wire [1:0]                         s1_axi_awburst     ,
494 
   input  wire [0:0]                         s1_axi_awlock      ,
495 
   input  wire [3:0]                         s1_axi_awcache     ,
496 
   input  wire [2:0]                         s1_axi_awprot      ,
497 
   input  wire [3:0]                         s1_axi_awqos       ,
498 
   input  wire                               s1_axi_awvalid     ,
499 
   output wire                               s1_axi_awready     ,
500 
   input  wire [C_S1_AXI_DATA_WIDTH-1:0]     s1_axi_wdata       ,
501 
   input  wire [C_S1_AXI_DATA_WIDTH/8-1:0]   s1_axi_wstrb       ,
502 
   input  wire                               s1_axi_wlast       ,
503 
   input  wire                               s1_axi_wvalid      ,
504 
   output wire                               s1_axi_wready      ,
505 
   output wire [C_S1_AXI_ID_WIDTH-1:0]       s1_axi_bid         ,
506 
   output wire [1:0]                         s1_axi_bresp       ,
507 
   output wire                               s1_axi_bvalid      ,
508 
   input  wire                               s1_axi_bready      ,
509 
   input  wire [C_S1_AXI_ID_WIDTH-1:0]       s1_axi_arid        ,
510 
   input  wire [C_S1_AXI_ADDR_WIDTH-1:0]     s1_axi_araddr      ,
511 
   input  wire [7:0]                         s1_axi_arlen       ,
512 
   input  wire [2:0]                         s1_axi_arsize      ,
513 
   input  wire [1:0]                         s1_axi_arburst     ,
514 
   input  wire [0:0]                         s1_axi_arlock      ,
515 
   input  wire [3:0]                         s1_axi_arcache     ,
516 
   input  wire [2:0]                         s1_axi_arprot      ,
517 
   input  wire [3:0]                         s1_axi_arqos       ,
518 
   input  wire                               s1_axi_arvalid     ,
519 
   output wire                               s1_axi_arready     ,
520 
   output wire [C_S1_AXI_ID_WIDTH-1:0]       s1_axi_rid         ,
521 
   output wire [C_S1_AXI_DATA_WIDTH-1:0]     s1_axi_rdata       ,
522 
   output wire [1:0]                         s1_axi_rresp       ,
523 
   output wire                               s1_axi_rlast       ,
524 
   output wire                               s1_axi_rvalid      ,
525 
   input  wire                               s1_axi_rready      ,
526 
 
527 
   input  wire                               s2_axi_aclk        ,
528 
   input  wire                               s2_axi_aresetn     ,
529 
   input  wire [C_S2_AXI_ID_WIDTH-1:0]       s2_axi_awid        ,
530 
   input  wire [C_S2_AXI_ADDR_WIDTH-1:0]     s2_axi_awaddr      ,
531 
   input  wire [7:0]                         s2_axi_awlen       ,
532 
   input  wire [2:0]                         s2_axi_awsize      ,
533 
   input  wire [1:0]                         s2_axi_awburst     ,
534 
   input  wire [0:0]                         s2_axi_awlock      ,
535 
   input  wire [3:0]                         s2_axi_awcache     ,
536 
   input  wire [2:0]                         s2_axi_awprot      ,
537 
   input  wire [3:0]                         s2_axi_awqos       ,
538 
   input  wire                               s2_axi_awvalid     ,
539 
   output wire                               s2_axi_awready     ,
540 
   input  wire [C_S2_AXI_DATA_WIDTH-1:0]     s2_axi_wdata       ,
541 
   input  wire [C_S2_AXI_DATA_WIDTH/8-1:0]   s2_axi_wstrb       ,
542 
   input  wire                               s2_axi_wlast       ,
543 
   input  wire                               s2_axi_wvalid      ,
544 
   output wire                               s2_axi_wready      ,
545 
   output wire [C_S2_AXI_ID_WIDTH-1:0]       s2_axi_bid         ,
546 
   output wire [1:0]                         s2_axi_bresp       ,
547 
   output wire                               s2_axi_bvalid      ,
548 
   input  wire                               s2_axi_bready      ,
549 
   input  wire [C_S2_AXI_ID_WIDTH-1:0]       s2_axi_arid        ,
550 
   input  wire [C_S2_AXI_ADDR_WIDTH-1:0]     s2_axi_araddr      ,
551 
   input  wire [7:0]                         s2_axi_arlen       ,
552 
   input  wire [2:0]                         s2_axi_arsize      ,
553 
   input  wire [1:0]                         s2_axi_arburst     ,
554 
   input  wire [0:0]                         s2_axi_arlock      ,
555 
   input  wire [3:0]                         s2_axi_arcache     ,
556 
   input  wire [2:0]                         s2_axi_arprot      ,
557 
   input  wire [3:0]                         s2_axi_arqos       ,
558 
   input  wire                               s2_axi_arvalid     ,
559 
   output wire                               s2_axi_arready     ,
560 
   output wire [C_S2_AXI_ID_WIDTH-1:0]       s2_axi_rid         ,
561 
   output wire [C_S2_AXI_DATA_WIDTH-1:0]     s2_axi_rdata       ,
562 
   output wire [1:0]                         s2_axi_rresp       ,
563 
   output wire                               s2_axi_rlast       ,
564 
   output wire                               s2_axi_rvalid      ,
565 
   input  wire                               s2_axi_rready      ,
566 
 
567 
   input  wire                               s3_axi_aclk        ,
568 
   input  wire                               s3_axi_aresetn     ,
569 
   input  wire [C_S3_AXI_ID_WIDTH-1:0]       s3_axi_awid        ,
570 
   input  wire [C_S3_AXI_ADDR_WIDTH-1:0]     s3_axi_awaddr      ,
571 
   input  wire [7:0]                         s3_axi_awlen       ,
572 
   input  wire [2:0]                         s3_axi_awsize      ,
573 
   input  wire [1:0]                         s3_axi_awburst     ,
574 
   input  wire [0:0]                         s3_axi_awlock      ,
575 
   input  wire [3:0]                         s3_axi_awcache     ,
576 
   input  wire [2:0]                         s3_axi_awprot      ,
577 
   input  wire [3:0]                         s3_axi_awqos       ,
578 
   input  wire                               s3_axi_awvalid     ,
579 
   output wire                               s3_axi_awready     ,
580 
   input  wire [C_S3_AXI_DATA_WIDTH-1:0]     s3_axi_wdata       ,
581 
   input  wire [C_S3_AXI_DATA_WIDTH/8-1:0]   s3_axi_wstrb       ,
582 
   input  wire                               s3_axi_wlast       ,
583 
   input  wire                               s3_axi_wvalid      ,
584 
   output wire                               s3_axi_wready      ,
585 
   output wire [C_S3_AXI_ID_WIDTH-1:0]       s3_axi_bid         ,
586 
   output wire [1:0]                         s3_axi_bresp       ,
587 
   output wire                               s3_axi_bvalid      ,
588 
   input  wire                               s3_axi_bready      ,
589 
   input  wire [C_S3_AXI_ID_WIDTH-1:0]       s3_axi_arid        ,
590 
   input  wire [C_S3_AXI_ADDR_WIDTH-1:0]     s3_axi_araddr      ,
591 
   input  wire [7:0]                         s3_axi_arlen       ,
592 
   input  wire [2:0]                         s3_axi_arsize      ,
593 
   input  wire [1:0]                         s3_axi_arburst     ,
594 
   input  wire [0:0]                         s3_axi_arlock      ,
595 
   input  wire [3:0]                         s3_axi_arcache     ,
596 
   input  wire [2:0]                         s3_axi_arprot      ,
597 
   input  wire [3:0]                         s3_axi_arqos       ,
598 
   input  wire                               s3_axi_arvalid     ,
599 
   output wire                               s3_axi_arready     ,
600 
   output wire [C_S3_AXI_ID_WIDTH-1:0]       s3_axi_rid         ,
601 
   output wire [C_S3_AXI_DATA_WIDTH-1:0]     s3_axi_rdata       ,
602 
   output wire [1:0]                         s3_axi_rresp       ,
603 
   output wire                               s3_axi_rlast       ,
604 
   output wire                               s3_axi_rvalid      ,
605 
   input  wire                               s3_axi_rready      ,
606 
 
607 
   input  wire                               s4_axi_aclk        ,
608 
   input  wire                               s4_axi_aresetn     ,
609 
   input  wire [C_S4_AXI_ID_WIDTH-1:0]       s4_axi_awid        ,
610 
   input  wire [C_S4_AXI_ADDR_WIDTH-1:0]     s4_axi_awaddr      ,
611 
   input  wire [7:0]                         s4_axi_awlen       ,
612 
   input  wire [2:0]                         s4_axi_awsize      ,
613 
   input  wire [1:0]                         s4_axi_awburst     ,
614 
   input  wire [0:0]                         s4_axi_awlock      ,
615 
   input  wire [3:0]                         s4_axi_awcache     ,
616 
   input  wire [2:0]                         s4_axi_awprot      ,
617 
   input  wire [3:0]                         s4_axi_awqos       ,
618 
   input  wire                               s4_axi_awvalid     ,
619 
   output wire                               s4_axi_awready     ,
620 
   input  wire [C_S4_AXI_DATA_WIDTH-1:0]     s4_axi_wdata       ,
621 
   input  wire [C_S4_AXI_DATA_WIDTH/8-1:0]   s4_axi_wstrb       ,
622 
   input  wire                               s4_axi_wlast       ,
623 
   input  wire                               s4_axi_wvalid      ,
624 
   output wire                               s4_axi_wready      ,
625 
   output wire [C_S4_AXI_ID_WIDTH-1:0]       s4_axi_bid         ,
626 
   output wire [1:0]                         s4_axi_bresp       ,
627 
   output wire                               s4_axi_bvalid      ,
628 
   input  wire                               s4_axi_bready      ,
629 
   input  wire [C_S4_AXI_ID_WIDTH-1:0]       s4_axi_arid        ,
630 
   input  wire [C_S4_AXI_ADDR_WIDTH-1:0]     s4_axi_araddr      ,
631 
   input  wire [7:0]                         s4_axi_arlen       ,
632 
   input  wire [2:0]                         s4_axi_arsize      ,
633 
   input  wire [1:0]                         s4_axi_arburst     ,
634 
   input  wire [0:0]                         s4_axi_arlock      ,
635 
   input  wire [3:0]                         s4_axi_arcache     ,
636 
   input  wire [2:0]                         s4_axi_arprot      ,
637 
   input  wire [3:0]                         s4_axi_arqos       ,
638 
   input  wire                               s4_axi_arvalid     ,
639 
   output wire                               s4_axi_arready     ,
640 
   output wire [C_S4_AXI_ID_WIDTH-1:0]       s4_axi_rid         ,
641 
   output wire [C_S4_AXI_DATA_WIDTH-1:0]     s4_axi_rdata       ,
642 
   output wire [1:0]                         s4_axi_rresp       ,
643 
   output wire                               s4_axi_rlast       ,
644 
   output wire                               s4_axi_rvalid      ,
645 
   input  wire                               s4_axi_rready      ,
646 
 
647 
   input  wire                               s5_axi_aclk        ,
648 
   input  wire                               s5_axi_aresetn     ,
649 
   input  wire [C_S5_AXI_ID_WIDTH-1:0]       s5_axi_awid        ,
650 
   input  wire [C_S5_AXI_ADDR_WIDTH-1:0]     s5_axi_awaddr      ,
651 
   input  wire [7:0]                         s5_axi_awlen       ,
652 
   input  wire [2:0]                         s5_axi_awsize      ,
653 
   input  wire [1:0]                         s5_axi_awburst     ,
654 
   input  wire [0:0]                         s5_axi_awlock      ,
655 
   input  wire [3:0]                         s5_axi_awcache     ,
656 
   input  wire [2:0]                         s5_axi_awprot      ,
657 
   input  wire [3:0]                         s5_axi_awqos       ,
658 
   input  wire                               s5_axi_awvalid     ,
659 
   output wire                               s5_axi_awready     ,
660 
   input  wire [C_S5_AXI_DATA_WIDTH-1:0]     s5_axi_wdata       ,
661 
   input  wire [C_S5_AXI_DATA_WIDTH/8-1:0]   s5_axi_wstrb       ,
662 
   input  wire                               s5_axi_wlast       ,
663 
   input  wire                               s5_axi_wvalid      ,
664 
   output wire                               s5_axi_wready      ,
665 
   output wire [C_S5_AXI_ID_WIDTH-1:0]       s5_axi_bid         ,
666 
   output wire [1:0]                         s5_axi_bresp       ,
667 
   output wire                               s5_axi_bvalid      ,
668 
   input  wire                               s5_axi_bready      ,
669 
   input  wire [C_S5_AXI_ID_WIDTH-1:0]       s5_axi_arid        ,
670 
   input  wire [C_S5_AXI_ADDR_WIDTH-1:0]     s5_axi_araddr      ,
671 
   input  wire [7:0]                         s5_axi_arlen       ,
672 
   input  wire [2:0]                         s5_axi_arsize      ,
673 
   input  wire [1:0]                         s5_axi_arburst     ,
674 
   input  wire [0:0]                         s5_axi_arlock      ,
675 
   input  wire [3:0]                         s5_axi_arcache     ,
676 
   input  wire [2:0]                         s5_axi_arprot      ,
677 
   input  wire [3:0]                         s5_axi_arqos       ,
678 
   input  wire                               s5_axi_arvalid     ,
679 
   output wire                               s5_axi_arready     ,
680 
   output wire [C_S5_AXI_ID_WIDTH-1:0]       s5_axi_rid         ,
681 
   output wire [C_S5_AXI_DATA_WIDTH-1:0]     s5_axi_rdata       ,
682 
   output wire [1:0]                         s5_axi_rresp       ,
683 
   output wire                               s5_axi_rlast       ,
684 
   output wire                               s5_axi_rvalid      ,
685 
   input  wire                               s5_axi_rready
686 
   );
687 
 
688 
////////////////////////////////////////////////////////////////////////////////
689 
// Functions
690 
////////////////////////////////////////////////////////////////////////////////
691 
// Barrel Left Shift Octal
692 
function [17:0] blso (
693 
  input [17:0] a,
694 
  input integer shift,
695 
  input integer width
696 
);
697 
begin : func_blso
698 
  integer i;
699 
  integer w;
700 
  integer s;
701 
  w = width*3;
702 
  s = (shift*3) % w;
703 
  blso = 18'o000000;
704 
  for (i = 0; i < w; i = i + 1) begin
705 
    blso[i] = a[(i+w-s)%w];
706 
    //bls[i] = 1'b1;
707 
  end
708 
end
709 
endfunction
710 
 
711 
// For a given port_config, port_enable and slot, calculate the round robin
712 
// arbitration that would be generated by the gui.
713 
function [17:0] rr (
714 
  input [5:0] port_enable,
715 
  input integer port_config,
716 
  input integer slot_num
717 
);
718 
begin : func_rr
719 
  integer i;
720 
  integer max_ports;
721 
  integer num_ports;
722 
  integer port_cnt;
723 
 
724 
  case (port_config)
725 
    1: max_ports = 6;
726 
    2: max_ports = 4;
727 
    3: max_ports = 3;
728 
    4: max_ports = 2;
729 
    5: max_ports = 1;
730 
// synthesis translate_off
731 
    default : $display("ERROR: Port Config can't be %d", port_config);
732 
// synthesis translate_on
733 
  endcase
734 
 
735 
  num_ports = 0;
736 
  for (i = 0; i < max_ports; i = i + 1) begin
737 
    if (port_enable[i] == 1'b1) begin
738 
      num_ports = num_ports + 1;
739 
    end
740 
  end
741 
 
742 
  rr = 18'o000000;
743 
  port_cnt = 0;
744 
 
745 
  for (i = (num_ports-1); i >= 0; i = i - 1) begin
746 
    while (port_enable[port_cnt] != 1'b1) begin
747 
      port_cnt = port_cnt + 1;
748 
    end
749 
    rr[i*3 +: 3] = port_cnt[2:0];
750 
    port_cnt = port_cnt +1;
751 
  end
752 
 
753 
 
754 
  rr = blso(rr, slot_num, num_ports);
755 
end
756 
endfunction
757 
 
758 
function [17:0] convert_arb_slot (
759 
  input [5:0]   port_enable,
760 
  input integer port_config,
761 
  input [17:0]  mig_arb_slot
762 
);
763 
begin : func_convert_arb_slot
764 
  integer i;
765 
  integer num_ports;
766 
  integer mig_port_num;
767 
  reg [17:0] port_map;
768 
  num_ports = 0;
769 
 
770 
  // Enumerated port configuration for ease of use
771 
  case (port_config)
772 
    1: port_map = 18'o543210;
773 
    2: port_map = 18'o774210;
774 
    3: port_map = 18'o777420;
775 
    4: port_map = 18'o777720;
776 
    5: port_map = 18'o777770;
777 
// synthesis translate_off
778 
    default : $display ("ERROR: Invalid Port Configuration.");
779 
// synthesis translate_on
780 
  endcase
781 
 
782 
  // Count the number of ports
783 
  for (i = 0; i < 6; i = i + 1) begin
784 
    if (port_enable[i] == 1'b1) begin
785 
      num_ports = num_ports + 1;
786 
    end
787 
  end
788 
 
789 
  // Map the ports from the MIG GUI to the MCB Wrapper
790 
  for (i = 0; i < 6; i = i + 1) begin
791 
    if (i < num_ports) begin
792 
      mig_port_num = mig_arb_slot[3*(num_ports-i-1) +: 3];
793 
      convert_arb_slot[3*i +: 3] = port_map[3*mig_port_num +: 3];
794 
    end else begin
795 
      convert_arb_slot[3*i +: 3] = 3'b111;
796 
    end
797 
  end
798 
end
799 
endfunction
800 
 
801 
// Function to calculate the number of time slots automatically based on the
802 
// number of ports used.  Will choose 10 if the number of valid ports is 5,
803 
// otherwise it will be 12.
804 
function integer calc_num_time_slots (
805 
  input [5:0]   port_enable,
806 
  input integer port_config
807 
);
808 
begin : func_calc_num_tim_slots
809 
  integer num_ports;
810 
  integer i;
811 
  num_ports = 0;
812 
  for (i = 0; i < 6; i = i + 1) begin
813 
    if (port_enable[i] == 1'b1) begin
814 
      num_ports = num_ports + 1;
815 
    end
816 
  end
817 
  calc_num_time_slots = (port_config == 1 && num_ports == 5) ? 10 : 12;
818 
end
819 
endfunction
820 
////////////////////////////////////////////////////////////////////////////////
821 
// Local Parameters
822 
////////////////////////////////////////////////////////////////////////////////
823 
  localparam P_S0_AXI_ADDRMASK = C_S0_AXI_BASEADDR ^ C_S0_AXI_HIGHADDR;
824 
  localparam P_S1_AXI_ADDRMASK = C_S1_AXI_BASEADDR ^ C_S1_AXI_HIGHADDR;
825 
  localparam P_S2_AXI_ADDRMASK = C_S2_AXI_BASEADDR ^ C_S2_AXI_HIGHADDR;
826 
  localparam P_S3_AXI_ADDRMASK = C_S3_AXI_BASEADDR ^ C_S3_AXI_HIGHADDR;
827 
  localparam P_S4_AXI_ADDRMASK = C_S4_AXI_BASEADDR ^ C_S4_AXI_HIGHADDR;
828 
  localparam P_S5_AXI_ADDRMASK = C_S5_AXI_BASEADDR ^ C_S5_AXI_HIGHADDR;
829 
  localparam P_PORT_CONFIG     = (C_PORT_CONFIG == "B32_B32_B32_B32") ? 2 :
830 
                                 (C_PORT_CONFIG == "B64_B32_B32"    ) ? 3 :
831 
                                 (C_PORT_CONFIG == "B64_B64"        ) ? 4 :
832 
                                 (C_PORT_CONFIG == "B128"           ) ? 5 :
833 
                                 1; // B32_B32_x32_x32_x32_x32 case
834 
  localparam P_ARB_NUM_TIME_SLOTS = (C_ARB_ALGORITHM == 0) ? calc_num_time_slots(C_PORT_ENABLE, P_PORT_CONFIG) : C_ARB_NUM_TIME_SLOTS;
835 
  localparam P_0_ARB_TIME_SLOT_0 =  (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 0 ) : C_ARB_TIME_SLOT_0 ;
836 
  localparam P_0_ARB_TIME_SLOT_1 =  (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 1 ) : C_ARB_TIME_SLOT_1 ;
837 
  localparam P_0_ARB_TIME_SLOT_2 =  (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 2 ) : C_ARB_TIME_SLOT_2 ;
838 
  localparam P_0_ARB_TIME_SLOT_3 =  (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 3 ) : C_ARB_TIME_SLOT_3 ;
839 
  localparam P_0_ARB_TIME_SLOT_4 =  (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 4 ) : C_ARB_TIME_SLOT_4 ;
840 
  localparam P_0_ARB_TIME_SLOT_5 =  (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 5 ) : C_ARB_TIME_SLOT_5 ;
841 
  localparam P_0_ARB_TIME_SLOT_6 =  (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 6 ) : C_ARB_TIME_SLOT_6 ;
842 
  localparam P_0_ARB_TIME_SLOT_7 =  (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 7 ) : C_ARB_TIME_SLOT_7 ;
843 
  localparam P_0_ARB_TIME_SLOT_8 =  (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 8 ) : C_ARB_TIME_SLOT_8 ;
844 
  localparam P_0_ARB_TIME_SLOT_9 =  (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 9 ) : C_ARB_TIME_SLOT_9 ;
845 
  localparam P_0_ARB_TIME_SLOT_10 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 10) : C_ARB_TIME_SLOT_10;
846 
  localparam P_0_ARB_TIME_SLOT_11 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 11) : C_ARB_TIME_SLOT_11;
847 
  localparam P_ARB_TIME_SLOT_0 =  convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_0);
848 
  localparam P_ARB_TIME_SLOT_1 =  convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_1);
849 
  localparam P_ARB_TIME_SLOT_2 =  convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_2);
850 
  localparam P_ARB_TIME_SLOT_3 =  convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_3);
851 
  localparam P_ARB_TIME_SLOT_4 =  convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_4);
852 
  localparam P_ARB_TIME_SLOT_5 =  convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_5);
853 
  localparam P_ARB_TIME_SLOT_6 =  convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_6);
854 
  localparam P_ARB_TIME_SLOT_7 =  convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_7);
855 
  localparam P_ARB_TIME_SLOT_8 =  convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_8);
856 
  localparam P_ARB_TIME_SLOT_9 =  convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_9);
857 
  localparam P_ARB_TIME_SLOT_10 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_10);
858 
  localparam P_ARB_TIME_SLOT_11 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_11);
859 
 
860 
////////////////////////////////////////////////////////////////////////////////
861 
// Wires/Reg declarations
862 
////////////////////////////////////////////////////////////////////////////////
863 
  wire [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_araddr_i;
864 
  wire [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_awaddr_i;
865 
  wire                           p0_arb_en_i;
866 
  wire                           p0_cmd_clk_i;
867 
  wire                           p0_cmd_en_i;
868 
  wire [2:0]                     p0_cmd_instr_i;
869 
  wire [5:0]                     p0_cmd_bl_i;
870 
  wire [29:0]                    p0_cmd_byte_addr_i;
871 
  wire                           p0_cmd_empty_i;
872 
  wire                           p0_cmd_full_i;
873 
  wire                           p0_wr_clk_i;
874 
  wire                           p0_wr_en_i;
875 
  wire [C_P0_MASK_SIZE-1:0]      p0_wr_mask_i;
876 
  wire [C_P0_DATA_PORT_SIZE-1:0] p0_wr_data_i;
877 
  wire                           p0_wr_full_i;
878 
  wire                           p0_wr_empty_i;
879 
  wire [6:0]                     p0_wr_count_i;
880 
  wire                           p0_wr_underrun_i;
881 
  wire                           p0_wr_error_i;
882 
  wire                           p0_rd_clk_i;
883 
  wire                           p0_rd_en_i;
884 
  wire [C_P0_DATA_PORT_SIZE-1:0] p0_rd_data_i;
885 
  wire                           p0_rd_full_i;
886 
  wire                           p0_rd_empty_i;
887 
  wire [6:0]                     p0_rd_count_i;
888 
  wire                           p0_rd_overflow_i;
889 
  wire                           p0_rd_error_i;
890 
 
891 
  wire [C_S1_AXI_ADDR_WIDTH-1:0] s1_axi_araddr_i;
892 
  wire [C_S1_AXI_ADDR_WIDTH-1:0] s1_axi_awaddr_i;
893 
  wire                           p1_arb_en_i;
894 
  wire                           p1_cmd_clk_i;
895 
  wire                           p1_cmd_en_i;
896 
  wire [2:0]                     p1_cmd_instr_i;
897 
  wire [5:0]                     p1_cmd_bl_i;
898 
  wire [29:0]                    p1_cmd_byte_addr_i;
899 
  wire                           p1_cmd_empty_i;
900 
  wire                           p1_cmd_full_i;
901 
  wire                           p1_wr_clk_i;
902 
  wire                           p1_wr_en_i;
903 
  wire [C_P1_MASK_SIZE-1:0]      p1_wr_mask_i;
904 
  wire [C_P1_DATA_PORT_SIZE-1:0] p1_wr_data_i;
905 
  wire                           p1_wr_full_i;
906 
  wire                           p1_wr_empty_i;
907 
  wire [6:0]                     p1_wr_count_i;
908 
  wire                           p1_wr_underrun_i;
909 
  wire                           p1_wr_error_i;
910 
  wire                           p1_rd_clk_i;
911 
  wire                           p1_rd_en_i;
912 
  wire [C_P1_DATA_PORT_SIZE-1:0] p1_rd_data_i;
913 
  wire                           p1_rd_full_i;
914 
  wire                           p1_rd_empty_i;
915 
  wire [6:0]                     p1_rd_count_i;
916 
  wire                           p1_rd_overflow_i;
917 
  wire                           p1_rd_error_i;
918 
 
919 
  wire [C_S2_AXI_ADDR_WIDTH-1:0] s2_axi_araddr_i;
920 
  wire [C_S2_AXI_ADDR_WIDTH-1:0] s2_axi_awaddr_i;
921 
  wire                           p2_arb_en_i;
922 
  wire                           p2_cmd_clk_i;
923 
  wire                           p2_cmd_en_i;
924 
  wire [2:0]                     p2_cmd_instr_i;
925 
  wire [5:0]                     p2_cmd_bl_i;
926 
  wire [29:0]                    p2_cmd_byte_addr_i;
927 
  wire                           p2_cmd_empty_i;
928 
  wire                           p2_cmd_full_i;
929 
  wire                           p2_wr_clk_i;
930 
  wire                           p2_wr_en_i;
931 
  wire [3:0]                     p2_wr_mask_i;
932 
  wire [31:0]                    p2_wr_data_i;
933 
  wire                           p2_wr_full_i;
934 
  wire                           p2_wr_empty_i;
935 
  wire [6:0]                     p2_wr_count_i;
936 
  wire                           p2_wr_underrun_i;
937 
  wire                           p2_wr_error_i;
938 
  wire                           p2_rd_clk_i;
939 
  wire                           p2_rd_en_i;
940 
  wire [31:0]                    p2_rd_data_i;
941 
  wire                           p2_rd_full_i;
942 
  wire                           p2_rd_empty_i;
943 
  wire [6:0]                     p2_rd_count_i;
944 
  wire                           p2_rd_overflow_i;
945 
  wire                           p2_rd_error_i;
946 
 
947 
  wire [C_S3_AXI_ADDR_WIDTH-1:0] s3_axi_araddr_i;
948 
  wire [C_S3_AXI_ADDR_WIDTH-1:0] s3_axi_awaddr_i;
949 
  wire                           p3_arb_en_i;
950 
  wire                           p3_cmd_clk_i;
951 
  wire                           p3_cmd_en_i;
952 
  wire [2:0]                     p3_cmd_instr_i;
953 
  wire [5:0]                     p3_cmd_bl_i;
954 
  wire [29:0]                    p3_cmd_byte_addr_i;
955 
  wire                           p3_cmd_empty_i;
956 
  wire                           p3_cmd_full_i;
957 
  wire                           p3_wr_clk_i;
958 
  wire                           p3_wr_en_i;
959 
  wire [3:0]                     p3_wr_mask_i;
960 
  wire [31:0]                    p3_wr_data_i;
961 
  wire                           p3_wr_full_i;
962 
  wire                           p3_wr_empty_i;
963 
  wire [6:0]                     p3_wr_count_i;
964 
  wire                           p3_wr_underrun_i;
965 
  wire                           p3_wr_error_i;
966 
  wire                           p3_rd_clk_i;
967 
  wire                           p3_rd_en_i;
968 
  wire [31:0]                    p3_rd_data_i;
969 
  wire                           p3_rd_full_i;
970 
  wire                           p3_rd_empty_i;
971 
  wire [6:0]                     p3_rd_count_i;
972 
  wire                           p3_rd_overflow_i;
973 
  wire                           p3_rd_error_i;
974 
 
975 
  wire [C_S4_AXI_ADDR_WIDTH-1:0] s4_axi_araddr_i;
976 
  wire [C_S4_AXI_ADDR_WIDTH-1:0] s4_axi_awaddr_i;
977 
  wire                           p4_arb_en_i;
978 
  wire                           p4_cmd_clk_i;
979 
  wire                           p4_cmd_en_i;
980 
  wire [2:0]                     p4_cmd_instr_i;
981 
  wire [5:0]                     p4_cmd_bl_i;
982 
  wire [29:0]                    p4_cmd_byte_addr_i;
983 
  wire                           p4_cmd_empty_i;
984 
  wire                           p4_cmd_full_i;
985 
  wire                           p4_wr_clk_i;
986 
  wire                           p4_wr_en_i;
987 
  wire [3:0]                     p4_wr_mask_i;
988 
  wire [31:0]                    p4_wr_data_i;
989 
  wire                           p4_wr_full_i;
990 
  wire                           p4_wr_empty_i;
991 
  wire [6:0]                     p4_wr_count_i;
992 
  wire                           p4_wr_underrun_i;
993 
  wire                           p4_wr_error_i;
994 
  wire                           p4_rd_clk_i;
995 
  wire                           p4_rd_en_i;
996 
  wire [31:0]                    p4_rd_data_i;
997 
  wire                           p4_rd_full_i;
998 
  wire                           p4_rd_empty_i;
999 
  wire [6:0]                     p4_rd_count_i;
1000 
  wire                           p4_rd_overflow_i;
1001 
  wire                           p4_rd_error_i;
1002 
 
1003 
  wire [C_S5_AXI_ADDR_WIDTH-1:0] s5_axi_araddr_i;
1004 
  wire [C_S5_AXI_ADDR_WIDTH-1:0] s5_axi_awaddr_i;
1005 
  wire                           p5_arb_en_i;
1006 
  wire                           p5_cmd_clk_i;
1007 
  wire                           p5_cmd_en_i;
1008 
  wire [2:0]                     p5_cmd_instr_i;
1009 
  wire [5:0]                     p5_cmd_bl_i;
1010 
  wire [29:0]                    p5_cmd_byte_addr_i;
1011 
  wire                           p5_cmd_empty_i;
1012 
  wire                           p5_cmd_full_i;
1013 
  wire                           p5_wr_clk_i;
1014 
  wire                           p5_wr_en_i;
1015 
  wire [3:0]                     p5_wr_mask_i;
1016 
  wire [31:0]                    p5_wr_data_i;
1017 
  wire                           p5_wr_full_i;
1018 
  wire                           p5_wr_empty_i;
1019 
  wire [6:0]                     p5_wr_count_i;
1020 
  wire                           p5_wr_underrun_i;
1021 
  wire                           p5_wr_error_i;
1022 
  wire                           p5_rd_clk_i;
1023 
  wire                           p5_rd_en_i;
1024 
  wire [31:0]                    p5_rd_data_i;
1025 
  wire                           p5_rd_full_i;
1026 
  wire                           p5_rd_empty_i;
1027 
  wire [6:0]                     p5_rd_count_i;
1028 
  wire                           p5_rd_overflow_i;
1029 
  wire                           p5_rd_error_i;
1030 
 
1031 
  wire                           ioclk0;
1032 
  wire                           ioclk180;
1033 
  wire                           pll_ce_0_i;
1034 
  wire                           pll_ce_90_i;
1035 
 
1036 
  generate
1037 
    if (C_MCB_USE_EXTERNAL_BUFPLL == 0) begin : gen_spartan6_bufpll_mcb
1038 
      // Instantiate the PLL for MCB.
1039 
      BUFPLL_MCB #
1040 
      (
1041 
      .DIVIDE   (2),
1042 
      .LOCK_SRC ("LOCK_TO_0")
1043 
      )
1044 
      bufpll_0
1045 
        (
1046 
        .IOCLK0       (ioclk0),
1047 
        .IOCLK1       (ioclk180),
1048 
        .GCLK         (ui_clk),
1049 
        .LOCKED       (pll_lock),
1050 
        .LOCK         (pll_lock_bufpll_o),
1051 
        .SERDESSTROBE0(pll_ce_0_i),
1052 
        .SERDESSTROBE1(pll_ce_90_i),
1053 
        .PLLIN0       (sysclk_2x),
1054 
        .PLLIN1       (sysclk_2x_180)
1055 
        );
1056 
      end else begin : gen_spartan6_no_bufpll_mcb
1057 
        // Use external bufpll_mcb.
1058 
        assign pll_ce_0_i   = pll_ce_0;
1059 
        assign pll_ce_90_i  = pll_ce_90;
1060 
        assign ioclk0     = sysclk_2x;
1061 
        assign ioclk180   = sysclk_2x_180;
1062 
        assign pll_lock_bufpll_o = pll_lock;
1063 
      end
1064 
  endgenerate
1065 
 
1066 
  assign sysclk_2x_bufpll_o     = ioclk0;
1067 
  assign sysclk_2x_180_bufpll_o = ioclk180;
1068 
  assign pll_ce_0_bufpll_o      = pll_ce_0_i;
1069 
  assign pll_ce_90_bufpll_o     = pll_ce_90_i;
1070 
 
1071 
mcb_raw_wrapper #
1072 
   (
1073 
   .C_MEMCLK_PERIOD           ( C_MEMCLK_PERIOD           ),
1074 
   .C_PORT_ENABLE             ( C_PORT_ENABLE             ),
1075 
   .C_MEM_ADDR_ORDER          ( C_MEM_ADDR_ORDER          ),
1076 
   .C_ARB_NUM_TIME_SLOTS      ( P_ARB_NUM_TIME_SLOTS      ),
1077 
   .C_ARB_TIME_SLOT_0         ( P_ARB_TIME_SLOT_0         ),
1078 
   .C_ARB_TIME_SLOT_1         ( P_ARB_TIME_SLOT_1         ),
1079 
   .C_ARB_TIME_SLOT_2         ( P_ARB_TIME_SLOT_2         ),
1080 
   .C_ARB_TIME_SLOT_3         ( P_ARB_TIME_SLOT_3         ),
1081 
   .C_ARB_TIME_SLOT_4         ( P_ARB_TIME_SLOT_4         ),
1082 
   .C_ARB_TIME_SLOT_5         ( P_ARB_TIME_SLOT_5         ),
1083 
   .C_ARB_TIME_SLOT_6         ( P_ARB_TIME_SLOT_6         ),
1084 
   .C_ARB_TIME_SLOT_7         ( P_ARB_TIME_SLOT_7         ),
1085 
   .C_ARB_TIME_SLOT_8         ( P_ARB_TIME_SLOT_8         ),
1086 
   .C_ARB_TIME_SLOT_9         ( P_ARB_TIME_SLOT_9         ),
1087 
   .C_ARB_TIME_SLOT_10        ( P_ARB_TIME_SLOT_10        ),
1088 
   .C_ARB_TIME_SLOT_11        ( P_ARB_TIME_SLOT_11        ),
1089 
   .C_PORT_CONFIG             ( C_PORT_CONFIG             ),
1090 
   .C_MEM_TRAS                ( C_MEM_TRAS                ),
1091 
   .C_MEM_TRCD                ( C_MEM_TRCD                ),
1092 
   .C_MEM_TREFI               ( C_MEM_TREFI               ),
1093 
   .C_MEM_TRFC                ( C_MEM_TRFC                ),
1094 
   .C_MEM_TRP                 ( C_MEM_TRP                 ),
1095 
   .C_MEM_TWR                 ( C_MEM_TWR                 ),
1096 
   .C_MEM_TRTP                ( C_MEM_TRTP                ),
1097 
   .C_MEM_TWTR                ( C_MEM_TWTR                ),
1098 
   .C_NUM_DQ_PINS             ( C_NUM_DQ_PINS             ),
1099 
   .C_MEM_TYPE                ( C_MEM_TYPE                ),
1100 
   .C_MEM_DENSITY             ( C_MEM_DENSITY             ),
1101 
   .C_MEM_BURST_LEN           ( C_MEM_BURST_LEN           ),
1102 
   .C_MEM_CAS_LATENCY         ( C_MEM_CAS_LATENCY         ),
1103 
   .C_MEM_ADDR_WIDTH          ( C_MEM_ADDR_WIDTH          ),
1104 
   .C_MEM_BANKADDR_WIDTH      ( C_MEM_BANKADDR_WIDTH      ),
1105 
   .C_MEM_NUM_COL_BITS        ( C_MEM_NUM_COL_BITS        ),
1106 
   .C_MEM_DDR3_CAS_LATENCY    ( C_MEM_DDR3_CAS_LATENCY    ),
1107 
   .C_MEM_MOBILE_PA_SR        ( C_MEM_MOBILE_PA_SR        ),
1108 
   .C_MEM_DDR1_2_ODS          ( C_MEM_DDR1_2_ODS          ),
1109 
   .C_MEM_DDR3_ODS            ( C_MEM_DDR3_ODS            ),
1110 
   .C_MEM_DDR2_RTT            ( C_MEM_DDR2_RTT            ),
1111 
   .C_MEM_DDR3_RTT            ( C_MEM_DDR3_RTT            ),
1112 
   .C_MEM_MDDR_ODS            ( C_MEM_MDDR_ODS            ),
1113 
   .C_MEM_DDR2_DIFF_DQS_EN    ( C_MEM_DDR2_DIFF_DQS_EN    ),
1114 
   .C_MEM_DDR2_3_PA_SR        ( C_MEM_DDR2_3_PA_SR        ),
1115 
   .C_MEM_DDR3_CAS_WR_LATENCY ( C_MEM_DDR3_CAS_WR_LATENCY ),
1116 
   .C_MEM_DDR3_AUTO_SR        ( C_MEM_DDR3_AUTO_SR        ),
1117 
   .C_MEM_DDR2_3_HIGH_TEMP_SR ( C_MEM_DDR2_3_HIGH_TEMP_SR ),
1118 
   .C_MEM_DDR3_DYN_WRT_ODT    ( C_MEM_DDR3_DYN_WRT_ODT    ),
1119 
   // Subtract 16 to stop TRFC violations.
1120 
   .C_MEM_TZQINIT_MAXCNT      ( C_MEM_TZQINIT_MAXCNT - 16 ),
1121 
   .C_MC_CALIB_BYPASS         ( C_MC_CALIB_BYPASS         ),
1122 
   .C_MC_CALIBRATION_RA       ( C_MC_CALIBRATION_RA       ),
1123 
   .C_MC_CALIBRATION_BA       ( C_MC_CALIBRATION_BA       ),
1124 
   .C_CALIB_SOFT_IP           ( C_CALIB_SOFT_IP           ),
1125 
   .C_SKIP_IN_TERM_CAL        ( C_SKIP_IN_TERM_CAL        ),
1126 
   .C_SKIP_DYNAMIC_CAL        ( C_SKIP_DYNAMIC_CAL        ),
1127 
   .C_SKIP_DYN_IN_TERM        ( C_SKIP_DYN_IN_TERM        ),
1128 
   .LDQSP_TAP_DELAY_VAL       ( LDQSP_TAP_DELAY_VAL       ),
1129 
   .UDQSP_TAP_DELAY_VAL       ( UDQSP_TAP_DELAY_VAL       ),
1130 
   .LDQSN_TAP_DELAY_VAL       ( LDQSN_TAP_DELAY_VAL       ),
1131 
   .UDQSN_TAP_DELAY_VAL       ( UDQSN_TAP_DELAY_VAL       ),
1132 
   .DQ0_TAP_DELAY_VAL         ( DQ0_TAP_DELAY_VAL         ),
1133 
   .DQ1_TAP_DELAY_VAL         ( DQ1_TAP_DELAY_VAL         ),
1134 
   .DQ2_TAP_DELAY_VAL         ( DQ2_TAP_DELAY_VAL         ),
1135 
   .DQ3_TAP_DELAY_VAL         ( DQ3_TAP_DELAY_VAL         ),
1136 
   .DQ4_TAP_DELAY_VAL         ( DQ4_TAP_DELAY_VAL         ),
1137 
   .DQ5_TAP_DELAY_VAL         ( DQ5_TAP_DELAY_VAL         ),
1138 
   .DQ6_TAP_DELAY_VAL         ( DQ6_TAP_DELAY_VAL         ),
1139 
   .DQ7_TAP_DELAY_VAL         ( DQ7_TAP_DELAY_VAL         ),
1140 
   .DQ8_TAP_DELAY_VAL         ( DQ8_TAP_DELAY_VAL         ),
1141 
   .DQ9_TAP_DELAY_VAL         ( DQ9_TAP_DELAY_VAL         ),
1142 
   .DQ10_TAP_DELAY_VAL        ( DQ10_TAP_DELAY_VAL        ),
1143 
   .DQ11_TAP_DELAY_VAL        ( DQ11_TAP_DELAY_VAL        ),
1144 
   .DQ12_TAP_DELAY_VAL        ( DQ12_TAP_DELAY_VAL        ),
1145 
   .DQ13_TAP_DELAY_VAL        ( DQ13_TAP_DELAY_VAL        ),
1146 
   .DQ14_TAP_DELAY_VAL        ( DQ14_TAP_DELAY_VAL        ),
1147 
   .DQ15_TAP_DELAY_VAL        ( DQ15_TAP_DELAY_VAL        ),
1148 
   .C_MC_CALIBRATION_CA       ( C_MC_CALIBRATION_CA       ),
1149 
   .C_MC_CALIBRATION_CLK_DIV  ( C_MC_CALIBRATION_CLK_DIV  ),
1150 
   .C_MC_CALIBRATION_MODE     ( C_MC_CALIBRATION_MODE     ),
1151 
   .C_MC_CALIBRATION_DELAY    ( C_MC_CALIBRATION_DELAY    ),
1152 
   // synthesis translate_off
1153 
   .C_SIMULATION              ( C_SIMULATION              ),
1154 
   // synthesis translate_on
1155 
   .C_P0_MASK_SIZE            ( C_P0_MASK_SIZE            ),
1156 
   .C_P0_DATA_PORT_SIZE       ( C_P0_DATA_PORT_SIZE       ),
1157 
   .C_P1_MASK_SIZE            ( C_P1_MASK_SIZE            ),
1158 
   .C_P1_DATA_PORT_SIZE       ( C_P1_DATA_PORT_SIZE       )
1159 
   )
1160 
   mcb_raw_wrapper_inst
1161 
   (
1162 
   .sysclk_2x                 ( ioclk0                    ),
1163 
   .sysclk_2x_180             ( ioclk180                  ),
1164 
   .pll_ce_0                  ( pll_ce_0_i                ),
1165 
   .pll_ce_90                 ( pll_ce_90_i               ),
1166 
   .pll_lock                  ( pll_lock_bufpll_o         ),
1167 
   .sys_rst                   ( sys_rst                   ),
1168 
   .p0_arb_en                 ( p0_arb_en_i               ),
1169 
   .p0_cmd_clk                ( p0_cmd_clk_i              ),
1170 
   .p0_cmd_en                 ( p0_cmd_en_i               ),
1171 
   .p0_cmd_instr              ( p0_cmd_instr_i            ),
1172 
   .p0_cmd_bl                 ( p0_cmd_bl_i               ),
1173 
   .p0_cmd_byte_addr          ( p0_cmd_byte_addr_i        ),
1174 
   .p0_cmd_empty              ( p0_cmd_empty_i            ),
1175 
   .p0_cmd_full               ( p0_cmd_full_i             ),
1176 
   .p0_wr_clk                 ( p0_wr_clk_i               ),
1177 
   .p0_wr_en                  ( p0_wr_en_i                ),
1178 
   .p0_wr_mask                ( p0_wr_mask_i              ),
1179 
   .p0_wr_data                ( p0_wr_data_i              ),
1180 
   .p0_wr_full                ( p0_wr_full_i              ),
1181 
   .p0_wr_empty               ( p0_wr_empty_i             ),
1182 
   .p0_wr_count               ( p0_wr_count_i             ),
1183 
   .p0_wr_underrun            ( p0_wr_underrun_i          ),
1184 
   .p0_wr_error               ( p0_wr_error_i             ),
1185 
   .p0_rd_clk                 ( p0_rd_clk_i               ),
1186 
   .p0_rd_en                  ( p0_rd_en_i                ),
1187 
   .p0_rd_data                ( p0_rd_data_i              ),
1188 
   .p0_rd_full                ( p0_rd_full_i              ),
1189 
   .p0_rd_empty               ( p0_rd_empty_i             ),
1190 
   .p0_rd_count               ( p0_rd_count_i             ),
1191 
   .p0_rd_overflow            ( p0_rd_overflow_i          ),
1192 
   .p0_rd_error               ( p0_rd_error_i             ),
1193 
   .p1_arb_en                 ( p1_arb_en_i               ),
1194 
   .p1_cmd_clk                ( p1_cmd_clk_i              ),
1195 
   .p1_cmd_en                 ( p1_cmd_en_i               ),
1196 
   .p1_cmd_instr              ( p1_cmd_instr_i            ),
1197 
   .p1_cmd_bl                 ( p1_cmd_bl_i               ),
1198 
   .p1_cmd_byte_addr          ( p1_cmd_byte_addr_i        ),
1199 
   .p1_cmd_empty              ( p1_cmd_empty_i            ),
1200 
   .p1_cmd_full               ( p1_cmd_full_i             ),
1201 
   .p1_wr_clk                 ( p1_wr_clk_i               ),
1202 
   .p1_wr_en                  ( p1_wr_en_i                ),
1203 
   .p1_wr_mask                ( p1_wr_mask_i              ),
1204 
   .p1_wr_data                ( p1_wr_data_i              ),
1205 
   .p1_wr_full                ( p1_wr_full_i              ),
1206 
   .p1_wr_empty               ( p1_wr_empty_i             ),
1207 
   .p1_wr_count               ( p1_wr_count_i             ),
1208 
   .p1_wr_underrun            ( p1_wr_underrun_i          ),
1209 
   .p1_wr_error               ( p1_wr_error_i             ),
1210 
   .p1_rd_clk                 ( p1_rd_clk_i               ),
1211 
   .p1_rd_en                  ( p1_rd_en_i                ),
1212 
   .p1_rd_data                ( p1_rd_data_i              ),
1213 
   .p1_rd_full                ( p1_rd_full_i              ),
1214 
   .p1_rd_empty               ( p1_rd_empty_i             ),
1215 
   .p1_rd_count               ( p1_rd_count_i             ),
1216 
   .p1_rd_overflow            ( p1_rd_overflow_i          ),
1217 
   .p1_rd_error               ( p1_rd_error_i             ),
1218 
   .p2_arb_en                 ( p2_arb_en_i               ),
1219 
   .p2_cmd_clk                ( p2_cmd_clk_i              ),
1220 
   .p2_cmd_en                 ( p2_cmd_en_i               ),
1221 
   .p2_cmd_instr              ( p2_cmd_instr_i            ),
1222 
   .p2_cmd_bl                 ( p2_cmd_bl_i               ),
1223 
   .p2_cmd_byte_addr          ( p2_cmd_byte_addr_i        ),
1224 
   .p2_cmd_empty              ( p2_cmd_empty_i            ),
1225 
   .p2_cmd_full               ( p2_cmd_full_i             ),
1226 
   .p2_wr_clk                 ( p2_wr_clk_i               ),
1227 
   .p2_wr_en                  ( p2_wr_en_i                ),
1228 
   .p2_wr_mask                ( p2_wr_mask_i              ),
1229 
   .p2_wr_data                ( p2_wr_data_i              ),
1230 
   .p2_wr_full                ( p2_wr_full_i              ),
1231 
   .p2_wr_empty               ( p2_wr_empty_i             ),
1232 
   .p2_wr_count               ( p2_wr_count_i             ),
1233 
   .p2_wr_underrun            ( p2_wr_underrun_i          ),
1234 
   .p2_wr_error               ( p2_wr_error_i             ),
1235 
   .p2_rd_clk                 ( p2_rd_clk_i               ),
1236 
   .p2_rd_en                  ( p2_rd_en_i                ),
1237 
   .p2_rd_data                ( p2_rd_data_i              ),
1238 
   .p2_rd_full                ( p2_rd_full_i              ),
1239 
   .p2_rd_empty               ( p2_rd_empty_i             ),
1240 
   .p2_rd_count               ( p2_rd_count_i             ),
1241 
   .p2_rd_overflow            ( p2_rd_overflow_i          ),
1242 
   .p2_rd_error               ( p2_rd_error_i             ),
1243 
   .p3_arb_en                 ( p3_arb_en_i               ),
1244 
   .p3_cmd_clk                ( p3_cmd_clk_i              ),
1245 
   .p3_cmd_en                 ( p3_cmd_en_i               ),
1246 
   .p3_cmd_instr              ( p3_cmd_instr_i            ),
1247 
   .p3_cmd_bl                 ( p3_cmd_bl_i               ),
1248 
   .p3_cmd_byte_addr          ( p3_cmd_byte_addr_i        ),
1249 
   .p3_cmd_empty              ( p3_cmd_empty_i            ),
1250 
   .p3_cmd_full               ( p3_cmd_full_i             ),
1251 
   .p3_wr_clk                 ( p3_wr_clk_i               ),
1252 
   .p3_wr_en                  ( p3_wr_en_i                ),
1253 
   .p3_wr_mask                ( p3_wr_mask_i              ),
1254 
   .p3_wr_data                ( p3_wr_data_i              ),
1255 
   .p3_wr_full                ( p3_wr_full_i              ),
1256 
   .p3_wr_empty               ( p3_wr_empty_i             ),
1257 
   .p3_wr_count               ( p3_wr_count_i             ),
1258 
   .p3_wr_underrun            ( p3_wr_underrun_i          ),
1259 
   .p3_wr_error               ( p3_wr_error_i             ),
1260 
   .p3_rd_clk                 ( p3_rd_clk_i               ),
1261 
   .p3_rd_en                  ( p3_rd_en_i                ),
1262 
   .p3_rd_data                ( p3_rd_data_i              ),
1263 
   .p3_rd_full                ( p3_rd_full_i              ),
1264 
   .p3_rd_empty               ( p3_rd_empty_i             ),
1265 
   .p3_rd_count               ( p3_rd_count_i             ),
1266 
   .p3_rd_overflow            ( p3_rd_overflow_i          ),
1267 
   .p3_rd_error               ( p3_rd_error_i             ),
1268 
   .p4_arb_en                 ( p4_arb_en_i               ),
1269 
   .p4_cmd_clk                ( p4_cmd_clk_i              ),
1270 
   .p4_cmd_en                 ( p4_cmd_en_i               ),
1271 
   .p4_cmd_instr              ( p4_cmd_instr_i            ),
1272 
   .p4_cmd_bl                 ( p4_cmd_bl_i               ),
1273 
   .p4_cmd_byte_addr          ( p4_cmd_byte_addr_i        ),
1274 
   .p4_cmd_empty              ( p4_cmd_empty_i            ),
1275 
   .p4_cmd_full               ( p4_cmd_full_i             ),
1276 
   .p4_wr_clk                 ( p4_wr_clk_i               ),
1277 
   .p4_wr_en                  ( p4_wr_en_i                ),
1278 
   .p4_wr_mask                ( p4_wr_mask_i              ),
1279 
   .p4_wr_data                ( p4_wr_data_i              ),
1280 
   .p4_wr_full                ( p4_wr_full_i              ),
1281 
   .p4_wr_empty               ( p4_wr_empty_i             ),
1282 
   .p4_wr_count               ( p4_wr_count_i             ),
1283 
   .p4_wr_underrun            ( p4_wr_underrun_i          ),
1284 
   .p4_wr_error               ( p4_wr_error_i             ),
1285 
   .p4_rd_clk                 ( p4_rd_clk_i               ),
1286 
   .p4_rd_en                  ( p4_rd_en_i                ),
1287 
   .p4_rd_data                ( p4_rd_data_i              ),
1288 
   .p4_rd_full                ( p4_rd_full_i              ),
1289 
   .p4_rd_empty               ( p4_rd_empty_i             ),
1290 
   .p4_rd_count               ( p4_rd_count_i             ),
1291 
   .p4_rd_overflow            ( p4_rd_overflow_i          ),
1292 
   .p4_rd_error               ( p4_rd_error_i             ),
1293 
   .p5_arb_en                 ( p5_arb_en_i               ),
1294 
   .p5_cmd_clk                ( p5_cmd_clk_i              ),
1295 
   .p5_cmd_en                 ( p5_cmd_en_i               ),
1296 
   .p5_cmd_instr              ( p5_cmd_instr_i            ),
1297 
   .p5_cmd_bl                 ( p5_cmd_bl_i               ),
1298 
   .p5_cmd_byte_addr          ( p5_cmd_byte_addr_i        ),
1299 
   .p5_cmd_empty              ( p5_cmd_empty_i            ),
1300 
   .p5_cmd_full               ( p5_cmd_full_i             ),
1301 
   .p5_wr_clk                 ( p5_wr_clk_i               ),
1302 
   .p5_wr_en                  ( p5_wr_en_i                ),
1303 
   .p5_wr_mask                ( p5_wr_mask_i              ),
1304 
   .p5_wr_data                ( p5_wr_data_i              ),
1305 
   .p5_wr_full                ( p5_wr_full_i              ),
1306 
   .p5_wr_empty               ( p5_wr_empty_i             ),
1307 
   .p5_wr_count               ( p5_wr_count_i             ),
1308 
   .p5_wr_underrun            ( p5_wr_underrun_i          ),
1309 
   .p5_wr_error               ( p5_wr_error_i             ),
1310 
   .p5_rd_clk                 ( p5_rd_clk_i               ),
1311 
   .p5_rd_en                  ( p5_rd_en_i                ),
1312 
   .p5_rd_data                ( p5_rd_data_i              ),
1313 
   .p5_rd_full                ( p5_rd_full_i              ),
1314 
   .p5_rd_empty               ( p5_rd_empty_i             ),
1315 
   .p5_rd_count               ( p5_rd_count_i             ),
1316 
   .p5_rd_overflow            ( p5_rd_overflow_i          ),
1317 
   .p5_rd_error               ( p5_rd_error_i             ),
1318 
   .mcbx_dram_addr            ( mcbx_dram_addr            ),
1319 
   .mcbx_dram_ba              ( mcbx_dram_ba              ),
1320 
   .mcbx_dram_ras_n           ( mcbx_dram_ras_n           ),
1321 
   .mcbx_dram_cas_n           ( mcbx_dram_cas_n           ),
1322 
   .mcbx_dram_we_n            ( mcbx_dram_we_n            ),
1323 
   .mcbx_dram_cke             ( mcbx_dram_cke             ),
1324 
   .mcbx_dram_clk             ( mcbx_dram_clk             ),
1325 
   .mcbx_dram_clk_n           ( mcbx_dram_clk_n           ),
1326 
   .mcbx_dram_dq              ( mcbx_dram_dq              ),
1327 
   .mcbx_dram_dqs             ( mcbx_dram_dqs             ),
1328 
   .mcbx_dram_dqs_n           ( mcbx_dram_dqs_n           ),
1329 
   .mcbx_dram_udqs            ( mcbx_dram_udqs            ),
1330 
   .mcbx_dram_udqs_n          ( mcbx_dram_udqs_n          ),
1331 
   .mcbx_dram_udm             ( mcbx_dram_udm             ),
1332 
   .mcbx_dram_ldm             ( mcbx_dram_ldm             ),
1333 
   .mcbx_dram_odt             ( mcbx_dram_odt             ),
1334 
   .mcbx_dram_ddr3_rst        ( mcbx_dram_ddr3_rst        ),
1335 
   .calib_recal               ( calib_recal               ),
1336 
   .rzq                       ( rzq                       ),
1337 
   .zio                       ( zio                       ),
1338 
   .ui_read                   ( ui_read                   ),
1339 
   .ui_add                    ( ui_add                    ),
1340 
   .ui_cs                     ( ui_cs                     ),
1341 
   .ui_clk                    ( ui_clk                    ),
1342 
   .ui_sdi                    ( ui_sdi                    ),
1343 
   .ui_addr                   ( ui_addr                   ),
1344 
   .ui_broadcast              ( ui_broadcast              ),
1345 
   .ui_drp_update             ( ui_drp_update             ),
1346 
   .ui_done_cal               ( ui_done_cal               ),
1347 
   .ui_cmd                    ( ui_cmd                    ),
1348 
   .ui_cmd_in                 ( ui_cmd_in                 ),
1349 
   .ui_cmd_en                 ( ui_cmd_en                 ),
1350 
   .ui_dqcount                ( ui_dqcount                ),
1351 
   .ui_dq_lower_dec           ( ui_dq_lower_dec           ),
1352 
   .ui_dq_lower_inc           ( ui_dq_lower_inc           ),
1353 
   .ui_dq_upper_dec           ( ui_dq_upper_dec           ),
1354 
   .ui_dq_upper_inc           ( ui_dq_upper_inc           ),
1355 
   .ui_udqs_inc               ( ui_udqs_inc               ),
1356 
   .ui_udqs_dec               ( ui_udqs_dec               ),
1357 
   .ui_ldqs_inc               ( ui_ldqs_inc               ),
1358 
   .ui_ldqs_dec               ( ui_ldqs_dec               ),
1359 
   .uo_data                   ( uo_data                   ),
1360 
   .uo_data_valid             ( uo_data_valid             ),
1361 
   .uo_done_cal               ( uo_done_cal               ),
1362 
   .uo_cmd_ready_in           ( uo_cmd_ready_in           ),
1363 
   .uo_refrsh_flag            ( uo_refrsh_flag            ),
1364 
   .uo_cal_start              ( uo_cal_start              ),
1365 
   .uo_sdo                    ( uo_sdo                    ),
1366 
   .status                    ( status                    ),
1367 
   .selfrefresh_enter         ( selfrefresh_enter         ),
1368 
   .selfrefresh_mode          ( selfrefresh_mode          )
1369 
   );
1370 
 
1371 
// P0 AXI Bridge Mux
1372 
  generate
1373 
    if (C_S0_AXI_ENABLE == 0) begin : P0_UI_MCB
1374 
      assign  p0_arb_en_i        =  p0_arb_en        ; //
1375 
      assign  p0_cmd_clk_i       =  p0_cmd_clk       ; //
1376 
      assign  p0_cmd_en_i        =  p0_cmd_en        ; //
1377 
      assign  p0_cmd_instr_i     =  p0_cmd_instr     ; // [2:0]
1378 
      assign  p0_cmd_bl_i        =  p0_cmd_bl        ; // [5:0]
1379 
      assign  p0_cmd_byte_addr_i =  p0_cmd_byte_addr ; // [29:0]
1380 
      assign  p0_cmd_empty       =  p0_cmd_empty_i   ; //
1381 
      assign  p0_cmd_full        =  p0_cmd_full_i    ; //
1382 
      assign  p0_wr_clk_i        =  p0_wr_clk        ; //
1383 
      assign  p0_wr_en_i         =  p0_wr_en         ; //
1384 
      assign  p0_wr_mask_i       =  p0_wr_mask       ; // [C_P0_MASK_SIZE-1:0]
1385 
      assign  p0_wr_data_i       =  p0_wr_data       ; // [C_P0_DATA_PORT_SIZE-1:0]
1386 
      assign  p0_wr_full         =  p0_wr_full_i     ; //
1387 
      assign  p0_wr_empty        =  p0_wr_empty_i    ; //
1388 
      assign  p0_wr_count        =  p0_wr_count_i    ; // [6:0]
1389 
      assign  p0_wr_underrun     =  p0_wr_underrun_i ; //
1390 
      assign  p0_wr_error        =  p0_wr_error_i    ; //
1391 
      assign  p0_rd_clk_i        =  p0_rd_clk        ; //
1392 
      assign  p0_rd_en_i         =  p0_rd_en         ; //
1393 
      assign  p0_rd_data         =  p0_rd_data_i     ; // [C_P0_DATA_PORT_SIZE-1:0]
1394 
      assign  p0_rd_full         =  p0_rd_full_i     ; //
1395 
      assign  p0_rd_empty        =  p0_rd_empty_i    ; //
1396 
      assign  p0_rd_count        =  p0_rd_count_i    ; // [6:0]
1397 
      assign  p0_rd_overflow     =  p0_rd_overflow_i ; //
1398 
      assign  p0_rd_error        =  p0_rd_error_i    ; //
1399 
    end
1400 
    else begin : P0_UI_AXI
1401 
      assign  p0_arb_en_i        =  p0_arb_en;
1402 
      assign  s0_axi_araddr_i    = s0_axi_araddr & P_S0_AXI_ADDRMASK;
1403 
      assign  s0_axi_awaddr_i    = s0_axi_awaddr & P_S0_AXI_ADDRMASK;
1404 
      wire                     calib_done_synch;
1405 
 
1406 
      mcb_ui_top_synch #(
1407 
        .C_SYNCH_WIDTH          ( 1 )
1408 
      )
1409 
      axi_mcb_synch
1410 
      (
1411 
        .clk       ( s0_axi_aclk      ) ,
1412 
        .synch_in  ( uo_done_cal      ) ,
1413 
        .synch_out ( calib_done_synch )
1414 
      );
1415 
      axi_mcb #
1416 
        (
1417 
        .C_FAMILY                ( "spartan6"               ) ,
1418 
        .C_S_AXI_ID_WIDTH        ( C_S0_AXI_ID_WIDTH        ) ,
1419 
        .C_S_AXI_ADDR_WIDTH      ( C_S0_AXI_ADDR_WIDTH      ) ,
1420 
        .C_S_AXI_DATA_WIDTH      ( C_S0_AXI_DATA_WIDTH      ) ,
1421 
        .C_S_AXI_SUPPORTS_READ   ( C_S0_AXI_SUPPORTS_READ   ) ,
1422 
        .C_S_AXI_SUPPORTS_WRITE  ( C_S0_AXI_SUPPORTS_WRITE  ) ,
1423 
        .C_S_AXI_REG_EN0         ( C_S0_AXI_REG_EN0         ) ,
1424 
        .C_S_AXI_REG_EN1         ( C_S0_AXI_REG_EN1         ) ,
1425 
        .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S0_AXI_SUPPORTS_NARROW_BURST ) ,
1426 
        .C_MCB_ADDR_WIDTH        ( 30                       ) ,
1427 
        .C_MCB_DATA_WIDTH        ( C_P0_DATA_PORT_SIZE      ) ,
1428 
        .C_STRICT_COHERENCY      ( C_S0_AXI_STRICT_COHERENCY    ) ,
1429 
        .C_ENABLE_AP             ( C_S0_AXI_ENABLE_AP           )
1430 
        )
1431 
        p0_axi_mcb
1432 
        (
1433 
        .aclk              ( s0_axi_aclk        ),
1434 
        .aresetn           ( s0_axi_aresetn     ),
1435 
        .s_axi_awid        ( s0_axi_awid        ),
1436 
        .s_axi_awaddr      ( s0_axi_awaddr_i    ),
1437 
        .s_axi_awlen       ( s0_axi_awlen       ),
1438 
        .s_axi_awsize      ( s0_axi_awsize      ),
1439 
        .s_axi_awburst     ( s0_axi_awburst     ),
1440 
        .s_axi_awlock      ( s0_axi_awlock      ),
1441 
        .s_axi_awcache     ( s0_axi_awcache     ),
1442 
        .s_axi_awprot      ( s0_axi_awprot      ),
1443 
        .s_axi_awqos       ( s0_axi_awqos       ),
1444 
        .s_axi_awvalid     ( s0_axi_awvalid     ),
1445 
        .s_axi_awready     ( s0_axi_awready     ),
1446 
        .s_axi_wdata       ( s0_axi_wdata       ),
1447 
        .s_axi_wstrb       ( s0_axi_wstrb       ),
1448 
        .s_axi_wlast       ( s0_axi_wlast       ),
1449 
        .s_axi_wvalid      ( s0_axi_wvalid      ),
1450 
        .s_axi_wready      ( s0_axi_wready      ),
1451 
        .s_axi_bid         ( s0_axi_bid         ),
1452 
        .s_axi_bresp       ( s0_axi_bresp       ),
1453 
        .s_axi_bvalid      ( s0_axi_bvalid      ),
1454 
        .s_axi_bready      ( s0_axi_bready      ),
1455 
        .s_axi_arid        ( s0_axi_arid        ),
1456 
        .s_axi_araddr      ( s0_axi_araddr_i    ),
1457 
        .s_axi_arlen       ( s0_axi_arlen       ),
1458 
        .s_axi_arsize      ( s0_axi_arsize      ),
1459 
        .s_axi_arburst     ( s0_axi_arburst     ),
1460 
        .s_axi_arlock      ( s0_axi_arlock      ),
1461 
        .s_axi_arcache     ( s0_axi_arcache     ),
1462 
        .s_axi_arprot      ( s0_axi_arprot      ),
1463 
        .s_axi_arqos       ( s0_axi_arqos       ),
1464 
        .s_axi_arvalid     ( s0_axi_arvalid     ),
1465 
        .s_axi_arready     ( s0_axi_arready     ),
1466 
        .s_axi_rid         ( s0_axi_rid         ),
1467 
        .s_axi_rdata       ( s0_axi_rdata       ),
1468 
        .s_axi_rresp       ( s0_axi_rresp       ),
1469 
        .s_axi_rlast       ( s0_axi_rlast       ),
1470 
        .s_axi_rvalid      ( s0_axi_rvalid      ),
1471 
        .s_axi_rready      ( s0_axi_rready      ),
1472 
        .mcb_cmd_clk       ( p0_cmd_clk_i       ),
1473 
        .mcb_cmd_en        ( p0_cmd_en_i        ),
1474 
        .mcb_cmd_instr     ( p0_cmd_instr_i     ),
1475 
        .mcb_cmd_bl        ( p0_cmd_bl_i        ),
1476 
        .mcb_cmd_byte_addr ( p0_cmd_byte_addr_i ),
1477 
        .mcb_cmd_empty     ( p0_cmd_empty_i     ),
1478 
        .mcb_cmd_full      ( p0_cmd_full_i      ),
1479 
        .mcb_wr_clk        ( p0_wr_clk_i        ),
1480 
        .mcb_wr_en         ( p0_wr_en_i         ),
1481 
        .mcb_wr_mask       ( p0_wr_mask_i       ),
1482 
        .mcb_wr_data       ( p0_wr_data_i       ),
1483 
        .mcb_wr_full       ( p0_wr_full_i       ),
1484 
        .mcb_wr_empty      ( p0_wr_empty_i      ),
1485 
        .mcb_wr_count      ( p0_wr_count_i      ),
1486 
        .mcb_wr_underrun   ( p0_wr_underrun_i   ),
1487 
        .mcb_wr_error      ( p0_wr_error_i      ),
1488 
        .mcb_rd_clk        ( p0_rd_clk_i        ),
1489 
        .mcb_rd_en         ( p0_rd_en_i         ),
1490 
        .mcb_rd_data       ( p0_rd_data_i       ),
1491 
        .mcb_rd_full       ( p0_rd_full_i       ),
1492 
        .mcb_rd_empty      ( p0_rd_empty_i      ),
1493 
        .mcb_rd_count      ( p0_rd_count_i      ),
1494 
        .mcb_rd_overflow   ( p0_rd_overflow_i   ),
1495 
        .mcb_rd_error      ( p0_rd_error_i      ),
1496 
        .mcb_calib_done    ( calib_done_synch   )
1497 
        );
1498 
    end
1499 
  endgenerate
1500 
 
1501 
// P1 AXI Bridge Mux
1502 
  generate
1503 
    if (C_S1_AXI_ENABLE == 0) begin : P1_UI_MCB
1504 
      assign  p1_arb_en_i        =  p1_arb_en        ; //
1505 
      assign  p1_cmd_clk_i       =  p1_cmd_clk       ; //
1506 
      assign  p1_cmd_en_i        =  p1_cmd_en        ; //
1507 
      assign  p1_cmd_instr_i     =  p1_cmd_instr     ; // [2:0]
1508 
      assign  p1_cmd_bl_i        =  p1_cmd_bl        ; // [5:0]
1509 
      assign  p1_cmd_byte_addr_i =  p1_cmd_byte_addr ; // [29:0]
1510 
      assign  p1_cmd_empty       =  p1_cmd_empty_i   ; //
1511 
      assign  p1_cmd_full        =  p1_cmd_full_i    ; //
1512 
      assign  p1_wr_clk_i        =  p1_wr_clk        ; //
1513 
      assign  p1_wr_en_i         =  p1_wr_en         ; //
1514 
      assign  p1_wr_mask_i       =  p1_wr_mask       ; // [C_P1_MASK_SIZE-1:0]
1515 
      assign  p1_wr_data_i       =  p1_wr_data       ; // [C_P1_DATA_PORT_SIZE-1:0]
1516 
      assign  p1_wr_full         =  p1_wr_full_i     ; //
1517 
      assign  p1_wr_empty        =  p1_wr_empty_i    ; //
1518 
      assign  p1_wr_count        =  p1_wr_count_i    ; // [6:0]
1519 
      assign  p1_wr_underrun     =  p1_wr_underrun_i ; //
1520 
      assign  p1_wr_error        =  p1_wr_error_i    ; //
1521 
      assign  p1_rd_clk_i        =  p1_rd_clk        ; //
1522 
      assign  p1_rd_en_i         =  p1_rd_en         ; //
1523 
      assign  p1_rd_data         =  p1_rd_data_i     ; // [C_P1_DATA_PORT_SIZE-1:0]
1524 
      assign  p1_rd_full         =  p1_rd_full_i     ; //
1525 
      assign  p1_rd_empty        =  p1_rd_empty_i    ; //
1526 
      assign  p1_rd_count        =  p1_rd_count_i    ; // [6:0]
1527 
      assign  p1_rd_overflow     =  p1_rd_overflow_i ; //
1528 
      assign  p1_rd_error        =  p1_rd_error_i    ; //
1529 
    end
1530 
    else begin : P1_UI_AXI
1531 
      assign  p1_arb_en_i        =  p1_arb_en;
1532 
      assign  s1_axi_araddr_i    = s1_axi_araddr & P_S1_AXI_ADDRMASK;
1533 
      assign  s1_axi_awaddr_i    = s1_axi_awaddr & P_S1_AXI_ADDRMASK;
1534 
      wire                     calib_done_synch;
1535 
 
1536 
      mcb_ui_top_synch #(
1537 
        .C_SYNCH_WIDTH          ( 1 )
1538 
      )
1539 
      axi_mcb_synch
1540 
      (
1541 
        .clk                    ( s1_axi_aclk      ),
1542 
        .synch_in               ( uo_done_cal      ),
1543 
        .synch_out              ( calib_done_synch )
1544 
      );
1545 
      axi_mcb #
1546 
        (
1547 
        .C_FAMILY                ( "spartan6"               ) ,
1548 
        .C_S_AXI_ID_WIDTH        ( C_S1_AXI_ID_WIDTH        ) ,
1549 
        .C_S_AXI_ADDR_WIDTH      ( C_S1_AXI_ADDR_WIDTH      ) ,
1550 
        .C_S_AXI_DATA_WIDTH      ( C_S1_AXI_DATA_WIDTH      ) ,
1551 
        .C_S_AXI_SUPPORTS_READ   ( C_S1_AXI_SUPPORTS_READ   ) ,
1552 
        .C_S_AXI_SUPPORTS_WRITE  ( C_S1_AXI_SUPPORTS_WRITE  ) ,
1553 
        .C_S_AXI_REG_EN0         ( C_S1_AXI_REG_EN0         ) ,
1554 
        .C_S_AXI_REG_EN1         ( C_S1_AXI_REG_EN1         ) ,
1555 
        .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S1_AXI_SUPPORTS_NARROW_BURST ) ,
1556 
        .C_MCB_ADDR_WIDTH        ( 30                       ) ,
1557 
        .C_MCB_DATA_WIDTH        ( C_P1_DATA_PORT_SIZE      ) ,
1558 
        .C_STRICT_COHERENCY      ( C_S1_AXI_STRICT_COHERENCY    ) ,
1559 
        .C_ENABLE_AP             ( C_S1_AXI_ENABLE_AP           )
1560 
        )
1561 
        p1_axi_mcb
1562 
        (
1563 
        .aclk              ( s1_axi_aclk        ),
1564 
        .aresetn           ( s1_axi_aresetn     ),
1565 
        .s_axi_awid        ( s1_axi_awid        ),
1566 
        .s_axi_awaddr      ( s1_axi_awaddr_i    ),
1567 
        .s_axi_awlen       ( s1_axi_awlen       ),
1568 
        .s_axi_awsize      ( s1_axi_awsize      ),
1569 
        .s_axi_awburst     ( s1_axi_awburst     ),
1570 
        .s_axi_awlock      ( s1_axi_awlock      ),
1571 
        .s_axi_awcache     ( s1_axi_awcache     ),
1572 
        .s_axi_awprot      ( s1_axi_awprot      ),
1573 
        .s_axi_awqos       ( s1_axi_awqos       ),
1574 
        .s_axi_awvalid     ( s1_axi_awvalid     ),
1575 
        .s_axi_awready     ( s1_axi_awready     ),
1576 
        .s_axi_wdata       ( s1_axi_wdata       ),
1577 
        .s_axi_wstrb       ( s1_axi_wstrb       ),
1578 
        .s_axi_wlast       ( s1_axi_wlast       ),
1579 
        .s_axi_wvalid      ( s1_axi_wvalid      ),
1580 
        .s_axi_wready      ( s1_axi_wready      ),
1581 
        .s_axi_bid         ( s1_axi_bid         ),
1582 
        .s_axi_bresp       ( s1_axi_bresp       ),
1583 
        .s_axi_bvalid      ( s1_axi_bvalid      ),
1584 
        .s_axi_bready      ( s1_axi_bready      ),
1585 
        .s_axi_arid        ( s1_axi_arid        ),
1586 
        .s_axi_araddr      ( s1_axi_araddr_i    ),
1587 
        .s_axi_arlen       ( s1_axi_arlen       ),
1588 
        .s_axi_arsize      ( s1_axi_arsize      ),
1589 
        .s_axi_arburst     ( s1_axi_arburst     ),
1590 
        .s_axi_arlock      ( s1_axi_arlock      ),
1591 
        .s_axi_arcache     ( s1_axi_arcache     ),
1592 
        .s_axi_arprot      ( s1_axi_arprot      ),
1593 
        .s_axi_arqos       ( s1_axi_arqos       ),
1594 
        .s_axi_arvalid     ( s1_axi_arvalid     ),
1595 
        .s_axi_arready     ( s1_axi_arready     ),
1596 
        .s_axi_rid         ( s1_axi_rid         ),
1597 
        .s_axi_rdata       ( s1_axi_rdata       ),
1598 
        .s_axi_rresp       ( s1_axi_rresp       ),
1599 
        .s_axi_rlast       ( s1_axi_rlast       ),
1600 
        .s_axi_rvalid      ( s1_axi_rvalid      ),
1601 
        .s_axi_rready      ( s1_axi_rready      ),
1602 
        .mcb_cmd_clk       ( p1_cmd_clk_i       ),
1603 
        .mcb_cmd_en        ( p1_cmd_en_i        ),
1604 
        .mcb_cmd_instr     ( p1_cmd_instr_i     ),
1605 
        .mcb_cmd_bl        ( p1_cmd_bl_i        ),
1606 
        .mcb_cmd_byte_addr ( p1_cmd_byte_addr_i ),
1607 
        .mcb_cmd_empty     ( p1_cmd_empty_i     ),
1608 
        .mcb_cmd_full      ( p1_cmd_full_i      ),
1609 
        .mcb_wr_clk        ( p1_wr_clk_i        ),
1610 
        .mcb_wr_en         ( p1_wr_en_i         ),
1611 
        .mcb_wr_mask       ( p1_wr_mask_i       ),
1612 
        .mcb_wr_data       ( p1_wr_data_i       ),
1613 
        .mcb_wr_full       ( p1_wr_full_i       ),
1614 
        .mcb_wr_empty      ( p1_wr_empty_i      ),
1615 
        .mcb_wr_count      ( p1_wr_count_i      ),
1616 
        .mcb_wr_underrun   ( p1_wr_underrun_i   ),
1617 
        .mcb_wr_error      ( p1_wr_error_i      ),
1618 
        .mcb_rd_clk        ( p1_rd_clk_i        ),
1619 
        .mcb_rd_en         ( p1_rd_en_i         ),
1620 
        .mcb_rd_data       ( p1_rd_data_i       ),
1621 
        .mcb_rd_full       ( p1_rd_full_i       ),
1622 
        .mcb_rd_empty      ( p1_rd_empty_i      ),
1623 
        .mcb_rd_count      ( p1_rd_count_i      ),
1624 
        .mcb_rd_overflow   ( p1_rd_overflow_i   ),
1625 
        .mcb_rd_error      ( p1_rd_error_i      ),
1626 
        .mcb_calib_done    ( calib_done_synch   )
1627 
        );
1628 
    end
1629 
  endgenerate
1630 
 
1631 
// P2 AXI Bridge Mux
1632 
  generate
1633 
    if (C_S2_AXI_ENABLE == 0) begin : P2_UI_MCB
1634 
      assign  p2_arb_en_i        =  p2_arb_en        ; //
1635 
      assign  p2_cmd_clk_i       =  p2_cmd_clk       ; //
1636 
      assign  p2_cmd_en_i        =  p2_cmd_en        ; //
1637 
      assign  p2_cmd_instr_i     =  p2_cmd_instr     ; // [2:0]
1638 
      assign  p2_cmd_bl_i        =  p2_cmd_bl        ; // [5:0]
1639 
      assign  p2_cmd_byte_addr_i =  p2_cmd_byte_addr ; // [29:0]
1640 
      assign  p2_cmd_empty       =  p2_cmd_empty_i   ; //
1641 
      assign  p2_cmd_full        =  p2_cmd_full_i    ; //
1642 
      assign  p2_wr_clk_i        =  p2_wr_clk        ; //
1643 
      assign  p2_wr_en_i         =  p2_wr_en         ; //
1644 
      assign  p2_wr_mask_i       =  p2_wr_mask       ; // [3:0]
1645 
      assign  p2_wr_data_i       =  p2_wr_data       ; // [31:0]
1646 
      assign  p2_wr_full         =  p2_wr_full_i     ; //
1647 
      assign  p2_wr_empty        =  p2_wr_empty_i    ; //
1648 
      assign  p2_wr_count        =  p2_wr_count_i    ; // [6:0]
1649 
      assign  p2_wr_underrun     =  p2_wr_underrun_i ; //
1650 
      assign  p2_wr_error        =  p2_wr_error_i    ; //
1651 
      assign  p2_rd_clk_i        =  p2_rd_clk        ; //
1652 
      assign  p2_rd_en_i         =  p2_rd_en         ; //
1653 
      assign  p2_rd_data         =  p2_rd_data_i     ; // [31:0]
1654 
      assign  p2_rd_full         =  p2_rd_full_i     ; //
1655 
      assign  p2_rd_empty        =  p2_rd_empty_i    ; //
1656 
      assign  p2_rd_count        =  p2_rd_count_i    ; // [6:0]
1657 
      assign  p2_rd_overflow     =  p2_rd_overflow_i ; //
1658 
      assign  p2_rd_error        =  p2_rd_error_i    ; //
1659 
    end
1660 
    else begin : P2_UI_AXI
1661 
      assign  p2_arb_en_i        =  p2_arb_en;
1662 
      assign  s2_axi_araddr_i    = s2_axi_araddr & P_S2_AXI_ADDRMASK;
1663 
      assign  s2_axi_awaddr_i    = s2_axi_awaddr & P_S2_AXI_ADDRMASK;
1664 
      wire                     calib_done_synch;
1665 
 
1666 
      mcb_ui_top_synch #(
1667 
        .C_SYNCH_WIDTH          ( 1 )
1668 
      )
1669 
      axi_mcb_synch
1670 
      (
1671 
        .clk                    ( s2_axi_aclk      ),
1672 
        .synch_in               ( uo_done_cal      ),
1673 
        .synch_out              ( calib_done_synch )
1674 
      );
1675 
      axi_mcb #
1676 
        (
1677 
        .C_FAMILY                ( "spartan6"               ) ,
1678 
        .C_S_AXI_ID_WIDTH        ( C_S2_AXI_ID_WIDTH        ) ,
1679 
        .C_S_AXI_ADDR_WIDTH      ( C_S2_AXI_ADDR_WIDTH      ) ,
1680 
        .C_S_AXI_DATA_WIDTH      ( 32                       ) ,
1681 
        .C_S_AXI_SUPPORTS_READ   ( C_S2_AXI_SUPPORTS_READ   ) ,
1682 
        .C_S_AXI_SUPPORTS_WRITE  ( C_S2_AXI_SUPPORTS_WRITE  ) ,
1683 
        .C_S_AXI_REG_EN0         ( C_S2_AXI_REG_EN0         ) ,
1684 
        .C_S_AXI_REG_EN1         ( C_S2_AXI_REG_EN1         ) ,
1685 
        .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S2_AXI_SUPPORTS_NARROW_BURST ) ,
1686 
        .C_MCB_ADDR_WIDTH        ( 30                       ) ,
1687 
        .C_MCB_DATA_WIDTH        ( 32                       ) ,
1688 
        .C_STRICT_COHERENCY      ( C_S2_AXI_STRICT_COHERENCY    ) ,
1689 
        .C_ENABLE_AP             ( C_S2_AXI_ENABLE_AP           )
1690 
        )
1691 
        p2_axi_mcb
1692 
        (
1693 
        .aclk              ( s2_axi_aclk        ),
1694 
        .aresetn           ( s2_axi_aresetn     ),
1695 
        .s_axi_awid        ( s2_axi_awid        ),
1696 
        .s_axi_awaddr      ( s2_axi_awaddr_i    ),
1697 
        .s_axi_awlen       ( s2_axi_awlen       ),
1698 
        .s_axi_awsize      ( s2_axi_awsize      ),
1699 
        .s_axi_awburst     ( s2_axi_awburst     ),
1700 
        .s_axi_awlock      ( s2_axi_awlock      ),
1701 
        .s_axi_awcache     ( s2_axi_awcache     ),
1702 
        .s_axi_awprot      ( s2_axi_awprot      ),
1703 
        .s_axi_awqos       ( s2_axi_awqos       ),
1704 
        .s_axi_awvalid     ( s2_axi_awvalid     ),
1705 
        .s_axi_awready     ( s2_axi_awready     ),
1706 
        .s_axi_wdata       ( s2_axi_wdata       ),
1707 
        .s_axi_wstrb       ( s2_axi_wstrb       ),
1708 
        .s_axi_wlast       ( s2_axi_wlast       ),
1709 
        .s_axi_wvalid      ( s2_axi_wvalid      ),
1710 
        .s_axi_wready      ( s2_axi_wready      ),
1711 
        .s_axi_bid         ( s2_axi_bid         ),
1712 
        .s_axi_bresp       ( s2_axi_bresp       ),
1713 
        .s_axi_bvalid      ( s2_axi_bvalid      ),
1714 
        .s_axi_bready      ( s2_axi_bready      ),
1715 
        .s_axi_arid        ( s2_axi_arid        ),
1716 
        .s_axi_araddr      ( s2_axi_araddr_i    ),
1717 
        .s_axi_arlen       ( s2_axi_arlen       ),
1718 
        .s_axi_arsize      ( s2_axi_arsize      ),
1719 
        .s_axi_arburst     ( s2_axi_arburst     ),
1720 
        .s_axi_arlock      ( s2_axi_arlock      ),
1721 
        .s_axi_arcache     ( s2_axi_arcache     ),
1722 
        .s_axi_arprot      ( s2_axi_arprot      ),
1723 
        .s_axi_arqos       ( s2_axi_arqos       ),
1724 
        .s_axi_arvalid     ( s2_axi_arvalid     ),
1725 
        .s_axi_arready     ( s2_axi_arready     ),
1726 
        .s_axi_rid         ( s2_axi_rid         ),
1727 
        .s_axi_rdata       ( s2_axi_rdata       ),
1728 
        .s_axi_rresp       ( s2_axi_rresp       ),
1729 
        .s_axi_rlast       ( s2_axi_rlast       ),
1730 
        .s_axi_rvalid      ( s2_axi_rvalid      ),
1731 
        .s_axi_rready      ( s2_axi_rready      ),
1732 
        .mcb_cmd_clk       ( p2_cmd_clk_i       ),
1733 
        .mcb_cmd_en        ( p2_cmd_en_i        ),
1734 
        .mcb_cmd_instr     ( p2_cmd_instr_i     ),
1735 
        .mcb_cmd_bl        ( p2_cmd_bl_i        ),
1736 
        .mcb_cmd_byte_addr ( p2_cmd_byte_addr_i ),
1737 
        .mcb_cmd_empty     ( p2_cmd_empty_i     ),
1738 
        .mcb_cmd_full      ( p2_cmd_full_i      ),
1739 
        .mcb_wr_clk        ( p2_wr_clk_i        ),
1740 
        .mcb_wr_en         ( p2_wr_en_i         ),
1741 
        .mcb_wr_mask       ( p2_wr_mask_i       ),
1742 
        .mcb_wr_data       ( p2_wr_data_i       ),
1743 
        .mcb_wr_full       ( p2_wr_full_i       ),
1744 
        .mcb_wr_empty      ( p2_wr_empty_i      ),
1745 
        .mcb_wr_count      ( p2_wr_count_i      ),
1746 
        .mcb_wr_underrun   ( p2_wr_underrun_i   ),
1747 
        .mcb_wr_error      ( p2_wr_error_i      ),
1748 
        .mcb_rd_clk        ( p2_rd_clk_i        ),
1749 
        .mcb_rd_en         ( p2_rd_en_i         ),
1750 
        .mcb_rd_data       ( p2_rd_data_i       ),
1751 
        .mcb_rd_full       ( p2_rd_full_i       ),
1752 
        .mcb_rd_empty      ( p2_rd_empty_i      ),
1753 
        .mcb_rd_count      ( p2_rd_count_i      ),
1754 
        .mcb_rd_overflow   ( p2_rd_overflow_i   ),
1755 
        .mcb_rd_error      ( p2_rd_error_i      ),
1756 
        .mcb_calib_done    ( calib_done_synch   )
1757 
        );
1758 
    end
1759 
  endgenerate
1760 
 
1761 
// P3 AXI Bridge Mux
1762 
  generate
1763 
    if (C_S3_AXI_ENABLE == 0) begin : P3_UI_MCB
1764 
      assign  p3_arb_en_i        =  p3_arb_en        ; //
1765 
      assign  p3_cmd_clk_i       =  p3_cmd_clk       ; //
1766 
      assign  p3_cmd_en_i        =  p3_cmd_en        ; //
1767 
      assign  p3_cmd_instr_i     =  p3_cmd_instr     ; // [2:0]
1768 
      assign  p3_cmd_bl_i        =  p3_cmd_bl        ; // [5:0]
1769 
      assign  p3_cmd_byte_addr_i =  p3_cmd_byte_addr ; // [29:0]
1770 
      assign  p3_cmd_empty       =  p3_cmd_empty_i   ; //
1771 
      assign  p3_cmd_full        =  p3_cmd_full_i    ; //
1772 
      assign  p3_wr_clk_i        =  p3_wr_clk        ; //
1773 
      assign  p3_wr_en_i         =  p3_wr_en         ; //
1774 
      assign  p3_wr_mask_i       =  p3_wr_mask       ; // [3:0]
1775 
      assign  p3_wr_data_i       =  p3_wr_data       ; // [31:0]
1776 
      assign  p3_wr_full         =  p3_wr_full_i     ; //
1777 
      assign  p3_wr_empty        =  p3_wr_empty_i    ; //
1778 
      assign  p3_wr_count        =  p3_wr_count_i    ; // [6:0]
1779 
      assign  p3_wr_underrun     =  p3_wr_underrun_i ; //
1780 
      assign  p3_wr_error        =  p3_wr_error_i    ; //
1781 
      assign  p3_rd_clk_i        =  p3_rd_clk        ; //
1782 
      assign  p3_rd_en_i         =  p3_rd_en         ; //
1783 
      assign  p3_rd_data         =  p3_rd_data_i     ; // [31:0]
1784 
      assign  p3_rd_full         =  p3_rd_full_i     ; //
1785 
      assign  p3_rd_empty        =  p3_rd_empty_i    ; //
1786 
      assign  p3_rd_count        =  p3_rd_count_i    ; // [6:0]
1787 
      assign  p3_rd_overflow     =  p3_rd_overflow_i ; //
1788 
      assign  p3_rd_error        =  p3_rd_error_i    ; //
1789 
    end
1790 
    else begin : P3_UI_AXI
1791 
      assign  p3_arb_en_i        =  p3_arb_en;
1792 
      assign  s3_axi_araddr_i    = s3_axi_araddr & P_S3_AXI_ADDRMASK;
1793 
      assign  s3_axi_awaddr_i    = s3_axi_awaddr & P_S3_AXI_ADDRMASK;
1794 
      wire                     calib_done_synch;
1795 
 
1796 
      mcb_ui_top_synch #(
1797 
        .C_SYNCH_WIDTH          ( 1 )
1798 
      )
1799 
      axi_mcb_synch
1800 
      (
1801 
        .clk                    ( s3_axi_aclk      ),
1802 
        .synch_in               ( uo_done_cal      ),
1803 
        .synch_out              ( calib_done_synch )
1804 
      );
1805 
 
1806 
      axi_mcb #
1807 
        (
1808 
        .C_FAMILY                ( "spartan6"               ) ,
1809 
        .C_S_AXI_ID_WIDTH        ( C_S3_AXI_ID_WIDTH        ) ,
1810 
        .C_S_AXI_ADDR_WIDTH      ( C_S3_AXI_ADDR_WIDTH      ) ,
1811 
        .C_S_AXI_DATA_WIDTH      ( 32                       ) ,
1812 
        .C_S_AXI_SUPPORTS_READ   ( C_S3_AXI_SUPPORTS_READ   ) ,
1813 
        .C_S_AXI_SUPPORTS_WRITE  ( C_S3_AXI_SUPPORTS_WRITE  ) ,
1814 
        .C_S_AXI_REG_EN0         ( C_S3_AXI_REG_EN0         ) ,
1815 
        .C_S_AXI_REG_EN1         ( C_S3_AXI_REG_EN1         ) ,
1816 
        .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S3_AXI_SUPPORTS_NARROW_BURST ) ,
1817 
        .C_MCB_ADDR_WIDTH        ( 30                       ) ,
1818 
        .C_MCB_DATA_WIDTH        ( 32                       ) ,
1819 
        .C_STRICT_COHERENCY      ( C_S3_AXI_STRICT_COHERENCY    ) ,
1820 
        .C_ENABLE_AP             ( C_S3_AXI_ENABLE_AP           )
1821 
        )
1822 
        p3_axi_mcb
1823 
        (
1824 
        .aclk              ( s3_axi_aclk        ),
1825 
        .aresetn           ( s3_axi_aresetn     ),
1826 
        .s_axi_awid        ( s3_axi_awid        ),
1827 
        .s_axi_awaddr      ( s3_axi_awaddr_i    ),
1828 
        .s_axi_awlen       ( s3_axi_awlen       ),
1829 
        .s_axi_awsize      ( s3_axi_awsize      ),
1830 
        .s_axi_awburst     ( s3_axi_awburst     ),
1831 
        .s_axi_awlock      ( s3_axi_awlock      ),
1832 
        .s_axi_awcache     ( s3_axi_awcache     ),
1833 
        .s_axi_awprot      ( s3_axi_awprot      ),
1834 
        .s_axi_awqos       ( s3_axi_awqos       ),
1835 
        .s_axi_awvalid     ( s3_axi_awvalid     ),
1836 
        .s_axi_awready     ( s3_axi_awready     ),
1837 
        .s_axi_wdata       ( s3_axi_wdata       ),
1838 
        .s_axi_wstrb       ( s3_axi_wstrb       ),
1839 
        .s_axi_wlast       ( s3_axi_wlast       ),
1840 
        .s_axi_wvalid      ( s3_axi_wvalid      ),
1841 
        .s_axi_wready      ( s3_axi_wready      ),
1842 
        .s_axi_bid         ( s3_axi_bid         ),
1843 
        .s_axi_bresp       ( s3_axi_bresp       ),
1844 
        .s_axi_bvalid      ( s3_axi_bvalid      ),
1845 
        .s_axi_bready      ( s3_axi_bready      ),
1846 
        .s_axi_arid        ( s3_axi_arid        ),
1847 
        .s_axi_araddr      ( s3_axi_araddr_i    ),
1848 
        .s_axi_arlen       ( s3_axi_arlen       ),
1849 
        .s_axi_arsize      ( s3_axi_arsize      ),
1850 
        .s_axi_arburst     ( s3_axi_arburst     ),
1851 
        .s_axi_arlock      ( s3_axi_arlock      ),
1852 
        .s_axi_arcache     ( s3_axi_arcache     ),
1853 
        .s_axi_arprot      ( s3_axi_arprot      ),
1854 
        .s_axi_arqos       ( s3_axi_arqos       ),
1855 
        .s_axi_arvalid     ( s3_axi_arvalid     ),
1856 
        .s_axi_arready     ( s3_axi_arready     ),
1857 
        .s_axi_rid         ( s3_axi_rid         ),
1858 
        .s_axi_rdata       ( s3_axi_rdata       ),
1859 
        .s_axi_rresp       ( s3_axi_rresp       ),
1860 
        .s_axi_rlast       ( s3_axi_rlast       ),
1861 
        .s_axi_rvalid      ( s3_axi_rvalid      ),
1862 
        .s_axi_rready      ( s3_axi_rready      ),
1863 
        .mcb_cmd_clk       ( p3_cmd_clk_i       ),
1864 
        .mcb_cmd_en        ( p3_cmd_en_i        ),
1865 
        .mcb_cmd_instr     ( p3_cmd_instr_i     ),
1866 
        .mcb_cmd_bl        ( p3_cmd_bl_i        ),
1867 
        .mcb_cmd_byte_addr ( p3_cmd_byte_addr_i ),
1868 
        .mcb_cmd_empty     ( p3_cmd_empty_i     ),
1869 
        .mcb_cmd_full      ( p3_cmd_full_i      ),
1870 
        .mcb_wr_clk        ( p3_wr_clk_i        ),
1871 
        .mcb_wr_en         ( p3_wr_en_i         ),
1872 
        .mcb_wr_mask       ( p3_wr_mask_i       ),
1873 
        .mcb_wr_data       ( p3_wr_data_i       ),
1874 
        .mcb_wr_full       ( p3_wr_full_i       ),
1875 
        .mcb_wr_empty      ( p3_wr_empty_i      ),
1876 
        .mcb_wr_count      ( p3_wr_count_i      ),
1877 
        .mcb_wr_underrun   ( p3_wr_underrun_i   ),
1878 
        .mcb_wr_error      ( p3_wr_error_i      ),
1879 
        .mcb_rd_clk        ( p3_rd_clk_i        ),
1880 
        .mcb_rd_en         ( p3_rd_en_i         ),
1881 
        .mcb_rd_data       ( p3_rd_data_i       ),
1882 
        .mcb_rd_full       ( p3_rd_full_i       ),
1883 
        .mcb_rd_empty      ( p3_rd_empty_i      ),
1884 
        .mcb_rd_count      ( p3_rd_count_i      ),
1885 
        .mcb_rd_overflow   ( p3_rd_overflow_i   ),
1886 
        .mcb_rd_error      ( p3_rd_error_i      ),
1887 
        .mcb_calib_done    ( calib_done_synch   )
1888 
        );
1889 
    end
1890 
  endgenerate
1891 
 
1892 
// P4 AXI Bridge Mux
1893 
  generate
1894 
    if (C_S4_AXI_ENABLE == 0) begin : P4_UI_MCB
1895 
      assign  p4_arb_en_i        =  p4_arb_en        ; //
1896 
      assign  p4_cmd_clk_i       =  p4_cmd_clk       ; //
1897 
      assign  p4_cmd_en_i        =  p4_cmd_en        ; //
1898 
      assign  p4_cmd_instr_i     =  p4_cmd_instr     ; // [2:0]
1899 
      assign  p4_cmd_bl_i        =  p4_cmd_bl        ; // [5:0]
1900 
      assign  p4_cmd_byte_addr_i =  p4_cmd_byte_addr ; // [29:0]
1901 
      assign  p4_cmd_empty       =  p4_cmd_empty_i   ; //
1902 
      assign  p4_cmd_full        =  p4_cmd_full_i    ; //
1903 
      assign  p4_wr_clk_i        =  p4_wr_clk        ; //
1904 
      assign  p4_wr_en_i         =  p4_wr_en         ; //
1905 
      assign  p4_wr_mask_i       =  p4_wr_mask       ; // [3:0]
1906 
      assign  p4_wr_data_i       =  p4_wr_data       ; // [31:0]
1907 
      assign  p4_wr_full         =  p4_wr_full_i     ; //
1908 
      assign  p4_wr_empty        =  p4_wr_empty_i    ; //
1909 
      assign  p4_wr_count        =  p4_wr_count_i    ; // [6:0]
1910 
      assign  p4_wr_underrun     =  p4_wr_underrun_i ; //
1911 
      assign  p4_wr_error        =  p4_wr_error_i    ; //
1912 
      assign  p4_rd_clk_i        =  p4_rd_clk        ; //
1913 
      assign  p4_rd_en_i         =  p4_rd_en         ; //
1914 
      assign  p4_rd_data         =  p4_rd_data_i     ; // [31:0]
1915 
      assign  p4_rd_full         =  p4_rd_full_i     ; //
1916 
      assign  p4_rd_empty        =  p4_rd_empty_i    ; //
1917 
      assign  p4_rd_count        =  p4_rd_count_i    ; // [6:0]
1918 
      assign  p4_rd_overflow     =  p4_rd_overflow_i ; //
1919 
      assign  p4_rd_error        =  p4_rd_error_i    ; //
1920 
    end
1921 
    else begin : P4_UI_AXI
1922 
      assign  p4_arb_en_i        =  p4_arb_en;
1923 
      assign  s4_axi_araddr_i    = s4_axi_araddr & P_S4_AXI_ADDRMASK;
1924 
      assign  s4_axi_awaddr_i    = s4_axi_awaddr & P_S4_AXI_ADDRMASK;
1925 
      wire                     calib_done_synch;
1926 
 
1927 
      mcb_ui_top_synch #(
1928 
        .C_SYNCH_WIDTH          ( 1 )
1929 
      )
1930 
      axi_mcb_synch
1931 
      (
1932 
        .clk                    ( s4_axi_aclk      ),
1933 
        .synch_in               ( uo_done_cal      ),
1934 
        .synch_out              ( calib_done_synch )
1935 
      );
1936 
 
1937 
      axi_mcb #
1938 
        (
1939 
        .C_FAMILY                ( "spartan6"               ) ,
1940 
        .C_S_AXI_ID_WIDTH        ( C_S4_AXI_ID_WIDTH        ) ,
1941 
        .C_S_AXI_ADDR_WIDTH      ( C_S4_AXI_ADDR_WIDTH      ) ,
1942 
        .C_S_AXI_DATA_WIDTH      ( 32                       ) ,
1943 
        .C_S_AXI_SUPPORTS_READ   ( C_S4_AXI_SUPPORTS_READ   ) ,
1944 
        .C_S_AXI_SUPPORTS_WRITE  ( C_S4_AXI_SUPPORTS_WRITE  ) ,
1945 
        .C_S_AXI_REG_EN0         ( C_S4_AXI_REG_EN0         ) ,
1946 
        .C_S_AXI_REG_EN1         ( C_S4_AXI_REG_EN1         ) ,
1947 
        .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S4_AXI_SUPPORTS_NARROW_BURST ) ,
1948 
        .C_MCB_ADDR_WIDTH        ( 30                       ) ,
1949 
        .C_MCB_DATA_WIDTH        ( 32                       ) ,
1950 
        .C_STRICT_COHERENCY      ( C_S4_AXI_STRICT_COHERENCY    ) ,
1951 
        .C_ENABLE_AP             ( C_S4_AXI_ENABLE_AP           )
1952 
        )
1953 
        p4_axi_mcb
1954 
        (
1955 
        .aclk              ( s4_axi_aclk        ),
1956 
        .aresetn           ( s4_axi_aresetn     ),
1957 
        .s_axi_awid        ( s4_axi_awid        ),
1958 
        .s_axi_awaddr      ( s4_axi_awaddr_i    ),
1959 
        .s_axi_awlen       ( s4_axi_awlen       ),
1960 
        .s_axi_awsize      ( s4_axi_awsize      ),
1961 
        .s_axi_awburst     ( s4_axi_awburst     ),
1962 
        .s_axi_awlock      ( s4_axi_awlock      ),
1963 
        .s_axi_awcache     ( s4_axi_awcache     ),
1964 
        .s_axi_awprot      ( s4_axi_awprot      ),
1965 
        .s_axi_awqos       ( s4_axi_awqos       ),
1966 
        .s_axi_awvalid     ( s4_axi_awvalid     ),
1967 
        .s_axi_awready     ( s4_axi_awready     ),
1968 
        .s_axi_wdata       ( s4_axi_wdata       ),
1969 
        .s_axi_wstrb       ( s4_axi_wstrb       ),
1970 
        .s_axi_wlast       ( s4_axi_wlast       ),
1971 
        .s_axi_wvalid      ( s4_axi_wvalid      ),
1972 
        .s_axi_wready      ( s4_axi_wready      ),
1973 
        .s_axi_bid         ( s4_axi_bid         ),
1974 
        .s_axi_bresp       ( s4_axi_bresp       ),
1975 
        .s_axi_bvalid      ( s4_axi_bvalid      ),
1976 
        .s_axi_bready      ( s4_axi_bready      ),
1977 
        .s_axi_arid        ( s4_axi_arid        ),
1978 
        .s_axi_araddr      ( s4_axi_araddr_i    ),
1979 
        .s_axi_arlen       ( s4_axi_arlen       ),
1980 
        .s_axi_arsize      ( s4_axi_arsize      ),
1981 
        .s_axi_arburst     ( s4_axi_arburst     ),
1982 
        .s_axi_arlock      ( s4_axi_arlock      ),
1983 
        .s_axi_arcache     ( s4_axi_arcache     ),
1984 
        .s_axi_arprot      ( s4_axi_arprot      ),
1985 
        .s_axi_arqos       ( s4_axi_arqos       ),
1986 
        .s_axi_arvalid     ( s4_axi_arvalid     ),
1987 
        .s_axi_arready     ( s4_axi_arready     ),
1988 
        .s_axi_rid         ( s4_axi_rid         ),
1989 
        .s_axi_rdata       ( s4_axi_rdata       ),
1990 
        .s_axi_rresp       ( s4_axi_rresp       ),
1991 
        .s_axi_rlast       ( s4_axi_rlast       ),
1992 
        .s_axi_rvalid      ( s4_axi_rvalid      ),
1993 
        .s_axi_rready      ( s4_axi_rready      ),
1994 
        .mcb_cmd_clk       ( p4_cmd_clk_i       ),
1995 
        .mcb_cmd_en        ( p4_cmd_en_i        ),
1996 
        .mcb_cmd_instr     ( p4_cmd_instr_i     ),
1997 
        .mcb_cmd_bl        ( p4_cmd_bl_i        ),
1998 
        .mcb_cmd_byte_addr ( p4_cmd_byte_addr_i ),
1999 
        .mcb_cmd_empty     ( p4_cmd_empty_i     ),
2000 
        .mcb_cmd_full      ( p4_cmd_full_i      ),
2001 
        .mcb_wr_clk        ( p4_wr_clk_i        ),
2002 
        .mcb_wr_en         ( p4_wr_en_i         ),
2003 
        .mcb_wr_mask       ( p4_wr_mask_i       ),
2004 
        .mcb_wr_data       ( p4_wr_data_i       ),
2005 
        .mcb_wr_full       ( p4_wr_full_i       ),
2006 
        .mcb_wr_empty      ( p4_wr_empty_i      ),
2007 
        .mcb_wr_count      ( p4_wr_count_i      ),
2008 
        .mcb_wr_underrun   ( p4_wr_underrun_i   ),
2009 
        .mcb_wr_error      ( p4_wr_error_i      ),
2010 
        .mcb_rd_clk        ( p4_rd_clk_i        ),
2011 
        .mcb_rd_en         ( p4_rd_en_i         ),
2012 
        .mcb_rd_data       ( p4_rd_data_i       ),
2013 
        .mcb_rd_full       ( p4_rd_full_i       ),
2014 
        .mcb_rd_empty      ( p4_rd_empty_i      ),
2015 
        .mcb_rd_count      ( p4_rd_count_i      ),
2016 
        .mcb_rd_overflow   ( p4_rd_overflow_i   ),
2017 
        .mcb_rd_error      ( p4_rd_error_i      ),
2018 
        .mcb_calib_done    ( calib_done_synch   )
2019 
        );
2020 
    end
2021 
  endgenerate
2022 
 
2023 
// P5 AXI Bridge Mux
2024 
  generate
2025 
    if (C_S5_AXI_ENABLE == 0) begin : P5_UI_MCB
2026 
      assign  p5_arb_en_i        =  p5_arb_en        ; //
2027 
      assign  p5_cmd_clk_i       =  p5_cmd_clk       ; //
2028 
      assign  p5_cmd_en_i        =  p5_cmd_en        ; //
2029 
      assign  p5_cmd_instr_i     =  p5_cmd_instr     ; // [2:0]
2030 
      assign  p5_cmd_bl_i        =  p5_cmd_bl        ; // [5:0]
2031 
      assign  p5_cmd_byte_addr_i =  p5_cmd_byte_addr ; // [29:0]
2032 
      assign  p5_cmd_empty       =  p5_cmd_empty_i   ; //
2033 
      assign  p5_cmd_full        =  p5_cmd_full_i    ; //
2034 
      assign  p5_wr_clk_i        =  p5_wr_clk        ; //
2035 
      assign  p5_wr_en_i         =  p5_wr_en         ; //
2036 
      assign  p5_wr_mask_i       =  p5_wr_mask       ; // [3:0]
2037 
      assign  p5_wr_data_i       =  p5_wr_data       ; // [31:0]
2038 
      assign  p5_wr_full         =  p5_wr_full_i     ; //
2039 
      assign  p5_wr_empty        =  p5_wr_empty_i    ; //
2040 
      assign  p5_wr_count        =  p5_wr_count_i    ; // [6:0]
2041 
      assign  p5_wr_underrun     =  p5_wr_underrun_i ; //
2042 
      assign  p5_wr_error        =  p5_wr_error_i    ; //
2043 
      assign  p5_rd_clk_i        =  p5_rd_clk        ; //
2044 
      assign  p5_rd_en_i         =  p5_rd_en         ; //
2045 
      assign  p5_rd_data         =  p5_rd_data_i     ; // [31:0]
2046 
      assign  p5_rd_full         =  p5_rd_full_i     ; //
2047 
      assign  p5_rd_empty        =  p5_rd_empty_i    ; //
2048 
      assign  p5_rd_count        =  p5_rd_count_i    ; // [6:0]
2049 
      assign  p5_rd_overflow     =  p5_rd_overflow_i ; //
2050 
      assign  p5_rd_error        =  p5_rd_error_i    ; //
2051 
    end
2052 
    else begin : P5_UI_AXI
2053 
      assign  p5_arb_en_i        =  p5_arb_en;
2054 
      assign  s5_axi_araddr_i    = s5_axi_araddr & P_S5_AXI_ADDRMASK;
2055 
      assign  s5_axi_awaddr_i    = s5_axi_awaddr & P_S5_AXI_ADDRMASK;
2056 
      wire                     calib_done_synch;
2057 
 
2058 
      mcb_ui_top_synch #(
2059 
        .C_SYNCH_WIDTH          ( 1 )
2060 
      )
2061 
      axi_mcb_synch
2062 
      (
2063 
        .clk                    ( s5_axi_aclk      ),
2064 
        .synch_in               ( uo_done_cal      ),
2065 
        .synch_out              ( calib_done_synch )
2066 
      );
2067 
 
2068 
      axi_mcb #
2069 
        (
2070 
        .C_FAMILY                ( "spartan6"               ) ,
2071 
        .C_S_AXI_ID_WIDTH        ( C_S5_AXI_ID_WIDTH        ) ,
2072 
        .C_S_AXI_ADDR_WIDTH      ( C_S5_AXI_ADDR_WIDTH      ) ,
2073 
        .C_S_AXI_DATA_WIDTH      ( 32                       ) ,
2074 
        .C_S_AXI_SUPPORTS_READ   ( C_S5_AXI_SUPPORTS_READ   ) ,
2075 
        .C_S_AXI_SUPPORTS_WRITE  ( C_S5_AXI_SUPPORTS_WRITE  ) ,
2076 
        .C_S_AXI_REG_EN0         ( C_S5_AXI_REG_EN0         ) ,
2077 
        .C_S_AXI_REG_EN1         ( C_S5_AXI_REG_EN1         ) ,
2078 
        .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S5_AXI_SUPPORTS_NARROW_BURST ) ,
2079 
        .C_MCB_ADDR_WIDTH        ( 30                       ) ,
2080 
        .C_MCB_DATA_WIDTH        ( 32                       ) ,
2081 
        .C_STRICT_COHERENCY      ( C_S5_AXI_STRICT_COHERENCY    ) ,
2082 
        .C_ENABLE_AP             ( C_S5_AXI_ENABLE_AP           )
2083 
        )
2084 
        p5_axi_mcb
2085 
        (
2086 
        .aclk              ( s5_axi_aclk        ),
2087 
        .aresetn           ( s5_axi_aresetn     ),
2088 
        .s_axi_awid        ( s5_axi_awid        ),
2089 
        .s_axi_awaddr      ( s5_axi_awaddr_i    ),
2090 
        .s_axi_awlen       ( s5_axi_awlen       ),
2091 
        .s_axi_awsize      ( s5_axi_awsize      ),
2092 
        .s_axi_awburst     ( s5_axi_awburst     ),
2093 
        .s_axi_awlock      ( s5_axi_awlock      ),
2094 
        .s_axi_awcache     ( s5_axi_awcache     ),
2095 
        .s_axi_awprot      ( s5_axi_awprot      ),
2096 
        .s_axi_awqos       ( s5_axi_awqos       ),
2097 
        .s_axi_awvalid     ( s5_axi_awvalid     ),
2098 
        .s_axi_awready     ( s5_axi_awready     ),
2099 
        .s_axi_wdata       ( s5_axi_wdata       ),
2100 
        .s_axi_wstrb       ( s5_axi_wstrb       ),
2101 
        .s_axi_wlast       ( s5_axi_wlast       ),
2102 
        .s_axi_wvalid      ( s5_axi_wvalid      ),
2103 
        .s_axi_wready      ( s5_axi_wready      ),
2104 
        .s_axi_bid         ( s5_axi_bid         ),
2105 
        .s_axi_bresp       ( s5_axi_bresp       ),
2106 
        .s_axi_bvalid      ( s5_axi_bvalid      ),
2107 
        .s_axi_bready      ( s5_axi_bready      ),
2108 
        .s_axi_arid        ( s5_axi_arid        ),
2109 
        .s_axi_araddr      ( s5_axi_araddr_i    ),
2110 
        .s_axi_arlen       ( s5_axi_arlen       ),
2111 
        .s_axi_arsize      ( s5_axi_arsize      ),
2112 
        .s_axi_arburst     ( s5_axi_arburst     ),
2113 
        .s_axi_arlock      ( s5_axi_arlock      ),
2114 
        .s_axi_arcache     ( s5_axi_arcache     ),
2115 
        .s_axi_arprot      ( s5_axi_arprot      ),
2116 
        .s_axi_arqos       ( s5_axi_arqos       ),
2117 
        .s_axi_arvalid     ( s5_axi_arvalid     ),
2118 
        .s_axi_arready     ( s5_axi_arready     ),
2119 
        .s_axi_rid         ( s5_axi_rid         ),
2120 
        .s_axi_rdata       ( s5_axi_rdata       ),
2121 
        .s_axi_rresp       ( s5_axi_rresp       ),
2122 
        .s_axi_rlast       ( s5_axi_rlast       ),
2123 
        .s_axi_rvalid      ( s5_axi_rvalid      ),
2124 
        .s_axi_rready      ( s5_axi_rready      ),
2125 
        .mcb_cmd_clk       ( p5_cmd_clk_i       ),
2126 
        .mcb_cmd_en        ( p5_cmd_en_i        ),
2127 
        .mcb_cmd_instr     ( p5_cmd_instr_i     ),
2128 
        .mcb_cmd_bl        ( p5_cmd_bl_i        ),
2129 
        .mcb_cmd_byte_addr ( p5_cmd_byte_addr_i ),
2130 
        .mcb_cmd_empty     ( p5_cmd_empty_i     ),
2131 
        .mcb_cmd_full      ( p5_cmd_full_i      ),
2132 
        .mcb_wr_clk        ( p5_wr_clk_i        ),
2133 
        .mcb_wr_en         ( p5_wr_en_i         ),
2134 
        .mcb_wr_mask       ( p5_wr_mask_i       ),
2135 
        .mcb_wr_data       ( p5_wr_data_i       ),
2136 
        .mcb_wr_full       ( p5_wr_full_i       ),
2137 
        .mcb_wr_empty      ( p5_wr_empty_i      ),
2138 
        .mcb_wr_count      ( p5_wr_count_i      ),
2139 
        .mcb_wr_underrun   ( p5_wr_underrun_i   ),
2140 
        .mcb_wr_error      ( p5_wr_error_i      ),
2141 
        .mcb_rd_clk        ( p5_rd_clk_i        ),
2142 
        .mcb_rd_en         ( p5_rd_en_i         ),
2143 
        .mcb_rd_data       ( p5_rd_data_i       ),
2144 
        .mcb_rd_full       ( p5_rd_full_i       ),
2145 
        .mcb_rd_empty      ( p5_rd_empty_i      ),
2146 
        .mcb_rd_count      ( p5_rd_count_i      ),
2147 
        .mcb_rd_overflow   ( p5_rd_overflow_i   ),
2148 
        .mcb_rd_error      ( p5_rd_error_i      ),
2149 
        .mcb_calib_done    ( calib_done_synch   )
2150 
        );
2151 
    end
2152 
  endgenerate
2153 
 
2154 
endmodule
2155 
 

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.