Subversion Repositories openrisc

/* atlys-or1ksim.cfg -- Simulator configuration script file for Atlys board.

   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org

   Copyright (C) 2010, Embecosm Limited

   Contributor Jeremy Bennett 

   This file is part of OpenRISC 1000 Architectural Simulator.

   This program is free software; you can redistribute it and/or modify it

   under the terms of the GNU General Public License as published by the Free

   Software Foundation; either version 3 of the License, or (at your option)

   any later version.

   This program is distributed in the hope that it will be useful, but WITHOUT

   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

   more details.

   You should have received a copy of the GNU General Public License along

   with this program.  If not, see . */

/* -------------------------------------------------------------------------- */

/* The Ork1sim has various parameters, that can be set in configuration files

   like this one. The user can specify a configuration file at startup with

   the -f  option.

   The user guide (see the 'doc' directory) gives full details on

   configuration files. This is a reference configuration, which may be used

   as a starting point for customization.

   A number of peripherals are mapped at standard addresses (above 0x80000000)

   in the Verilog RTL of ORPSoC standard sitribution. The same values should

   be used in Or1ksim section definitions to match the behavior of the Verilog

      0x90000000 UART

      0x91000000 GPIO

      0x92000000 Ethernet

                                                                              */

/* -------------------------------------------------------------------------- */

/* Simulator section

   verbose               = 0|1

   debug                 = 0-9

   profile               = 0|1

   prof_file             = "" (default: "sim.profile")

   mprofile              = 0|1

   mprof_file            = "" (default: "sim.mprofile")

   history               = 0|1

   exe_log               = 0|1

   exe_log_type          = hardware|simple|software|default

   exe_log_start         =  (default: 0)

   exe_log_end           =  (default: never end)

   exe_log_marker        =  (default: no markers)

   exe_log_file          = "" (default: "executed.log")

   exe_bin_insn_log      = 0|1

   exe_bin_insn_log_file = "" (default: "exe-insn.bin")

   clkcycle              = [ps|ns|us|ms]

*/

section sim

  clkcycle = 20ns

end

/* CPU section

   ver         =  (default: 0)

   cfg         =  (default: 0)

   rev         =  (default: 0)

   upr         =  (see user manual for default settings)

   cfgr        =  (default: 0x00000020)

   sr          =  (default: 0x00008001)

   superscalar = 0|1

   hazards     = 0|1

   dependstats = 0|1

   sbuf_len    =  (default: 0)

   hardfloat   = 0|1

*/

section cpu

  ver = 0x12

  cfg = 0x00

  rev = 0x0001

end

/* Memory section

   type        = unknown|random|unknown|pattern

   random_seed =  (default: -1)

   pattern     =  (default: 0)

   baseaddr    =  (default: 0)

   size        =  (default: 1024)

   name        = "" (default: "anonymous memory block")

   ce          =  (default: -1)

   mc          =  (default: 0)

   delayr      =  (default: 1)

   delayw      =  (default: 1)

   log         = "" (default: NULL)

*/

section memory

  name        = "RAM"

  type        = unknown

  baseaddr    = 0x00000000

  size        = 0x08000000

  delayr      = 1

  delayw      = 1

end

/* Data MMU section

   enabled   = 0|1

   nsets     =  (default: 1)

   nways     =  (default: 1)

   pagesize  =  (default: 8192)

   entrysize =  (default: 1)

   ustates   =  (default: 1)

   hitdelay  =  (default: 1)

   missdelay =  (default: 1)

*/

section dmmu

  enabled   = 1

  nsets     = 64

  nways     = 1

  pagesize  = 8192

  hitdelay  = 0

  missdelay = 0

end

/* Instruction MMU section

   enabled   = 0|1

   nsets     =  (default: 1)

   nways     =  (default: 1)

   pagesize  =  (default: 8192)

   entrysize =  (default: 1)

   ustates   =  (default: 1)

   hitdelay  =  (default: 1)

   missdelay =  (default: 1)

*/

section immu

  enabled   = 1

  nsets     = 64

  nways     = 1

  pagesize  = 8192

  hitdelay  = 0

  missdelay = 0

end

/* Data cache section

   enabled         = 0|1

   nsets           =  (default: 1)

   nways           =  (default: 1)

   blocksize       =  (default: 16)

   ustates         =  (default: 2)

   load_hitdelay   =  (default: 2)

   load_missdelay  =  (default: 2)

   store_hitdelay  =  (default: 0)

   store_missdelay =  (default: 0)

*/

section dc

  enabled         = 1

  nsets           = 32768

  nways           = 1

  blocksize       = 32

  load_hitdelay   = 0

  load_missdelay  = 0

  store_hitdelay  = 0

  store_missdelay = 0

end

/* Instruction cache section

   enabled    = 0|1

   nsets      =  (default: 1)

   nways      =  (default: 1)

   blocksize  =  (default: 16)

   ustates    =  (default: 2)

   hitdelay   =  (default: 1)

   missdelay  =  (default: 1)

*/

section ic

  enabled   = 1

  nsets     = 32768

  nways     = 1

  blocksize = 32

  hitdelay  = 0

  missdelay = 0

end

/* Programmable interrupt controller section

  enabled      = 0|1

  edge_trigger = 0|1 (default: 1)

*/

section pic

  enabled = 1

end

/* Power management section

   enabled = 0|1

*/

section pm

  enabled = 0

end

/* Debug unit section

   enabled     = 0|1

   rsp_enabled = 0|1

   rsp_port    =  (default: 51000)

   vapi_id     =  (default: 0)

*/

section debug

  enabled = 0

end

/* UART section

   enabled  = 0|1

   baseaddr =  (default: 0)

   channel  = "value>" (default: "xterm:")

   irq      =  (default: 0)

   16550    = 0|1

   jitter   =  (default: 0)

   vapi_id  =  (default: 0)

*/

section uart

  enabled  = 1

  baseaddr = 0x90000000

  irq      = 2

  16550    = 1

end

/* Ethernet section

   enabled    = 0|1

   baseaddr   =  (default: 0)

   dma        =  (default: 0)

   irq        =  (default: 0)

   rtx_type   = 0|1

   rx_channel =  (default: 0)

   tx_channel =  (default: 0)

   rxfile     = "" (default: "eth_rx")

   txfile     = "" (default: "eth_rx")

   sockif     = "" (default: "or1ksim_eth")

   vapi_id    =  (default: 0)

*/

section ethernet

  enabled  = 1

  baseaddr = 0x92000000

  irq      = 4

  rtx_type = "tap"

  tap_dev = "tap0"

  dummy_crc = 1

end