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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [sw/] [Makefile.inc] - Blame information for rev 628

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Line No. Rev Author Line
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# Expecting BOARD_SW_ROOT already set to indicate how far below directory we're
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# in the board's software root path is.
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# Root from the board's sw/ path
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PROJ_ROOT=../../../..
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# Figure out actual path the common software directory
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SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw
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# Set the BOARD_PATH to point to the root of this board build
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BOARD=xilinx/atlys
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# Set RTL_VERILOG_INCLUDE_DIR so software
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RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include
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# Set the processor capability flags
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MARCH_FLAGS =-mhard-mul -mhard-div -mhard-float
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#MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float
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export MARCH_FLAGS
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# Finally include the main software include file
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include $(SW_ROOT)/Makefile.inc

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