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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [syn/] [xst/] [coregen/] [coregen.cgp] - Blame information for rev 634

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SET designentry = VHDL
SET BusFormat = BusFormatAngleBracketNotRipped
SET devicefamily = spartan6
SET device = xc6slx45
SET package = csg324
SET speedgrade = -2
SET FlowVendor = Foundation_ISE
SET VerilogSim = True
SET VHDLSim = True

Line No.	Rev	Author	Line
1	634	stekern	`SET designentry = VHDL`
2			`SET BusFormat = BusFormatAngleBracketNotRipped`
3			`SET devicefamily = spartan6`
4			`SET device = xc6slx45`
5			`SET package = csg324`
6			`SET speedgrade = -2`
7			`SET FlowVendor = Foundation_ISE`
8			`SET VerilogSim = True`
9			`SET VHDLSim = True`

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [syn/] [xst/] [coregen/] [coregen.cgp] - Blame information for rev 634