| 1 |
542 |
julius |
# Makefile fragment with some variables global to this board board
|
| 2 |
|
|
# Expects BOARD_ROOT to be set
|
| 3 |
|
|
|
| 4 |
|
|
FPGA_VENDOR=xilinx
|
| 5 |
|
|
BOARD_NAME=ml501
|
| 6 |
|
|
BOARD=$(FPGA_VENDOR)/$(BOARD_NAME)
|
| 7 |
|
|
DESIGN_NAME=orpsoc
|
| 8 |
|
|
|
| 9 |
|
|
# Path down to root of project
|
| 10 |
|
|
PROJECT_ROOT=$(BOARD_ROOT)/../../..
|
| 11 |
|
|
|
| 12 |
|
|
SYNTHESIS_TOOL=xst
|
| 13 |
|
|
|
| 14 |
|
|
export BOARD
|
| 15 |
|
|
|
| 16 |
|
|
include $(PROJECT_ROOT)/scripts/make/Makefile-misc.inc
|
| 17 |
|
|
include $(PROJECT_ROOT)/scripts/make/Makefile-board-paths.inc
|
| 18 |
|
|
include $(PROJECT_ROOT)/scripts/make/Makefile-board-tops.inc
|
| 19 |
|
|
include $(PROJECT_ROOT)/scripts/make/Makefile-board-definesparse.inc
|
| 20 |
|
|
|
| 21 |
|
|
# Check that the XILINX_PATH variable is set
|
| 22 |
|
|
ifeq ($(XILINX_PATH),)
|
| 23 |
|
|
$(error XILINX_PATH environment variable not set. Set it and rerun)
|
| 24 |
|
|
endif
|
| 25 |
|
|
XILINX_SETTINGS_SCRIPT=$(XILINX_PATH)/settings32.sh
|
| 26 |
|
|
XILINX_SETTINGS_SCRIPT_EXISTS=$(shell if [ -e $(XILINX_SETTINGS_SCRIPT) ]; then echo 1; else echo 0; fi)
|
| 27 |
|
|
ifeq ($(XILINX_SETTINGS_SCRIPT_EXISTS),0)
|
| 28 |
|
|
$(error XILINX_PATH variable not set correctly. Cannot find $$XILINX_PATH/settings32.sh)
|
| 29 |
|
|
endif
|
| 30 |
|
|
|
| 31 |
|
|
# Backend directories
|
| 32 |
|
|
# This one is the board build's backend dir.
|
| 33 |
|
|
BOARD_BACKEND_DIR=$(BOARD_ROOT)/backend
|
| 34 |
|
|
BOARD_BACKEND_VERILOG_DIR=$(BOARD_BACKEND_DIR)/rtl/verilog
|
| 35 |
|
|
BOARD_BACKEND_BIN_DIR=$(BOARD_BACKEND_DIR)/bin
|
| 36 |
|
|
# Technology backend (vendor-specific)
|
| 37 |
|
|
TECHNOLOGY_BACKEND_DIR=$(BOARD_ROOT)/../backend
|
| 38 |
|
|
# This path is for the technology library
|
| 39 |
|
|
TECHNOLOGY_LIBRARY_VERILOG_DIR=$(XILINX_PATH)/verilog
|
| 40 |
|
|
|
| 41 |
|
|
# Bootrom setup
|
| 42 |
|
|
# BootROM code, which generates a verilog array select values
|
| 43 |
|
|
BOOTROM_FILE=bootrom.v
|
| 44 |
|
|
BOOTROM_SW_DIR=$(BOARD_SW_DIR)/bootrom
|
| 45 |
|
|
BOOTROM_SRC=$(shell ls $(BOOTROM_SW_DIR)/* | grep -v $(BOOTROM_FILE))
|
| 46 |
|
|
BOOTROM_VERILOG=$(BOOTROM_SW_DIR)/$(BOOTROM_FILE)
|
| 47 |
|
|
|
| 48 |
|
|
bootrom: $(BOOTROM_VERILOG)
|
| 49 |
|
|
|
| 50 |
|
|
$(BOOTROM_VERILOG): $(BOOTROM_SRC)
|
| 51 |
|
|
$(Q)echo; echo "\t### Generating bootup ROM ###"; echo
|
| 52 |
|
|
$(Q)$(MAKE) -C $(BOOTROM_SW_DIR) $(BOOTROM_FILE)
|
| 53 |
|
|
|
| 54 |
|
|
clean-bootrom:
|
| 55 |
|
|
$(Q)echo; echo "\t### Cleaning bootup ROM ###"; echo
|
| 56 |
|
|
$(Q)$(MAKE) -C $(BOOTROM_SW_DIR) clean
|
| 57 |
|
|
|
| 58 |
|
|
include $(PROJECT_ROOT)/scripts/make/Makefile-board-rtlmodules.inc
|
| 59 |
|
|
|
| 60 |
|
|
# "Backend" source file stuff (PLL, RAM macro models.)
|
| 61 |
|
|
BOARD_BACKEND_VERILOG_SRC=$(shell ls $(BOARD_BACKEND_VERILOG_DIR)/*.v )
|
| 62 |
|
|
|
| 63 |
|
|
# Backend tool path
|
| 64 |
|
|
|
| 65 |
|
|
# BACKEND_TECHNOLOGY_VERILOG_SRC should be set if we need to compile specific
|
| 66 |
|
|
# libraries, as in the Actel and Altera case, and left empty for Xilinx who
|
| 67 |
|
|
# allow us to simply pass the path with the -y option because they have each
|
| 68 |
|
|
# bit of the tech library in individual files, and in which case this variable
|
| 69 |
|
|
# should be left unset.
|
| 70 |
|
|
|
| 71 |
|
|
# Keep this variable empty
|
| 72 |
|
|
BACKEND_TECHNOLOGY_VERILOG_SRC=
|
