OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [Makefile.inc] - Blame information for rev 856

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 542 julius
# Makefile fragment with some variables global to this board board
2
# Expects BOARD_ROOT to be set
3
 
4
FPGA_VENDOR=xilinx
5
BOARD_NAME=ml501
6
BOARD=$(FPGA_VENDOR)/$(BOARD_NAME)
7
DESIGN_NAME=orpsoc
8
 
9
# Path down to root of project
10
PROJECT_ROOT=$(BOARD_ROOT)/../../..
11
 
12
SYNTHESIS_TOOL=xst
13
 
14
export BOARD
15
 
16
include $(PROJECT_ROOT)/scripts/make/Makefile-misc.inc
17
include $(PROJECT_ROOT)/scripts/make/Makefile-board-paths.inc
18
include $(PROJECT_ROOT)/scripts/make/Makefile-board-tops.inc
19
include $(PROJECT_ROOT)/scripts/make/Makefile-board-definesparse.inc
20
 
21 638 stekern
# Check that the Xilinx scripts have been sourced
22
ifndef XILINX
23
$(error The XILINX environment variable was not set, \
24
please run: 'source /path/to/xilinx_ise/settings{32|64}.sh')
25 542 julius
endif
26
 
27
# Backend directories
28
# This one is the board build's backend dir.
29
BOARD_BACKEND_DIR=$(BOARD_ROOT)/backend
30
BOARD_BACKEND_VERILOG_DIR=$(BOARD_BACKEND_DIR)/rtl/verilog
31
BOARD_BACKEND_BIN_DIR=$(BOARD_BACKEND_DIR)/bin
32
# Technology backend (vendor-specific)
33
TECHNOLOGY_BACKEND_DIR=$(BOARD_ROOT)/../backend
34
# This path is for the technology library
35 638 stekern
TECHNOLOGY_LIBRARY_VERILOG_DIR=$(XILINX)/verilog
36 542 julius
 
37
# Bootrom setup
38
# BootROM code, which generates a verilog array select values
39
BOOTROM_FILE=bootrom.v
40
BOOTROM_SW_DIR=$(BOARD_SW_DIR)/bootrom
41
BOOTROM_SRC=$(shell ls $(BOOTROM_SW_DIR)/* | grep -v $(BOOTROM_FILE))
42
BOOTROM_VERILOG=$(BOOTROM_SW_DIR)/$(BOOTROM_FILE)
43
 
44
bootrom: $(BOOTROM_VERILOG)
45
 
46
$(BOOTROM_VERILOG): $(BOOTROM_SRC)
47
        $(Q)echo; echo "\t### Generating bootup ROM ###"; echo
48
        $(Q)$(MAKE) -C $(BOOTROM_SW_DIR) $(BOOTROM_FILE)
49
 
50
clean-bootrom:
51
        $(Q)echo; echo "\t### Cleaning bootup ROM ###"; echo
52
        $(Q)$(MAKE) -C $(BOOTROM_SW_DIR) clean
53
 
54
include $(PROJECT_ROOT)/scripts/make/Makefile-board-rtlmodules.inc
55
 
56
# "Backend" source file stuff (PLL, RAM macro models.)
57
BOARD_BACKEND_VERILOG_SRC=$(shell ls $(BOARD_BACKEND_VERILOG_DIR)/*.v )
58
 
59
# Backend tool path
60
 
61
# BACKEND_TECHNOLOGY_VERILOG_SRC should be set if we need to compile specific
62
# libraries, as in the Actel and Altera case, and left empty for Xilinx who
63
# allow us to simply pass the path with the -y option because they have each
64
# bit of the tech library in individual files, and in which case this variable
65
# should be left unset.
66
 
67
# Keep this variable empty
68
BACKEND_TECHNOLOGY_VERILOG_SRC=

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.