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//************************************************************************
//************************************************************************
//** This model is the property of Cypress Semiconductor Corp and is    **
//** protected by the US copyright laws, any unauthorized copying and   **
//** distribution is prohibited. Cypress reserves the right to change   ** 
//** any of the functional specifications without any prior notice.     ** 
//** Cypress is not liable for any damages which may result from the    **
//** use of this functional model.                                      **
//**                                                                    **
//** File Name  :   CY7C1354B                                   **
//**                                                                    **
//** Revision   :   1.1 - 01/30/2004                                    **
//**                                                                    **
//** The timings are to be selected by the user depending upon the      **
//** frequency of operation from the datasheet.                         **
//**                                                                    **
//** Model      :   CY7C1354B - 256K x 36 NoBL Pipelined SRAM           **
//** Queries    :   MPD Applications                                    **
//**                e-mail: mpd_apps@cypress.com                        **              
//************************************************************************
//************************************************************************
 
`timescale  1ns /  10ps
 
//      NOTE :  Any setup/hold errors will force input signal to x state
//              or if results indeterminant (write addr) core is reset x
 
// define fixed values
 
`define wordsize (36 -1)                //
`define no_words (262144  -1)           // 256K x 36 RAM
 
module cy7c1354 ( d, clk, a, bws, we_b, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode);
 
inout   [`wordsize:0]    d;
input                   clk,            // clock input (R)
                        we_b,           // byte write enable(L)
                        adv_lb,         // burst(H)/load(L) address
                        ce1b,           // chip enable(L)
                        ce2,            // chip enable(H)
                        ce3b,           // chip enable(L)
                        oeb,            // async output enable(L)(read)
                        cenb,           // clock enable(L)
                        mode;           // interleave(H)/linear(L) burst
input   [3:0]            bws;            // byte write select(L)
input   [18:0]           a;              // address bus
 
//      ***     NOTE DEVICE OPERATES #0.01 AFTER CLOCK          ***
//      *** THEREFORE DELAYS HAVE TO TAKE THIS INTO ACCOUNT     ***
 
//**********************************************************************
//  This model is configured for 166 MHz Operation (CY7C1354-166). 
//**********************************************************************
  `define teohz #3.5
  `define teolz #0
  `define tchz #3.5
  `define tclz #1.5
 
  `define tco   #3.5
  `define tdoh  #1.5
 
  `define tas 1.5
  `define tah 0.5
 
/**********************************************************************
//  Timings for 225MHz
//**********************************************************************
  `define teohz #2.8
  `define teolz #0
  `define tchz #2.8
  `define tclz #1.5
 
  `define tco   #2.8
  `define tdoh  #1.5
 
  `define tas 1.5
  `define tah 0.5
 
//***********************************************************************
//  Timings for 200MHz
//**********************************************************************
  `define teohz #3.2
  `define teolz #0
  `define tchz #3.2
  `define tclz #1.5
 
  `define tco   #3.2
  `define tdoh  #1.5
 
  `define tas 1.5
  `define tah 0.5
***********************************************************************/
 
reg             notifier;       // error support reg's
reg             noti1_0;
reg             noti1_1;
reg             noti1_2;
reg             noti1_3;
reg             noti1_4;
reg             noti1_5;
reg             noti1_6;
reg             noti2;
 
 
wire chipen;            // combined chip enable (high for an active chip)
 
reg  chipen_d;          // _d = delayed
reg  chipen_o;          // _o = operational = delayed sig or _d sig
 
wire writestate;        // holds 1 if any of writebus is low
reg  writestate_d;
reg  writestate_o;
 
wire loadcyc;           // holds 1 for load cycles (setup and hold checks)
wire writecyc;          // holds 1 for write cycles (setup and hold checks)
wire [3:0] bws;          // holds the bws values
 
wire [3:0] writebusb;    // holds the "internal" bws bus based on we_b
reg  [3:0] writebusb_d;
reg  [3:0] writebusb_o;
 
wire [2:0] operation;    // holds chipen, adv_ld and writestate
reg  [2:0] operation_d;
reg  [2:0] operation_o;
 
wire [17:0] a;           // address input bus
reg  [17:0] a_d;
reg  [17:0] a_o;
 
reg  [`wordsize:0] do;           // data  output reg
reg  [`wordsize:0] di;           // data   input bus
reg  [`wordsize:0] dd;           // data delayed bus
 
wire tristate;          // tristate output (on a bytewise basis) when asserted
reg  cetri;             // register set by chip disable which sets the tristate 
reg  oetri;             // register set by oe which sets the tristate
reg  enable;            // register to make the ram enabled when equal to 1
reg  [17:0] addreg;      // register to hold the input address
reg  [`wordsize:0] pipereg;      // register for the output data
 
reg  [`wordsize:0] mem [0:`no_words];     // RAM array
 
reg [`wordsize:0] writeword;     // temporary holding register for the write data
reg  burstinit;         // register to hold a[0] for burst type
reg  [18:0] i;   // temporary register used to write to all mem locs.
reg  writetri;          // tristate
reg  lw, bw;            // pipelined write functions
reg  we_bl;
 
 
wire [`wordsize:0]  d =  !tristate ?  do[`wordsize:0] : 36'bz ;   //  data bus
 
assign chipen           = (adv_lb == 1 ) ? chipen_d :
                                ~ce1b & ce2 & ~ce3b ;
 
assign writestate       = ~& writebusb;
 
assign operation        = {chipen, adv_lb, writestate};
 
assign writebusb[3:0]    = (  we_b  ==0 & adv_lb ==0) ? bws[3:0]:
                          (  we_b  ==1 & adv_lb ==0) ? 4'b1111 :
                          (  we_bl ==0 & adv_lb ==1) ? bws[3:0]:
                          (  we_bl ==1 & adv_lb ==1) ? 4'b1111 :
                                                       4'bxxxx ;
 
assign loadcyc          = chipen & !cenb;
 
assign writecyc         = writestate_d & enable & ~cenb & chipen; // check
 
assign tristate         = cetri | writetri | oetri;
 
pullup    (mode);
 
// formers for notices/errors etc
//
//$display("NOTICE      : xxx :");
//$display("WARNING     : xxx :");
//$display("ERROR   *** : xxx :");
 
 
// initialize the output to be tri-state, ram to be disabled
 
initial
        begin
// signals
 
          writetri      = 0;
          cetri         = 1;
          enable        = 0;
          lw            = 0;
          bw            = 0;
 
// error signals 
 
          notifier      = 0;
          noti1_0       = 0;
          noti1_1       = 0;
          noti1_2       = 0;
          noti1_3       = 0;
          noti1_4       = 0;
          noti1_5       = 0;
          noti1_6       = 0;
          noti2         = 0;
 
end
 
 
 
// asynchronous OE
 
always @(oeb)
begin
  if (oeb == 1)
    oetri <= `teohz 1;
  else
    oetri <= `teolz 0;
end
 
//      ***     SETUP / HOLD VIOLATIONS         ***
 
always @(noti2)
begin
$display("NOTICE      : 020 : Data bus    corruption");
    force d =36'bx;
    #1;
    release d;
end
 
always @(noti1_0)
begin
$display("NOTICE      : 010 : Byte write  corruption");
    force bws = 4'bx;
    #1;
    release bws;
end
 
always @(noti1_1)
begin
$display("NOTICE      : 011 : Byte enable corruption");
    force we_b = 1'bx;
    #1;
    release we_b;
end
 
always @(noti1_2)
begin
$display("NOTICE      : 012 : CE1B       corruption");
    force ce1b =1'bx;
    #1;
    release ce1b;
end
 
always @(noti1_3)
begin
$display("NOTICE      : 013 : CE2       corruption");
    force ce2 =1'bx;
    #1;
   release ce2;
end
 
always @(noti1_4)
begin
$display("NOTICE      : 014 : CE3B      corruption");
    force ce3b =1'bx;
    #1;
    release ce3b;
end
 
always @(noti1_5)
begin
$display("NOTICE      : 015 : CENB      corruption");
    force cenb =1'bx;
    #1;
    release cenb;
end
 
always @(noti1_6)
begin
$display("NOTICE      : 016 : ADV_LB   corruption");
    force adv_lb = 1'bx;
    #1;
    release adv_lb;
end
 
// synchronous functions from clk edge
 
always @(posedge clk)
if (!cenb)
begin
#0.01;
  // latch conditions on adv_lb
 
  if (adv_lb)
   we_bl                <=      we_bl;
  else
   we_bl                <=      we_b;
 
  chipen_d              <=      chipen;
 
 
      chipen_o          <=      chipen;
      writestate_o      <=      writestate;
      writestate_d      <=      writestate_o;
      writebusb_o       <=      writebusb;
      writebusb_d       <=      writebusb_o;
      operation_o       <=      operation;
      a_o               <=      a;
      a_d               <=      a_o;
      di                 =      d;
 
  // execute previously pipelined fns
 
  if (lw) begin
                loadwrite;
                lw =0;
          end
 
  if (bw) begin
                burstwrite;
                bw =0;
          end
 
  // decode input/piplined state
 
    casex (operation_o)
    3'b0??      : turnoff;
    3'b101      : setlw;
    3'b111      : setbw;
    3'b100      : loadread;
    3'b110      : burstread;
    default : unknown; // output unknown values and display an error message
  endcase
 
   do <= `tco  pipereg;
 
end
 
//                      ***     task section    ***
 
task read;
begin
  if (enable) cetri <= `tclz 0;
     do <= `tdoh 36'hx;
     writetri <= `tchz 0;
  pipereg = mem[addreg];
end
endtask
 
task write;
begin
  if (enable) cetri <= `tclz 0;
  writeword = mem[addreg];  // set up a word to hold the data for the current location
  /* overwrite the current word for the bytes being written to */
  if (!writebusb_d[3]) writeword[35:27] = di[35:27];
  if (!writebusb_d[2]) writeword[26:18] = di[26:18];
  if (!writebusb_d[1]) writeword[17:9]  = di[17:9];
  if (!writebusb_d[0]) writeword[8:0]   = di[8:0];
  writeword = writeword &  writeword; //convert z to x states
  mem[addreg] = writeword; // store the new word into the memory location
  //writetri <= `tchz 1;    // tristate the outputs
end
endtask
 
task setlw;
begin
    lw =1;
    writetri <= `tchz 1;    // tristate the outputs
end
endtask
 
task setbw;
begin
    bw =1;
    writetri <= `tchz 1;    // tristate the outputs
end
endtask
 
task loadread;
begin
  burstinit = a_o[0];
  addreg = a_o;
  enable = 1;
  read;
end
endtask
 
task loadwrite;
begin
  burstinit = a_d[0];
  addreg = a_d;
  enable = 1;
  write;
end
endtask
 
task burstread;
begin
  burst;
  read;
end
endtask
 
task burstwrite;
begin
  burst;
  write;
end
endtask
 
task unknown;
begin
  do = 36'bx;
  // $display ("Unknown function:  Operation = %b\n", operation);
end
endtask
 
task turnoff;
begin
  enable = 0;
  cetri <= `tchz 1;
  pipereg = 36'h0;
end
endtask
 
task burst;
begin
  if (burstinit == 0 || mode == 0)
  begin
    case (addreg[1:0])
      2'b00:   addreg[1:0] = 2'b01;
      2'b01:   addreg[1:0] = 2'b10;
      2'b10:   addreg[1:0] = 2'b11;
      2'b11:   addreg[1:0] = 2'b00;
      default: addreg[1:0] = 2'bxx;
    endcase
  end
  else
  begin
    case (addreg[1:0])
      2'b00:   addreg[1:0] = 2'b11;
      2'b01:   addreg[1:0] = 2'b00;
      2'b10:   addreg[1:0] = 2'b01;
      2'b11:   addreg[1:0] = 2'b10;
      default: addreg[1:0] = 2'bxx;
    endcase
  end
end
endtask
 
// IO checks
 
specify
// specify the setup and hold checks
 
// notifier will wipe memory as result is indeterminent
 
$setuphold(posedge clk &&& loadcyc, a, `tas, `tah, notifier);
 
// noti1 should make ip = 'bx;
 
$setuphold(posedge clk, bws,  `tas, `tah, noti1_0);
 
$setuphold(posedge clk, we_b, `tas, `tah, noti1_1);
$setuphold(posedge clk, ce1b, `tas, `tah, noti1_2);
$setuphold(posedge clk,  ce2, `tas, `tah, noti1_3);
$setuphold(posedge clk, ce3b, `tas, `tah, noti1_4);
 
// noti2 should make d = 36'hxxxxxxxxx;
 
$setuphold(posedge clk &&& writecyc, d, `tas, `tah, noti2);
//$setuphold(posedge clk &&& WriteTimingCheck , d, `tas, `tah, noti2);
 
// add extra tests here.
 
$setuphold(posedge clk,   cenb, `tas, `tah, noti1_5);
$setuphold(posedge clk, adv_lb, `tas, `tah, noti1_6);
 
endspecify
 
endmodule
 
 

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [cy7c1354.v] - Blame information for rev 360

Line No.	Rev	Author	Line
1	67	julius	`//************************************************************************`
2			`//************************************************************************`
3			`// This model is the property of Cypress Semiconductor Corp and is `
4			`// protected by the US copyright laws, any unauthorized copying and `
5			`// distribution is prohibited. Cypress reserves the right to change `
6			`// any of the functional specifications without any prior notice. `
7			`// Cypress is not liable for any damages which may result from the `
8			`// use of this functional model. `
9			`// `
10			`// File Name : CY7C1354B `
11			`// `
12			`// Revision : 1.1 - 01/30/2004 `
13			`// `
14			`// The timings are to be selected by the user depending upon the `
15			`// frequency of operation from the datasheet. `
16			`// `
17			`// Model : CY7C1354B - 256K x 36 NoBL Pipelined SRAM `
18			`// Queries : MPD Applications `
19			`// e-mail: mpd_apps@cypress.com `
20			`//************************************************************************`
21			`//************************************************************************`
22
23			`timescale 1ns / 10ps
24
25			`// NOTE : Any setup/hold errors will force input signal to x state`
26			`// or if results indeterminant (write addr) core is reset x`
27
28			`// define fixed values`
29
30			`define wordsize (36 -1) //
31			`define no_words (262144 -1) // 256K x 36 RAM
32
33			`module cy7c1354 ( d, clk, a, bws, we_b, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode);`
34
35			inout [`wordsize:0] d;
36			`input clk, // clock input (R)`
37			`we_b, // byte write enable(L)`
38			`adv_lb, // burst(H)/load(L) address`
39			`ce1b, // chip enable(L)`
40			`ce2, // chip enable(H)`
41			`ce3b, // chip enable(L)`
42			`oeb, // async output enable(L)(read)`
43			`cenb, // clock enable(L)`
44			`mode; // interleave(H)/linear(L) burst`
45			`input [3:0] bws; // byte write select(L)`
46			`input [18:0] a; // address bus`
47
48			`// * NOTE DEVICE OPERATES #0.01 AFTER CLOCK *`
49			`// * THEREFORE DELAYS HAVE TO TAKE THIS INTO ACCOUNT *`
50
51			`//**********************************************************************`
52			`// This model is configured for 166 MHz Operation (CY7C1354-166).`
53			`//**********************************************************************`
54			`define teohz #3.5
55			`define teolz #0
56			`define tchz #3.5
57			`define tclz #1.5
58
59			`define tco #3.5
60			`define tdoh #1.5
61
62			`define tas 1.5
63			`define tah 0.5
64
65			`/**********************************************************************`
66			`// Timings for 225MHz`
67			`//**********************************************************************`
68			`define teohz #2.8
69			`define teolz #0
70			`define tchz #2.8
71			`define tclz #1.5
72
73			`define tco #2.8
74			`define tdoh #1.5
75
76			`define tas 1.5
77			`define tah 0.5
78
79			`//***********************************************************************`
80			`// Timings for 200MHz`
81			`//**********************************************************************`
82			`define teohz #3.2
83			`define teolz #0
84			`define tchz #3.2
85			`define tclz #1.5
86
87			`define tco #3.2
88			`define tdoh #1.5
89
90			`define tas 1.5
91			`define tah 0.5
92			`***********************************************************************/`
93
94			`reg notifier; // error support reg's`
95			`reg noti1_0;`
96			`reg noti1_1;`
97			`reg noti1_2;`
98			`reg noti1_3;`
99			`reg noti1_4;`
100			`reg noti1_5;`
101			`reg noti1_6;`
102			`reg noti2;`
103
104
105			`wire chipen; // combined chip enable (high for an active chip)`
106
107			`reg chipen_d; // _d = delayed`
108			`reg chipen_o; // _o = operational = delayed sig or _d sig`
109
110			`wire writestate; // holds 1 if any of writebus is low`
111			`reg writestate_d;`
112			`reg writestate_o;`
113
114			`wire loadcyc; // holds 1 for load cycles (setup and hold checks)`
115			`wire writecyc; // holds 1 for write cycles (setup and hold checks)`
116			`wire [3:0] bws; // holds the bws values`
117
118			`wire [3:0] writebusb; // holds the "internal" bws bus based on we_b`
119			`reg [3:0] writebusb_d;`
120			`reg [3:0] writebusb_o;`
121
122			`wire [2:0] operation; // holds chipen, adv_ld and writestate`
123			`reg [2:0] operation_d;`
124			`reg [2:0] operation_o;`
125
126			`wire [17:0] a; // address input bus`
127			`reg [17:0] a_d;`
128			`reg [17:0] a_o;`
129
130			reg [`wordsize:0] do; // data output reg
131			reg [`wordsize:0] di; // data input bus
132			reg [`wordsize:0] dd; // data delayed bus
133
134			`wire tristate; // tristate output (on a bytewise basis) when asserted`
135			`reg cetri; // register set by chip disable which sets the tristate`
136			`reg oetri; // register set by oe which sets the tristate`
137			`reg enable; // register to make the ram enabled when equal to 1`
138			`reg [17:0] addreg; // register to hold the input address`
139			reg [`wordsize:0] pipereg; // register for the output data
140
141			reg [`wordsize:0] mem [0:`no_words]; // RAM array
142
143			reg [`wordsize:0] writeword; // temporary holding register for the write data
144			`reg burstinit; // register to hold a[0] for burst type`
145			`reg [18:0] i; // temporary register used to write to all mem locs.`
146			`reg writetri; // tristate`
147			`reg lw, bw; // pipelined write functions`
148			`reg we_bl;`
149
150
151			wire [`wordsize:0] d = !tristate ? do[`wordsize:0] : 36'bz ; // data bus
152
153			`assign chipen = (adv_lb == 1 ) ? chipen_d :`
154			`~ce1b & ce2 & ~ce3b ;`
155
156			`assign writestate = ~& writebusb;`
157
158			`assign operation = {chipen, adv_lb, writestate};`
159
160			`assign writebusb[3:0] = ( we_b ==0 & adv_lb ==0) ? bws[3:0]:`
161			`( we_b ==1 & adv_lb ==0) ? 4'b1111 :`
162			`( we_bl ==0 & adv_lb ==1) ? bws[3:0]:`
163			`( we_bl ==1 & adv_lb ==1) ? 4'b1111 :`
164			`4'bxxxx ;`
165
166			`assign loadcyc = chipen & !cenb;`
167
168			`assign writecyc = writestate_d & enable & ~cenb & chipen; // check`
169
170			`assign tristate = cetri \| writetri \| oetri;`
171
172			`pullup (mode);`
173
174			`// formers for notices/errors etc`
175			`//`
176			`//$display("NOTICE : xxx :");`
177			`//$display("WARNING : xxx :");`
178			`//$display("ERROR *** : xxx :");`
179
180
181			`// initialize the output to be tri-state, ram to be disabled`
182
183			`initial`
184			`begin`
185			`// signals`
186
187			`writetri = 0;`
188			`cetri = 1;`
189			`enable = 0;`
190			`lw = 0;`
191			`bw = 0;`
192
193			`// error signals`
194
195			`notifier = 0;`
196			`noti1_0 = 0;`
197			`noti1_1 = 0;`
198			`noti1_2 = 0;`
199			`noti1_3 = 0;`
200			`noti1_4 = 0;`
201			`noti1_5 = 0;`
202			`noti1_6 = 0;`
203			`noti2 = 0;`
204
205			`end`
206
207
208
209			`// asynchronous OE`
210
211			`always @(oeb)`
212			`begin`
213			`if (oeb == 1)`
214			oetri <= `teohz 1;
215			`else`
216			oetri <= `teolz 0;
217			`end`
218
219			`// * SETUP / HOLD VIOLATIONS *`
220
221			`always @(noti2)`
222			`begin`
223			`$display("NOTICE : 020 : Data bus corruption");`
224			`force d =36'bx;`
225			`#1;`
226			`release d;`
227			`end`
228
229			`always @(noti1_0)`
230			`begin`
231			`$display("NOTICE : 010 : Byte write corruption");`
232			`force bws = 4'bx;`
233			`#1;`
234			`release bws;`
235			`end`
236
237			`always @(noti1_1)`
238			`begin`
239			`$display("NOTICE : 011 : Byte enable corruption");`
240			`force we_b = 1'bx;`
241			`#1;`
242			`release we_b;`
243			`end`
244
245			`always @(noti1_2)`
246			`begin`
247			`$display("NOTICE : 012 : CE1B corruption");`
248			`force ce1b =1'bx;`
249			`#1;`
250			`release ce1b;`
251			`end`
252
253			`always @(noti1_3)`
254			`begin`
255			`$display("NOTICE : 013 : CE2 corruption");`
256			`force ce2 =1'bx;`
257			`#1;`
258			`release ce2;`
259			`end`
260
261			`always @(noti1_4)`
262			`begin`
263			`$display("NOTICE : 014 : CE3B corruption");`
264			`force ce3b =1'bx;`
265			`#1;`
266			`release ce3b;`
267			`end`
268
269			`always @(noti1_5)`
270			`begin`
271			`$display("NOTICE : 015 : CENB corruption");`
272			`force cenb =1'bx;`
273			`#1;`
274			`release cenb;`
275			`end`
276
277			`always @(noti1_6)`
278			`begin`
279			`$display("NOTICE : 016 : ADV_LB corruption");`
280			`force adv_lb = 1'bx;`
281			`#1;`
282			`release adv_lb;`
283			`end`
284
285			`// synchronous functions from clk edge`
286
287			`always @(posedge clk)`
288			`if (!cenb)`
289			`begin`
290			`#0.01;`
291			`// latch conditions on adv_lb`
292
293			`if (adv_lb)`
294			`we_bl <= we_bl;`
295			`else`
296			`we_bl <= we_b;`
297
298			`chipen_d <= chipen;`
299
300
301			`chipen_o <= chipen;`
302			`writestate_o <= writestate;`
303			`writestate_d <= writestate_o;`
304			`writebusb_o <= writebusb;`
305			`writebusb_d <= writebusb_o;`
306			`operation_o <= operation;`
307			`a_o <= a;`
308			`a_d <= a_o;`
309			`di = d;`
310
311			`// execute previously pipelined fns`
312
313			`if (lw) begin`
314			`loadwrite;`
315			`lw =0;`
316			`end`
317
318			`if (bw) begin`
319			`burstwrite;`
320			`bw =0;`
321			`end`
322
323			`// decode input/piplined state`
324
325			`casex (operation_o)`
326			`3'b0?? : turnoff;`
327			`3'b101 : setlw;`
328			`3'b111 : setbw;`
329			`3'b100 : loadread;`
330			`3'b110 : burstread;`
331			`default : unknown; // output unknown values and display an error message`
332			`endcase`
333
334			do <= `tco pipereg;
335
336			`end`
337
338			`// * task section *`
339
340			`task read;`
341			`begin`
342			if (enable) cetri <= `tclz 0;
343			do <= `tdoh 36'hx;
344			writetri <= `tchz 0;
345			`pipereg = mem[addreg];`
346			`end`
347			`endtask`
348
349			`task write;`
350			`begin`
351			if (enable) cetri <= `tclz 0;
352			`writeword = mem[addreg]; // set up a word to hold the data for the current location`
353			`/* overwrite the current word for the bytes being written to */`
354			`if (!writebusb_d[3]) writeword[35:27] = di[35:27];`
355			`if (!writebusb_d[2]) writeword[26:18] = di[26:18];`
356			`if (!writebusb_d[1]) writeword[17:9] = di[17:9];`
357			`if (!writebusb_d[0]) writeword[8:0] = di[8:0];`
358			`writeword = writeword & writeword; //convert z to x states`
359			`mem[addreg] = writeword; // store the new word into the memory location`
360			//writetri <= `tchz 1; // tristate the outputs
361			`end`
362			`endtask`
363
364			`task setlw;`
365			`begin`
366			`lw =1;`
367			writetri <= `tchz 1; // tristate the outputs
368			`end`
369			`endtask`
370
371			`task setbw;`
372			`begin`
373			`bw =1;`
374			writetri <= `tchz 1; // tristate the outputs
375			`end`
376			`endtask`
377
378			`task loadread;`
379			`begin`
380			`burstinit = a_o[0];`
381			`addreg = a_o;`
382			`enable = 1;`
383			`read;`
384			`end`
385			`endtask`
386
387			`task loadwrite;`
388			`begin`
389			`burstinit = a_d[0];`
390			`addreg = a_d;`
391			`enable = 1;`
392			`write;`
393			`end`
394			`endtask`
395
396			`task burstread;`
397			`begin`
398			`burst;`
399			`read;`
400			`end`
401			`endtask`
402
403			`task burstwrite;`
404			`begin`
405			`burst;`
406			`write;`
407			`end`
408			`endtask`
409
410			`task unknown;`
411			`begin`
412			`do = 36'bx;`
413			`// $display ("Unknown function: Operation = %b\n", operation);`
414			`end`
415			`endtask`
416
417			`task turnoff;`
418			`begin`
419			`enable = 0;`
420			cetri <= `tchz 1;
421			`pipereg = 36'h0;`
422			`end`
423			`endtask`
424
425			`task burst;`
426			`begin`
427			`if (burstinit == 0 \|\| mode == 0)`
428			`begin`
429			`case (addreg[1:0])`
430			`2'b00: addreg[1:0] = 2'b01;`
431			`2'b01: addreg[1:0] = 2'b10;`
432			`2'b10: addreg[1:0] = 2'b11;`
433			`2'b11: addreg[1:0] = 2'b00;`
434			`default: addreg[1:0] = 2'bxx;`
435			`endcase`
436			`end`
437			`else`
438			`begin`
439			`case (addreg[1:0])`
440			`2'b00: addreg[1:0] = 2'b11;`
441			`2'b01: addreg[1:0] = 2'b00;`
442			`2'b10: addreg[1:0] = 2'b01;`
443			`2'b11: addreg[1:0] = 2'b10;`
444			`default: addreg[1:0] = 2'bxx;`
445			`endcase`
446			`end`
447			`end`
448			`endtask`
449
450			`// IO checks`
451
452			`specify`
453			`// specify the setup and hold checks`
454
455			`// notifier will wipe memory as result is indeterminent`
456
457			$setuphold(posedge clk &&& loadcyc, a, `tas, `tah, notifier);
458
459			`// noti1 should make ip = 'bx;`
460
461			$setuphold(posedge clk, bws, `tas, `tah, noti1_0);
462
463			$setuphold(posedge clk, we_b, `tas, `tah, noti1_1);
464			$setuphold(posedge clk, ce1b, `tas, `tah, noti1_2);
465			$setuphold(posedge clk, ce2, `tas, `tah, noti1_3);
466			$setuphold(posedge clk, ce3b, `tas, `tah, noti1_4);
467
468			`// noti2 should make d = 36'hxxxxxxxxx;`
469
470			$setuphold(posedge clk &&& writecyc, d, `tas, `tah, noti2);
471			//$setuphold(posedge clk &&& WriteTimingCheck , d, `tas, `tah, noti2);
472
473			`// add extra tests here.`
474
475			$setuphold(posedge clk, cenb, `tas, `tah, noti1_5);
476			$setuphold(posedge clk, adv_lb, `tas, `tah, noti1_6);
477
478			`endspecify`
479
480			`endmodule`
481
482