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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [orpsoc_testbench.v] - Blame information for rev 856

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//////////////////////////////////////////////////////////////////////
///                                                               //// 
/// ORPSoC ML501 testbench                                        ////
///                                                               ////
/// Instantiate ORPSoC, monitors, provide stimulus                ////
///                                                               ////
/// Julius Baxter, julius@opencores.org                           ////
///                                                               ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "orpsoc-defines.v"
`include "orpsoc-testbench-defines.v"
`include "test-defines.v"
`include "timescale.v"
// Xilinx simulation:
`include "glbl.v"
 
module orpsoc_testbench;
 
   // Clock and reset signal registers
   reg clk = 0;
   reg rst_n = 1; // Active LOW
 
   always
     #((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
 
   wire clk_n, clk_p;
   assign clk_p = clk;
   assign clk_n = ~clk;
 
 
   // Reset, ACTIVE LOW
   initial
     begin
        #1;
        repeat (32) @(negedge clk)
          rst_n <= 1;
        repeat (32) @(negedge clk)
          rst_n <= 0;
        repeat (32) @(negedge clk)
          rst_n <= 1;
     end
 
   // Include design parameters file
`include "orpsoc-params.v"
 
   // Pullup bus for I2C
   tri1 i2c_scl, i2c_sda;
 
`ifdef JTAG_DEBUG
   wire tdo_pad_o;
   wire tck_pad_i;
   wire tms_pad_i;
   wire tdi_pad_i;
`endif
`ifdef UART0
   wire uart0_stx_pad_o;
   wire uart0_srx_pad_i;
`endif
`ifdef GPIO0
   wire [gpio0_io_width-1:0] gpio0_io;
`endif
`ifdef SPI0
   wire                      spi0_mosi_o;
   wire                      spi0_miso_i;
   wire                      spi0_sck_o;
   wire                      spi0_hold_n_o;
   wire                      spi0_w_n_o;
   wire [spi0_ss_width-1:0]  spi0_ss_o;
`endif
`ifdef ETH0
   wire                      mtx_clk_o;
   wire [3:0]                 ethphy_mii_tx_d;
   wire                      ethphy_mii_tx_en;
   wire                      ethphy_mii_tx_err;
   wire                      mrx_clk_o;
   wire [3:0]                 mrxd_o;
   wire                      mrxdv_o;
   wire                      mrxerr_o;
   wire                      mcoll_o;
   wire                      mcrs_o;
   wire                      ethphy_rst_n;
   wire                      eth0_mdc_pad_o;
   wire                      eth0_md_pad_io;
`endif
`ifdef XILINX_DDR2
 `include "xilinx_ddr2_params.v"
   localparam DEVICE_WIDTH    = 16;      // Memory device data width
   localparam real           CLK_PERIOD_NS   = CLK_PERIOD / 1000.0;
   localparam real           TCYC_200           = 5.0;
   localparam real           TPROP_DQS          = 0.00;  // Delay for DQS signal during Write Operation
   localparam real           TPROP_DQS_RD       = 0.00;  // Delay for DQS signal during Read Operation
   localparam real           TPROP_PCB_CTRL     = 0.00;  // Delay for Address and Ctrl signals
   localparam real           TPROP_PCB_DATA     = 0.00;  // Delay for data signal during Write operation
   localparam real           TPROP_PCB_DATA_RD  = 0.00;  // Delay for data signal during Read operation
 
   wire [DQ_WIDTH-1:0]        ddr2_dq_sdram;
   wire [DQS_WIDTH-1:0]      ddr2_dqs_sdram;
   wire [DQS_WIDTH-1:0]      ddr2_dqs_n_sdram;
   wire [DM_WIDTH-1:0]        ddr2_dm_sdram;
   reg [DM_WIDTH-1:0]         ddr2_dm_sdram_tmp;
   reg [CLK_WIDTH-1:0]        ddr2_ck_sdram;
   reg [CLK_WIDTH-1:0]        ddr2_ck_n_sdram;
   reg [ROW_WIDTH-1:0]        ddr2_a_sdram;
   reg [BANK_WIDTH-1:0]      ddr2_ba_sdram;
   reg                       ddr2_ras_n_sdram;
   reg                       ddr2_cas_n_sdram;
   reg                       ddr2_we_n_sdram;
   reg [CS_WIDTH-1:0]         ddr2_cs_n_sdram;
   reg [CKE_WIDTH-1:0]        ddr2_cke_sdram;
   reg [ODT_WIDTH-1:0]        ddr2_odt_sdram;
 
   wire [DQ_WIDTH-1:0]        ddr2_dq_fpga;
   wire [DQS_WIDTH-1:0]      ddr2_dqs_fpga;
   wire [DQS_WIDTH-1:0]      ddr2_dqs_n_fpga;
   wire [DM_WIDTH-1:0]        ddr2_dm_fpga;
   wire [CLK_WIDTH-1:0]      ddr2_ck_fpga;
   wire [CLK_WIDTH-1:0]      ddr2_ck_n_fpga;
   wire [ROW_WIDTH-1:0]      ddr2_a_fpga;
   wire [BANK_WIDTH-1:0]     ddr2_ba_fpga;
   wire                      ddr2_ras_n_fpga;
   wire                      ddr2_cas_n_fpga;
   wire                      ddr2_we_n_fpga;
   wire [CS_WIDTH-1:0]        ddr2_cs_n_fpga;
   wire [CKE_WIDTH-1:0]      ddr2_cke_fpga;
   wire [ODT_WIDTH-1:0]      ddr2_odt_fpga;
`endif
`ifdef XILINX_SSRAM
   wire                      sram_clk;
   wire                      sram_clk_fb;
   wire                      sram_adv_ld_n;
   wire [3:0]                 sram_bw;
   wire                      sram_cen;
   wire [21:1]               sram_flash_addr;
   wire [31:0]                sram_flash_data;
   wire                      sram_flash_oe_n;
   wire                      sram_flash_we_n;
   wire                      sram_mode;
`endif
`ifdef CFI_FLASH
   wire [15:0]        flash_dq_io;
   wire [23:0]        flash_adr_o;
   wire              flash_adv_n_o;
   wire              flash_ce_n_o;
   wire              flash_clk_o;
   wire              flash_oe_n_o;
   wire              flash_rst_n_o;
   wire              flash_wait_i;
   wire              flash_we_n_o;
`endif //  `ifdef CFI_FLASH
 
 
   orpsoc_top dut
     (
`ifdef JTAG_DEBUG
      .tms_pad_i                        (tms_pad_i),
      .tck_pad_i                        (tck_pad_i),
      .tdi_pad_i                        (tdi_pad_i),
      .tdo_pad_o                        (tdo_pad_o),
`endif
`ifdef XILINX_DDR2
      .ddr2_a                           (ddr2_a_fpga),
      .ddr2_ba                          (ddr2_ba_fpga),
      .ddr2_ras_n                       (ddr2_ras_n_fpga),
      .ddr2_cas_n                       (ddr2_cas_n_fpga),
      .ddr2_we_n                        (ddr2_we_n_fpga),
      .ddr2_cs_n                        (ddr2_cs_n_fpga),
      .ddr2_odt                         (ddr2_odt_fpga),
      .ddr2_cke                         (ddr2_cke_fpga),
      .ddr2_dm                          (ddr2_dm_fpga),
      .ddr2_ck                          (ddr2_ck_fpga),
      .ddr2_ck_n                        (ddr2_ck_n_fpga),
      .ddr2_dq                          (ddr2_dq_fpga),
      .ddr2_dqs                         (ddr2_dqs_fpga),
      .ddr2_dqs_n                       (ddr2_dqs_n_fpga),
`endif
`ifdef XILINX_SSRAM
      .sram_clk                         (sram_clk),
      .sram_flash_addr                  (sram_flash_addr),
      .sram_cen                         (sram_cen),
      .sram_flash_oe_n                  (sram_flash_oe_n),
      .sram_flash_we_n                  (sram_flash_we_n),
      .sram_bw                          (sram_bw),
      .sram_adv_ld_n                    (sram_adv_ld_n),
      .sram_mode                        (sram_mode),
      .sram_clk_fb                      (sram_clk_fb),
      .sram_flash_data                  (sram_flash_data),
`endif //  `ifdef XILINX_SSRAM
`ifdef CFI_FLASH
      .flash_dq_io                      (flash_dq_io),
      .flash_adr_o                      (flash_adr_o),
      .flash_adv_n_o                    (flash_adv_n_o),
      .flash_ce_n_o                     (flash_ce_n_o),
      .flash_clk_o                      (flash_clk_o),
      .flash_oe_n_o                     (flash_oe_n_o),
      .flash_rst_n_o                    (flash_rst_n_o),
      .flash_wait_i                     (flash_wait_i),
      .flash_we_n_o                     (flash_we_n_o),
`endif
`ifdef UART0
      .uart0_stx_pad_o                  (uart0_stx_pad_o),
      .uart0_srx_pad_i                  (uart0_srx_pad_i),
      .uart0_stx_expheader_pad_o        (uart0_stx_pad_o),
      .uart0_srx_expheader_pad_i        (uart0_srx_pad_i),
`endif
`ifdef SPI0
      /*
       via STARTUP_VIRTEX5
       .spi0_sck_o                      (spi0_sck_o),
       .spi0_miso_i                     (spi0_miso_i),
       */
      .spi0_mosi_o                      (spi0_mosi_o),
      .spi0_ss_o                        (spi0_ss_o),
`endif
`ifdef I2C0
      .i2c0_sda_io                      (i2c_sda),
      .i2c0_scl_io                      (i2c_scl),
`endif
`ifdef I2C1
      .i2c1_sda_io                      (i2c_sda),
      .i2c1_scl_io                      (i2c_scl),
`endif
`ifdef GPIO0
      .gpio0_io                         (gpio0_io),
`endif
`ifdef ETH0
      .eth0_tx_clk                      (mtx_clk_o),
      .eth0_tx_data                     (ethphy_mii_tx_d),
      .eth0_tx_en                       (ethphy_mii_tx_en),
      .eth0_tx_er                       (ethphy_mii_tx_err),
      .eth0_rx_clk                      (mrx_clk_o),
      .eth0_rx_data                     (mrxd_o),
      .eth0_dv                          (mrxdv_o),
      .eth0_rx_er                       (mrxerr_o),
      .eth0_col                         (mcoll_o),
      .eth0_crs                         (mcrs_o),
      .eth0_rst_n_o                     (ethphy_rst_n),
      .eth0_mdc_pad_o                   (eth0_mdc_pad_o),
      .eth0_md_pad_io                   (eth0_md_pad_io),
`endif //  `ifdef ETH0
 
      .sys_clk_in_p                     (clk_p),
      .sys_clk_in_n                     (clk_n),
 
      .rst_n_pad_i                      (rst_n)
      );
 
   //
   // Instantiate OR1200 monitor
   //
   or1200_monitor monitor();
 
`ifndef SIM_QUIET
 `define CPU_ic_top or1200_ic_top
 `define CPU_dc_top or1200_dc_top
   wire                      ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;
   always @(posedge ic_en)
     $display("Or1200 IC enabled at %t", $time);
 
   wire                      dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;
   always @(posedge dc_en)
     $display("Or1200 DC enabled at %t", $time);
`endif
 
 
`ifdef JTAG_DEBUG
 `ifdef VPI_DEBUG
   // Debugging interface
   vpi_debug_module vpi_dbg
     (
      .tms(tms_pad_i),
      .tck(tck_pad_i),
      .tdi(tdi_pad_i),
      .tdo(tdo_pad_o)
      );
 `else
   // If no VPI debugging, tie off JTAG inputs
   assign tdi_pad_i = 1;
   assign tck_pad_i = 0;
   assign tms_pad_i = 1;
 `endif // !`ifdef VPI_DEBUG_ENABLE
`endif //  `ifdef JTAG_DEBUG
 
`ifdef SPI0
   // STARTUP_VIRTEX5 module routes these out on the board.
   // So for now just connect directly to the internals here.
   assign spi0_sck_o = dut.spi0_sck_o;
   assign dut.spi0_miso_i = spi0_miso_i;
 
   // SPI flash memory - M25P16 compatible SPI protocol
   AT26DFxxx
     #(.MEMSIZE(2048*1024)) // 2MB flash on ML501
     spi0_flash
     (// Outputs
      .SO                                       (spi0_miso_i),
      // Inputs
      .CSB                                      (spi0_ss_o),
      .SCK                                      (spi0_sck_o),
      .SI                                       (spi0_mosi_o),
      .WPB                                      (1'b1)
      );
 
 
`endif //  `ifdef SPI0
 
`ifdef ETH0
 
   /* TX/RXes packets and checks them, enabled when ethernet MAC is */
 `include "eth_stim.v"
 
   eth_phy eth_phy0
     (
      // Outputs
      .mtx_clk_o                        (mtx_clk_o),
      .mrx_clk_o                        (mrx_clk_o),
      .mrxd_o                           (mrxd_o[3:0]),
      .mrxdv_o                          (mrxdv_o),
      .mrxerr_o                         (mrxerr_o),
      .mcoll_o                          (mcoll_o),
      .mcrs_o                           (mcrs_o),
      .link_o                           (),
      .speed_o                          (),
      .duplex_o                         (),
      .smii_clk_i                       (1'b0),
      .smii_sync_i                      (1'b0),
      .smii_rx_o                        (),
      // Inouts
      .md_io                            (eth0_md_pad_io),
      // Inputs
 `ifndef ETH0_PHY_RST
      // If no reset out from the design, hook up to the board's active low rst
      .m_rst_n_i                        (rst_n),
 `else
      .m_rst_n_i                        (ethphy_rst_n),
 `endif
      .mtxd_i                           (ethphy_mii_tx_d[3:0]),
      .mtxen_i                          (ethphy_mii_tx_en),
      .mtxerr_i                         (ethphy_mii_tx_err),
      .mdc_i                            (eth0_mdc_pad_o));
 
`endif //  `ifdef ETH0
 
`ifdef XILINX_SSRAM
   wire [18:0]                sram_a;
   wire [3:0]                 dqp;
 
   assign sram_a[18:0] = sram_flash_addr[19:1];
   wire                      sram_ce1b, sram_ce2, sram_ce3b;
   assign sram_ce1b = 1'b0;
   assign sram_ce2 = 1'b1;
   assign sram_ce3b = 1'b0;
   assign sram_clk_fb = sram_clk;
 
   cy7c1354 ssram0
     (
      // Inouts
      // This model puts each parity bit after each byte, but the ML501's part
      // doesn't, so we wire up the data bus like so.
      .d                                ({dqp[3],sram_flash_data[31:24],
                                          dqp[2],sram_flash_data[23:16],
                                          dqp[1],sram_flash_data[15:8],
                                          dqp[0],sram_flash_data[7:0]}),
      // Inputs
      .clk                              (sram_clk),
      .we_b                             (sram_flash_we_n),
      .adv_lb                           (sram_adv_ld_n),
      .ce1b                             (sram_ce1b),
      .ce2                              (sram_ce2),
      .ce3b                             (sram_ce3b),
      .oeb                              (sram_flash_oe_n),
      .cenb                             (sram_cen),
      .mode                             (sram_mode),
      .bws                              (sram_bw),
      .a                                (sram_a));
`endif
 
`ifdef XILINX_DDR2
 `ifndef GATE_SIM
   defparam dut.xilinx_ddr2_0.xilinx_ddr2_if0.ddr2_mig0.SIM_ONLY = 1;
 `endif
 
   always @( * ) begin
      ddr2_ck_sdram        <=  #(TPROP_PCB_CTRL) ddr2_ck_fpga;
      ddr2_ck_n_sdram      <=  #(TPROP_PCB_CTRL) ddr2_ck_n_fpga;
      ddr2_a_sdram    <=  #(TPROP_PCB_CTRL) ddr2_a_fpga;
      ddr2_ba_sdram         <=  #(TPROP_PCB_CTRL) ddr2_ba_fpga;
      ddr2_ras_n_sdram      <=  #(TPROP_PCB_CTRL) ddr2_ras_n_fpga;
      ddr2_cas_n_sdram      <=  #(TPROP_PCB_CTRL) ddr2_cas_n_fpga;
      ddr2_we_n_sdram       <=  #(TPROP_PCB_CTRL) ddr2_we_n_fpga;
      ddr2_cs_n_sdram       <=  #(TPROP_PCB_CTRL) ddr2_cs_n_fpga;
      ddr2_cke_sdram        <=  #(TPROP_PCB_CTRL) ddr2_cke_fpga;
      ddr2_odt_sdram        <=  #(TPROP_PCB_CTRL) ddr2_odt_fpga;
      ddr2_dm_sdram_tmp     <=  #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation
   end // always @ ( * )
 
   // Model delays on bi-directional BUS
   genvar dqwd;
   generate
      for (dqwd = 0;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
         wiredelay #
           (
            .Delay_g     (TPROP_PCB_DATA),
            .Delay_rd    (TPROP_PCB_DATA_RD)
            )
         u_delay_dq
           (
            .A           (ddr2_dq_fpga[dqwd]),
            .B           (ddr2_dq_sdram[dqwd]),
            .reset       (rst_n)
            );
      end
   endgenerate
 
   genvar dqswd;
   generate
      for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
         wiredelay #
           (
            .Delay_g     (TPROP_DQS),
            .Delay_rd    (TPROP_DQS_RD)
            )
         u_delay_dqs
           (
            .A           (ddr2_dqs_fpga[dqswd]),
            .B           (ddr2_dqs_sdram[dqswd]),
            .reset       (rst_n)
            );
 
         wiredelay #
           (
            .Delay_g     (TPROP_DQS),
            .Delay_rd    (TPROP_DQS_RD)
            )
         u_delay_dqs_n
           (
            .A           (ddr2_dqs_n_fpga[dqswd]),
            .B           (ddr2_dqs_n_sdram[dqswd]),
            .reset       (rst_n)
            );
      end
   endgenerate
 
   assign ddr2_dm_sdram = ddr2_dm_sdram_tmp;
   parameter NUM_PROGRAM_WORDS=1048576;
   integer ram_ptr, program_word_ptr, k;
   reg [31:0] tmp_program_word;
   reg [31:0] program_array [0:NUM_PROGRAM_WORDS-1]; // 1M words = 4MB
   reg [8*16-1:0] ddr2_ram_mem_line; //8*16-bits= 8 shorts (half-words)
   genvar         i, j;
   generate
      // if the data width is multiple of 16
      for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs // Loop of 1
         for(i = 0; i < DQS_WIDTH/2; i = i+1) begin : gen // Loop of 4 (DQS_WIDTH=8)
            initial
              begin
 
 `ifdef PRELOAD_RAM
  `include "ddr2_model_preload.v"
 `endif
              end
 
            ddr2_model u_mem0
              (
               .ck        (ddr2_ck_sdram[CLK_WIDTH*i/DQS_WIDTH]),
               .ck_n      (ddr2_ck_n_sdram[CLK_WIDTH*i/DQS_WIDTH]),
               .cke       (ddr2_cke_sdram[j]),
               .cs_n      (ddr2_cs_n_sdram[CS_WIDTH*i/DQS_WIDTH]),
               .ras_n     (ddr2_ras_n_sdram),
               .cas_n     (ddr2_cas_n_sdram),
               .we_n      (ddr2_we_n_sdram),
               .dm_rdqs   (ddr2_dm_sdram[(2*(i+1))-1 : i*2]),
               .ba        (ddr2_ba_sdram),
               .addr      (ddr2_a_sdram),
               .dq        (ddr2_dq_sdram[(16*(i+1))-1 : i*16]),
               .dqs       (ddr2_dqs_sdram[(2*(i+1))-1 : i*2]),
               .dqs_n     (ddr2_dqs_n_sdram[(2*(i+1))-1 : i*2]),
               .rdqs_n    (),
               .odt       (ddr2_odt_sdram[ODT_WIDTH*i/DQS_WIDTH])
               );
         end
      end
   endgenerate
 
`endif
 
 
`ifdef VCD
   reg vcd_go = 0;
   always @(vcd_go)
     begin
 
 `ifdef VCD_DELAY
        #(`VCD_DELAY);/*#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
        #(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
        #(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
        #(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
        #(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
        #(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
        #(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
        #(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
        #(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);#(`VCD_DELAY);
*/
 `endif
 
        // Delay by x insns
 `ifdef VCD_DELAY_INSNS
        #10; // Delay until after the value becomes valid
        while (monitor.insns < `VCD_DELAY_INSNS)
          @(posedge clk);
 `endif
 
 `ifdef SIMULATOR_MODELSIM
        // Modelsim can GZip VCDs on the fly if given in the suffix
  `define VCD_SUFFIX   ".vcd.gz"
 `else
  `define VCD_SUFFIX   ".vcd"
 `endif
 
 `ifndef SIM_QUIET
        $display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
 `endif
        $dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
 `ifndef VCD_DEPTH
  `define VCD_DEPTH 0
 `endif
        $dumpvars(`VCD_DEPTH);
 
     end
`endif //  `ifdef VCD
 
   initial
     begin
`ifndef SIM_QUIET
        $display("\n* Starting simulation of design RTL.\n* Test: %s\n",
                 `TEST_NAME_STRING );
`endif
 
`ifdef VCD
        vcd_go = 1;
`endif
 
     end // initial begin
 
`ifdef END_TIME
   initial begin
      #(`END_TIME);
 `ifndef SIM_QUIET
      $display("* Finish simulation due to END_TIME being set at %t", $time);
 `endif
      $finish;
   end
`endif
 
`ifdef END_INSNS
   initial begin
      #10
        while (monitor.insns < `END_INSNS)
          @(posedge clk);
 `ifndef SIM_QUIET
      $display("* Finish simulation due to END_INSNS count (%d) reached at %t",
               `END_INSNS, $time);
 `endif
      $finish;
   end
`endif
 
`ifdef UART0
   //   
   // UART0 decoder
   //   
   uart_decoder
     #(
        .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
        )
   uart0_decoder
     (
      .clk(clk),
      .uart_tx(uart0_stx_pad_o)
      );
 
   // Loopback UART lines
   assign uart0_srx_pad_i = uart0_stx_pad_o;
 
`endif //  `ifdef UART0
 
`ifdef CFI_FLASH
 
  wire [35:0] VCC;  // Supply Voltage
  wire [35:0] VCCQ; // Supply Voltage for I/O Buffers
  wire [35:0] VPP; // Optional Supply Voltage for Fast Program & Erase  
 
   wire       Info;      // Activate/Deactivate info device operation
   assign Info = 1;
   assign VCC = 36'd1700;
   assign VCCQ = 36'd1700;
   assign VPP = 36'd2000;
 
   x28fxxxp30 cfi_flash(flash_adr_o,
                        flash_dq_io,
                        flash_we_n_o,
                        flash_oe_n_o,
                        flash_ce_n_o,
                        flash_adv_n_o,
                        flash_clk_o,
                        flash_wait_i,
                        1'b1,
                        flash_rst_n_o,
                        VCC,
                        VCCQ,
                        VPP,
                        Info);
 
`endif //  `ifdef CFI_FLASH
 
endmodule // orpsoc_testbench
 
// Local Variables:
// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")
// verilog-library-files:()
// verilog-library-extensions:(".v" ".h")
// End:
 

Line No.	Rev	Author	Line
1	412	julius	`//////////////////////////////////////////////////////////////////////`
2			`/// ////`
3			`/// ORPSoC ML501 testbench ////`
4			`/// ////`
5			`/// Instantiate ORPSoC, monitors, provide stimulus ////`
6			`/// ////`
7			`/// Julius Baxter, julius@opencores.org ////`
8			`/// ////`
9			`//////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer. ////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation; ////`
21			`//// either version 2.1 of the License, or (at your option) any ////`
22			`//// later version. ////`
23			`//// ////`
24			`//// This source is distributed in the hope that it will be ////`
25			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
26			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
27			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
28			`//// details. ////`
29			`//// ////`
30			`//// You should have received a copy of the GNU Lesser General ////`
31			`//// Public License along with this source; if not, download it ////`
32			`//// from http://www.opencores.org/lgpl.shtml ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35
36			`include "orpsoc-defines.v"
37			`include "orpsoc-testbench-defines.v"
38			`include "test-defines.v"
39			`include "timescale.v"
40			`// Xilinx simulation:`
41			`include "glbl.v"
42
43			`module orpsoc_testbench;`
44
45			`// Clock and reset signal registers`
46			`reg clk = 0;`
47			`reg rst_n = 1; // Active LOW`
48
49			`always`
50			#((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
51
52			`wire clk_n, clk_p;`
53			`assign clk_p = clk;`
54			`assign clk_n = ~clk;`
55
56
57			`// Reset, ACTIVE LOW`
58			`initial`
59			`begin`
60			`#1;`
61			`repeat (32) @(negedge clk)`
62			`rst_n <= 1;`
63			`repeat (32) @(negedge clk)`
64			`rst_n <= 0;`
65			`repeat (32) @(negedge clk)`
66			`rst_n <= 1;`
67			`end`
68
69			`// Include design parameters file`
70			`include "orpsoc-params.v"
71
72			`// Pullup bus for I2C`
73			`tri1 i2c_scl, i2c_sda;`
74
75			`ifdef JTAG_DEBUG
76	415	julius	`wire tdo_pad_o;`
77			`wire tck_pad_i;`
78			`wire tms_pad_i;`
79			`wire tdi_pad_i;`
80	412	julius	`endif
81			`ifdef UART0
82	415	julius	`wire uart0_stx_pad_o;`
83			`wire uart0_srx_pad_i;`
84	412	julius	`endif
85			`ifdef GPIO0
86			`wire [gpio0_io_width-1:0] gpio0_io;`
87			`endif
88			`ifdef SPI0
89			`wire spi0_mosi_o;`
90			`wire spi0_miso_i;`
91			`wire spi0_sck_o;`
92			`wire spi0_hold_n_o;`
93			`wire spi0_w_n_o;`
94			`wire [spi0_ss_width-1:0] spi0_ss_o;`
95			`endif
96			`ifdef ETH0
97			`wire mtx_clk_o;`
98			`wire [3:0] ethphy_mii_tx_d;`
99			`wire ethphy_mii_tx_en;`
100			`wire ethphy_mii_tx_err;`
101			`wire mrx_clk_o;`
102			`wire [3:0] mrxd_o;`
103			`wire mrxdv_o;`
104			`wire mrxerr_o;`
105			`wire mcoll_o;`
106			`wire mcrs_o;`
107			`wire ethphy_rst_n;`
108			`wire eth0_mdc_pad_o;`
109			`wire eth0_md_pad_io;`
110			`endif
111			`ifdef XILINX_DDR2
112			`include "xilinx_ddr2_params.v"
113			`localparam DEVICE_WIDTH = 16; // Memory device data width`
114			`localparam real CLK_PERIOD_NS = CLK_PERIOD / 1000.0;`
115			`localparam real TCYC_200 = 5.0;`
116			`localparam real TPROP_DQS = 0.00; // Delay for DQS signal during Write Operation`
117			`localparam real TPROP_DQS_RD = 0.00; // Delay for DQS signal during Read Operation`
118			`localparam real TPROP_PCB_CTRL = 0.00; // Delay for Address and Ctrl signals`
119			`localparam real TPROP_PCB_DATA = 0.00; // Delay for data signal during Write operation`
120			`localparam real TPROP_PCB_DATA_RD = 0.00; // Delay for data signal during Read operation`
121
122			`wire [DQ_WIDTH-1:0] ddr2_dq_sdram;`
123			`wire [DQS_WIDTH-1:0] ddr2_dqs_sdram;`
124			`wire [DQS_WIDTH-1:0] ddr2_dqs_n_sdram;`
125			`wire [DM_WIDTH-1:0] ddr2_dm_sdram;`
126			`reg [DM_WIDTH-1:0] ddr2_dm_sdram_tmp;`
127			`reg [CLK_WIDTH-1:0] ddr2_ck_sdram;`
128			`reg [CLK_WIDTH-1:0] ddr2_ck_n_sdram;`
129			`reg [ROW_WIDTH-1:0] ddr2_a_sdram;`
130			`reg [BANK_WIDTH-1:0] ddr2_ba_sdram;`
131			`reg ddr2_ras_n_sdram;`
132			`reg ddr2_cas_n_sdram;`
133			`reg ddr2_we_n_sdram;`
134			`reg [CS_WIDTH-1:0] ddr2_cs_n_sdram;`
135			`reg [CKE_WIDTH-1:0] ddr2_cke_sdram;`
136			`reg [ODT_WIDTH-1:0] ddr2_odt_sdram;`
137
138			`wire [DQ_WIDTH-1:0] ddr2_dq_fpga;`
139			`wire [DQS_WIDTH-1:0] ddr2_dqs_fpga;`
140			`wire [DQS_WIDTH-1:0] ddr2_dqs_n_fpga;`
141			`wire [DM_WIDTH-1:0] ddr2_dm_fpga;`
142			`wire [CLK_WIDTH-1:0] ddr2_ck_fpga;`
143			`wire [CLK_WIDTH-1:0] ddr2_ck_n_fpga;`
144			`wire [ROW_WIDTH-1:0] ddr2_a_fpga;`
145			`wire [BANK_WIDTH-1:0] ddr2_ba_fpga;`
146			`wire ddr2_ras_n_fpga;`
147			`wire ddr2_cas_n_fpga;`
148			`wire ddr2_we_n_fpga;`
149			`wire [CS_WIDTH-1:0] ddr2_cs_n_fpga;`
150			`wire [CKE_WIDTH-1:0] ddr2_cke_fpga;`
151			`wire [ODT_WIDTH-1:0] ddr2_odt_fpga;`
152			`endif
153			`ifdef XILINX_SSRAM
154	415	julius	`wire sram_clk;`
155			`wire sram_clk_fb;`
156			`wire sram_adv_ld_n;`
157			`wire [3:0] sram_bw;`
158			`wire sram_cen;`
159			`wire [21:1] sram_flash_addr;`
160			`wire [31:0] sram_flash_data;`
161			`wire sram_flash_oe_n;`
162			`wire sram_flash_we_n;`
163			`wire sram_mode;`
164	412	julius	`endif
165	655	julius	`ifdef CFI_FLASH
166			`wire [15:0] flash_dq_io;`
167			`wire [23:0] flash_adr_o;`
168			`wire flash_adv_n_o;`
169			`wire flash_ce_n_o;`
170			`wire flash_clk_o;`
171			`wire flash_oe_n_o;`
172			`wire flash_rst_n_o;`
173			`wire flash_wait_i;`
174			`wire flash_we_n_o;`
175			`endif // `ifdef CFI_FLASH
176	412	julius
177	655	julius
178	412	julius	`orpsoc_top dut`
179			`(`
180			`ifdef JTAG_DEBUG
181			`.tms_pad_i (tms_pad_i),`
182			`.tck_pad_i (tck_pad_i),`
183			`.tdi_pad_i (tdi_pad_i),`
184			`.tdo_pad_o (tdo_pad_o),`
185			`endif
186			`ifdef XILINX_DDR2
187			`.ddr2_a (ddr2_a_fpga),`
188			`.ddr2_ba (ddr2_ba_fpga),`
189			`.ddr2_ras_n (ddr2_ras_n_fpga),`
190			`.ddr2_cas_n (ddr2_cas_n_fpga),`
191			`.ddr2_we_n (ddr2_we_n_fpga),`
192			`.ddr2_cs_n (ddr2_cs_n_fpga),`
193			`.ddr2_odt (ddr2_odt_fpga),`
194			`.ddr2_cke (ddr2_cke_fpga),`
195			`.ddr2_dm (ddr2_dm_fpga),`
196			`.ddr2_ck (ddr2_ck_fpga),`
197			`.ddr2_ck_n (ddr2_ck_n_fpga),`
198			`.ddr2_dq (ddr2_dq_fpga),`
199			`.ddr2_dqs (ddr2_dqs_fpga),`
200			`.ddr2_dqs_n (ddr2_dqs_n_fpga),`
201			`endif
202			`ifdef XILINX_SSRAM
203			`.sram_clk (sram_clk),`
204			`.sram_flash_addr (sram_flash_addr),`
205			`.sram_cen (sram_cen),`
206			`.sram_flash_oe_n (sram_flash_oe_n),`
207			`.sram_flash_we_n (sram_flash_we_n),`
208			`.sram_bw (sram_bw),`
209			`.sram_adv_ld_n (sram_adv_ld_n),`
210			`.sram_mode (sram_mode),`
211			`.sram_clk_fb (sram_clk_fb),`
212			`.sram_flash_data (sram_flash_data),`
213	655	julius	`endif // `ifdef XILINX_SSRAM
214			`ifdef CFI_FLASH
215			`.flash_dq_io (flash_dq_io),`
216			`.flash_adr_o (flash_adr_o),`
217			`.flash_adv_n_o (flash_adv_n_o),`
218			`.flash_ce_n_o (flash_ce_n_o),`
219			`.flash_clk_o (flash_clk_o),`
220			`.flash_oe_n_o (flash_oe_n_o),`
221			`.flash_rst_n_o (flash_rst_n_o),`
222			`.flash_wait_i (flash_wait_i),`
223			`.flash_we_n_o (flash_we_n_o),`
224			`endif
225	412	julius	`ifdef UART0
226			`.uart0_stx_pad_o (uart0_stx_pad_o),`
227			`.uart0_srx_pad_i (uart0_srx_pad_i),`
228			`.uart0_stx_expheader_pad_o (uart0_stx_pad_o),`
229			`.uart0_srx_expheader_pad_i (uart0_srx_pad_i),`
230			`endif
231			`ifdef SPI0
232	415	julius	`/*`
233			`via STARTUP_VIRTEX5`
234			`.spi0_sck_o (spi0_sck_o),`
235			`.spi0_miso_i (spi0_miso_i),`
236			`*/`
237	412	julius	`.spi0_mosi_o (spi0_mosi_o),`
238			`.spi0_ss_o (spi0_ss_o),`
239			`endif
240			`ifdef I2C0
241			`.i2c0_sda_io (i2c_sda),`
242			`.i2c0_scl_io (i2c_scl),`
243			`endif
244			`ifdef I2C1
245			`.i2c1_sda_io (i2c_sda),`
246			`.i2c1_scl_io (i2c_scl),`
247			`endif
248			`ifdef GPIO0
249			`.gpio0_io (gpio0_io),`
250			`endif
251			`ifdef ETH0
252			`.eth0_tx_clk (mtx_clk_o),`
253			`.eth0_tx_data (ethphy_mii_tx_d),`
254			`.eth0_tx_en (ethphy_mii_tx_en),`
255			`.eth0_tx_er (ethphy_mii_tx_err),`
256			`.eth0_rx_clk (mrx_clk_o),`
257			`.eth0_rx_data (mrxd_o),`
258			`.eth0_dv (mrxdv_o),`
259			`.eth0_rx_er (mrxerr_o),`
260			`.eth0_col (mcoll_o),`
261			`.eth0_crs (mcrs_o),`
262			`.eth0_rst_n_o (ethphy_rst_n),`
263			`.eth0_mdc_pad_o (eth0_mdc_pad_o),`
264			`.eth0_md_pad_io (eth0_md_pad_io),`
265			`endif // `ifdef ETH0
266
267			`.sys_clk_in_p (clk_p),`
268			`.sys_clk_in_n (clk_n),`
269
270			`.rst_n_pad_i (rst_n)`
271			`);`
272
273			`//`
274			`// Instantiate OR1200 monitor`
275			`//`
276			`or1200_monitor monitor();`
277
278			`ifndef SIM_QUIET
279			`define CPU_ic_top or1200_ic_top
280			`define CPU_dc_top or1200_dc_top
281	415	julius	`wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;`
282	412	julius	`always @(posedge ic_en)`
283			`$display("Or1200 IC enabled at %t", $time);`
284
285	415	julius	`wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;`
286	412	julius	`always @(posedge dc_en)`
287			`$display("Or1200 DC enabled at %t", $time);`
288			`endif
289
290
291			`ifdef JTAG_DEBUG
292			`ifdef VPI_DEBUG
293			`// Debugging interface`
294			`vpi_debug_module vpi_dbg`
295			`(`
296			`.tms(tms_pad_i),`
297			`.tck(tck_pad_i),`
298			`.tdi(tdi_pad_i),`
299			`.tdo(tdo_pad_o)`
300			`);`
301			`else
302			`// If no VPI debugging, tie off JTAG inputs`
303			`assign tdi_pad_i = 1;`
304			`assign tck_pad_i = 0;`
305			`assign tms_pad_i = 1;`
306			`endif // !`ifdef VPI_DEBUG_ENABLE
307			`endif // `ifdef JTAG_DEBUG
308
309			`ifdef SPI0
310	415	julius	`// STARTUP_VIRTEX5 module routes these out on the board.`
311			`// So for now just connect directly to the internals here.`
312			`assign spi0_sck_o = dut.spi0_sck_o;`
313			`assign dut.spi0_miso_i = spi0_miso_i;`
314
315	412	julius	`// SPI flash memory - M25P16 compatible SPI protocol`
316	415	julius	`AT26DFxxx`
317			`#(.MEMSIZE(2048*1024)) // 2MB flash on ML501`
318			`spi0_flash`
319	412	julius	`(// Outputs`
320			`.SO (spi0_miso_i),`
321			`// Inputs`
322			`.CSB (spi0_ss_o),`
323			`.SCK (spi0_sck_o),`
324			`.SI (spi0_mosi_o),`
325			`.WPB (1'b1)`
326			`);`
327	415	julius
328
329	412	julius	`endif // `ifdef SPI0
330
331			`ifdef ETH0
332
333			`/* TX/RXes packets and checks them, enabled when ethernet MAC is */`
334			`include "eth_stim.v"
335
336			`eth_phy eth_phy0`
337			`(`
338			`// Outputs`
339			`.mtx_clk_o (mtx_clk_o),`
340			`.mrx_clk_o (mrx_clk_o),`
341			`.mrxd_o (mrxd_o[3:0]),`
342			`.mrxdv_o (mrxdv_o),`
343			`.mrxerr_o (mrxerr_o),`
344			`.mcoll_o (mcoll_o),`
345			`.mcrs_o (mcrs_o),`
346			`.link_o (),`
347			`.speed_o (),`
348			`.duplex_o (),`
349			`.smii_clk_i (1'b0),`
350			`.smii_sync_i (1'b0),`
351			`.smii_rx_o (),`
352			`// Inouts`
353			`.md_io (eth0_md_pad_io),`
354			`// Inputs`
355			`ifndef ETH0_PHY_RST
356			`// If no reset out from the design, hook up to the board's active low rst`
357			`.m_rst_n_i (rst_n),`
358			`else
359			`.m_rst_n_i (ethphy_rst_n),`
360			`endif
361			`.mtxd_i (ethphy_mii_tx_d[3:0]),`
362			`.mtxen_i (ethphy_mii_tx_en),`
363			`.mtxerr_i (ethphy_mii_tx_err),`
364			`.mdc_i (eth0_mdc_pad_o));`
365
366			`endif // `ifdef ETH0
367
368			`ifdef XILINX_SSRAM
369	415	julius	`wire [18:0] sram_a;`
370			`wire [3:0] dqp;`
371	412	julius
372			`assign sram_a[18:0] = sram_flash_addr[19:1];`
373	415	julius	`wire sram_ce1b, sram_ce2, sram_ce3b;`
374	412	julius	`assign sram_ce1b = 1'b0;`
375			`assign sram_ce2 = 1'b1;`
376			`assign sram_ce3b = 1'b0;`
377			`assign sram_clk_fb = sram_clk;`
378
379			`cy7c1354 ssram0`
380			`(`
381			`// Inouts`
382			`// This model puts each parity bit after each byte, but the ML501's part`
383			`// doesn't, so we wire up the data bus like so.`
384			`.d ({dqp[3],sram_flash_data[31:24],`
385			`dqp[2],sram_flash_data[23:16],`
386			`dqp[1],sram_flash_data[15:8],`
387			`dqp[0],sram_flash_data[7:0]}),`
388			`// Inputs`
389			`.clk (sram_clk),`
390			`.we_b (sram_flash_we_n),`
391			`.adv_lb (sram_adv_ld_n),`
392			`.ce1b (sram_ce1b),`
393			`.ce2 (sram_ce2),`
394			`.ce3b (sram_ce3b),`
395			`.oeb (sram_flash_oe_n),`
396			`.cenb (sram_cen),`
397			`.mode (sram_mode),`
398			`.bws (sram_bw),`
399			`.a (sram_a));`
400			`endif
401
402			`ifdef XILINX_DDR2
403			`ifndef GATE_SIM
404			`defparam dut.xilinx_ddr2_0.xilinx_ddr2_if0.ddr2_mig0.SIM_ONLY = 1;`
405			`endif
406
407			`always @( * ) begin`
408			`ddr2_ck_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_fpga;`
409			`ddr2_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_n_fpga;`
410			`ddr2_a_sdram <= #(TPROP_PCB_CTRL) ddr2_a_fpga;`
411			`ddr2_ba_sdram <= #(TPROP_PCB_CTRL) ddr2_ba_fpga;`
412			`ddr2_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ras_n_fpga;`
413			`ddr2_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cas_n_fpga;`
414			`ddr2_we_n_sdram <= #(TPROP_PCB_CTRL) ddr2_we_n_fpga;`
415			`ddr2_cs_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cs_n_fpga;`
416			`ddr2_cke_sdram <= #(TPROP_PCB_CTRL) ddr2_cke_fpga;`
417			`ddr2_odt_sdram <= #(TPROP_PCB_CTRL) ddr2_odt_fpga;`
418			`ddr2_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation`
419			`end // always @ ( * )`
420
421			`// Model delays on bi-directional BUS`
422			`genvar dqwd;`
423			`generate`
424			`for (dqwd = 0;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay`
425			`wiredelay #`
426			`(`
427			`.Delay_g (TPROP_PCB_DATA),`
428			`.Delay_rd (TPROP_PCB_DATA_RD)`
429			`)`
430			`u_delay_dq`
431			`(`
432			`.A (ddr2_dq_fpga[dqwd]),`
433			`.B (ddr2_dq_sdram[dqwd]),`
434			`.reset (rst_n)`
435			`);`
436			`end`
437			`endgenerate`
438
439			`genvar dqswd;`
440			`generate`
441			`for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay`
442			`wiredelay #`
443			`(`
444			`.Delay_g (TPROP_DQS),`
445			`.Delay_rd (TPROP_DQS_RD)`
446			`)`
447			`u_delay_dqs`
448			`(`
449			`.A (ddr2_dqs_fpga[dqswd]),`
450			`.B (ddr2_dqs_sdram[dqswd]),`
451			`.reset (rst_n)`
452			`);`
453
454			`wiredelay #`
455			`(`
456			`.Delay_g (TPROP_DQS),`
457			`.Delay_rd (TPROP_DQS_RD)`
458			`)`
459			`u_delay_dqs_n`
460			`(`
461			`.A (ddr2_dqs_n_fpga[dqswd]),`
462			`.B (ddr2_dqs_n_sdram[dqswd]),`
463			`.reset (rst_n)`
464			`);`
465			`end`
466			`endgenerate`
467
468			`assign ddr2_dm_sdram = ddr2_dm_sdram_tmp;`
469			`parameter NUM_PROGRAM_WORDS=1048576;`
470			`integer ram_ptr, program_word_ptr, k;`
471			`reg [31:0] tmp_program_word;`
472			`reg [31:0] program_array [0:NUM_PROGRAM_WORDS-1]; // 1M words = 4MB`
473			`reg [816-1:0] ddr2_ram_mem_line; //816-bits= 8 shorts (half-words)`
474			`genvar i, j;`
475			`generate`
476			`// if the data width is multiple of 16`
477			`for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs // Loop of 1`
478			`for(i = 0; i < DQS_WIDTH/2; i = i+1) begin : gen // Loop of 4 (DQS_WIDTH=8)`
479			`initial`
480			`begin`
481
482			`ifdef PRELOAD_RAM
483			`include "ddr2_model_preload.v"
484	415	julius	`endif
485			`end`
486
487			`ddr2_model u_mem0`
488			`(`
489			`.ck (ddr2_ck_sdram[CLK_WIDTH*i/DQS_WIDTH]),`
490			`.ck_n (ddr2_ck_n_sdram[CLK_WIDTH*i/DQS_WIDTH]),`
491			`.cke (ddr2_cke_sdram[j]),`
492			`.cs_n (ddr2_cs_n_sdram[CS_WIDTH*i/DQS_WIDTH]),`
493			`.ras_n (ddr2_ras_n_sdram),`
494			`.cas_n (ddr2_cas_n_sdram),`
495			`.we_n (ddr2_we_n_sdram),`
496			`.dm_rdqs (ddr2_dm_sdram[(2(i+1))-1 : i2]),`
497			`.ba (ddr2_ba_sdram),`
498			`.addr (ddr2_a_sdram),`
499			`.dq (ddr2_dq_sdram[(16(i+1))-1 : i16]),`
500			`.dqs (ddr2_dqs_sdram[(2(i+1))-1 : i2]),`

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [orpsoc_testbench.v] - Blame information for rev 856