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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [gpio/] [gpio.v] - Blame information for rev 425

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1 408 julius 
/*
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 *
3 412 julius 
 * Simple 24-bit wide GPIO module
4 408 julius 
 *
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 * Can be made wider as needed, but must be done manually.
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 *
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 * First lot of bytes are the GPIO I/O regs
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 * Second lot are the direction registers
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 *
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 * Set direction bit to '1' to output corresponding data bit.
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 *
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 * Register mapping:
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 *
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 * For 8 GPIOs we would have
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 * adr 0: gpio data 7:0
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 * adr 1: gpio data 15:8
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 * adr 2: gpio data 23:16
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 * adr 3: gpio dir 7:0
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 * adr 4: gpio dir 15:8
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 * adr 5: gpio dir 23:16
21 408 julius 
 *
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 * Backend pinout file needs to be updated for any GPIO width changes.
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 *
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 */
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module gpio(
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            wb_clk,
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            wb_rst,
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            wb_adr_i,
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            wb_dat_i,
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            wb_we_i,
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            wb_cyc_i,
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            wb_stb_i,
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            wb_cti_i,
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            wb_bte_i,
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            wb_ack_o,
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            wb_dat_o,
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            wb_err_o,
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            wb_rty_o,
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            gpio_io);
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   parameter gpio_io_width = 24;
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   parameter gpio_dir_reset_val = 0;
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   parameter gpio_o_reset_val = 0;
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   parameter wb_dat_width = 8;
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   parameter wb_adr_width = 3; // 8 bytes addressable
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   input wb_clk;
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   input wb_rst;
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   input [wb_adr_width-1:0] wb_adr_i;
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   input [wb_dat_width-1:0] wb_dat_i;
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   input                    wb_we_i;
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   input                    wb_cyc_i;
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   input                    wb_stb_i;
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   input [2:0]               wb_cti_i;
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   input [1:0]               wb_bte_i;
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   output reg [wb_dat_width-1:0] wb_dat_o; // constantly sampling gpio in bus
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   output reg                wb_ack_o;
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   output                    wb_err_o;
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   output                    wb_rty_o;
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   inout [gpio_io_width-1:0] gpio_io;
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   // Internal registers
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   reg [gpio_io_width-1:0]   gpio_dir;
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   reg [gpio_io_width-1:0]   gpio_o;
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   wire [gpio_io_width-1:0]  gpio_i;
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   // Tristate logic for IO
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   genvar                    i;
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   generate
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      for (i=0;i<gpio_io_width;i=i+1)  begin: gpio_tris
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         assign gpio_io[i] = (gpio_dir[i]) ? gpio_o[i] : 1'bz;
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         assign gpio_i[i] = (gpio_dir[i]) ? gpio_o[i] : gpio_io[i];
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      end
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   endgenerate
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   // GPIO data out register
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   always @(posedge wb_clk)
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     if (wb_rst)
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       gpio_o <= 0; // All set to in at reset
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     else if (wb_stb_i & wb_we_i)
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       begin
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          if (wb_adr_i == 0)
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            gpio_o[7:0] <= wb_dat_i;
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          if (wb_adr_i == 1)
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            gpio_o[15:8] <= wb_dat_i;
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          if (wb_adr_i == 2)
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            gpio_o[23:16] <= wb_dat_i;
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          /* Add appropriate address detection here for wider GPIO */
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       end
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   // GPIO dir register
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   always @(posedge wb_clk)
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     if (wb_rst)
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       gpio_dir <= 0; // All set to in at reset
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     else if (wb_stb_i & wb_we_i)
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       begin
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          if (wb_adr_i == ((gpio_io_width/8)))
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            gpio_dir[7:0] <= wb_dat_i;
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          if (wb_adr_i == ((gpio_io_width/8)+1))
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            gpio_dir[15:8] <= wb_dat_i;
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          if (wb_adr_i == ((gpio_io_width/8)+2))
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            //gpio_dir[23:16] <= wb_dat_i;
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            gpio_dir[21:16] <= wb_dat_i[5:0];
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          /* Add appropriate address detection here for wider GPIO */
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       end
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   // Register the gpio in signal
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   always @(posedge wb_clk)
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     begin
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        // Data regs
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        if (wb_adr_i == 0)
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          wb_dat_o[7:0] <= gpio_i[7:0];
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        if (wb_adr_i == 1)
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          wb_dat_o[7:0] <= gpio_i[15:8];
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        if (wb_adr_i == 2)
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          wb_dat_o[7:0] <= gpio_i[23:16];
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        /* Add appropriate address detection here for wider GPIO */
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        // Direction regs
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        if (wb_adr_i == ((gpio_io_width/8)))
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          wb_dat_o[7:0] <= gpio_dir[7:0];
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        if (wb_adr_i == ((gpio_io_width/8)+1))
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          wb_dat_o[7:0] <= gpio_dir[15:8];
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        if (wb_adr_i == ((gpio_io_width/8)+2))
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          wb_dat_o[7:0] <= gpio_dir[23:16];
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        /* Add appropriate address detection here for wider GPIO */
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     end
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   // Ack generation
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   always @(posedge wb_clk)
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     if (wb_rst)
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       wb_ack_o <= 0;
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     else if (wb_ack_o)
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       wb_ack_o <= 0;
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     else if (wb_stb_i & !wb_ack_o)
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       wb_ack_o <= 1;
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   assign wb_err_o = 0;
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   assign wb_rty_o = 0;
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endmodule // gpio

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