| 1 |
412 |
julius |
//////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//// ////
|
| 3 |
|
|
//// dbg_defines.v ////
|
| 4 |
|
|
//// ////
|
| 5 |
|
|
//// ////
|
| 6 |
|
|
//// This file is part of the SoC Debug Interface. ////
|
| 7 |
|
|
//// http://www.opencores.org/projects/DebugInterface/ ////
|
| 8 |
|
|
//// ////
|
| 9 |
|
|
//// Author(s): ////
|
| 10 |
|
|
//// Igor Mohor (igorm@opencores.org) ////
|
| 11 |
|
|
//// ////
|
| 12 |
|
|
//// ////
|
| 13 |
|
|
//// All additional information is avaliable in the README.txt ////
|
| 14 |
|
|
//// file. ////
|
| 15 |
|
|
//// ////
|
| 16 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 17 |
|
|
//// ////
|
| 18 |
|
|
//// Copyright (C) 2000 - 2004 Authors ////
|
| 19 |
|
|
//// ////
|
| 20 |
|
|
//// This source file may be used and distributed without ////
|
| 21 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 22 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 23 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 24 |
|
|
//// ////
|
| 25 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 26 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 27 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 28 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 29 |
|
|
//// later version. ////
|
| 30 |
|
|
//// ////
|
| 31 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 32 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 33 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 34 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 35 |
|
|
//// details. ////
|
| 36 |
|
|
//// ////
|
| 37 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 38 |
|
|
//// Public License along with this source; if not, download it ////
|
| 39 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 40 |
|
|
//// ////
|
| 41 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 42 |
|
|
//
|
| 43 |
|
|
// CVS Revision History
|
| 44 |
|
|
//
|
| 45 |
|
|
// $Log: dbg_defines.v,v $
|
| 46 |
|
|
// Revision 1.20 2004/04/01 11:56:59 igorm
|
| 47 |
|
|
// Port names and defines for the supported CPUs changed.
|
| 48 |
|
|
//
|
| 49 |
|
|
// Revision 1.19 2004/03/28 20:27:02 igorm
|
| 50 |
|
|
// New release of the debug interface (3rd. release).
|
| 51 |
|
|
//
|
| 52 |
|
|
// Revision 1.18 2004/03/22 16:35:46 igorm
|
| 53 |
|
|
// Temp version before changing dbg interface.
|
| 54 |
|
|
//
|
| 55 |
|
|
// Revision 1.17 2004/01/30 10:24:30 mohor
|
| 56 |
|
|
// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
|
| 57 |
|
|
// turned on.
|
| 58 |
|
|
//
|
| 59 |
|
|
// Revision 1.16 2004/01/20 14:23:45 mohor
|
| 60 |
|
|
// Define name changed.
|
| 61 |
|
|
//
|
| 62 |
|
|
// Revision 1.15 2003/12/23 15:07:34 mohor
|
| 63 |
|
|
// New directory structure. New version of the debug interface.
|
| 64 |
|
|
// Files that are not needed removed.
|
| 65 |
|
|
//
|
| 66 |
|
|
// Revision 1.14 2003/10/23 16:17:00 mohor
|
| 67 |
|
|
// CRC logic changed.
|
| 68 |
|
|
//
|
| 69 |
|
|
// Revision 1.13 2003/10/21 09:48:31 simons
|
| 70 |
|
|
// Mbist support added.
|
| 71 |
|
|
//
|
| 72 |
|
|
// Revision 1.12 2003/09/17 14:38:57 simons
|
| 73 |
|
|
// WB_CNTL register added, some syncronization fixes.
|
| 74 |
|
|
//
|
| 75 |
|
|
// Revision 1.11 2003/08/28 13:55:21 simons
|
| 76 |
|
|
// Three more chains added for cpu debug access.
|
| 77 |
|
|
//
|
| 78 |
|
|
// Revision 1.10 2003/07/31 12:19:49 simons
|
| 79 |
|
|
// Multiple cpu support added.
|
| 80 |
|
|
//
|
| 81 |
|
|
// Revision 1.9 2002/05/07 14:43:59 mohor
|
| 82 |
|
|
// mon_cntl_o signals that controls monitor mux added.
|
| 83 |
|
|
//
|
| 84 |
|
|
// Revision 1.8 2002/01/25 07:58:34 mohor
|
| 85 |
|
|
// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
|
| 86 |
|
|
// not filled-in. Tested in hw.
|
| 87 |
|
|
//
|
| 88 |
|
|
// Revision 1.7 2001/12/06 10:08:06 mohor
|
| 89 |
|
|
// Warnings from synthesys tools fixed.
|
| 90 |
|
|
//
|
| 91 |
|
|
// Revision 1.6 2001/11/28 09:38:30 mohor
|
| 92 |
|
|
// Trace disabled by default.
|
| 93 |
|
|
//
|
| 94 |
|
|
// Revision 1.5 2001/10/15 09:55:47 mohor
|
| 95 |
|
|
// Wishbone interface added, few fixes for better performance,
|
| 96 |
|
|
// hooks for boundary scan testing added.
|
| 97 |
|
|
//
|
| 98 |
|
|
// Revision 1.4 2001/09/24 14:06:42 mohor
|
| 99 |
|
|
// Changes connected to the OpenRISC access (SPR read, SPR write).
|
| 100 |
|
|
//
|
| 101 |
|
|
// Revision 1.3 2001/09/20 10:11:25 mohor
|
| 102 |
|
|
// Working version. Few bugs fixed, comments added.
|
| 103 |
|
|
//
|
| 104 |
|
|
// Revision 1.2 2001/09/18 14:13:47 mohor
|
| 105 |
|
|
// Trace fixed. Some registers changed, trace simplified.
|
| 106 |
|
|
//
|
| 107 |
|
|
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
|
| 108 |
|
|
// Initial official release.
|
| 109 |
|
|
//
|
| 110 |
|
|
// Revision 1.3 2001/06/01 22:22:35 mohor
|
| 111 |
|
|
// This is a backup. It is not a fully working version. Not for use, yet.
|
| 112 |
|
|
//
|
| 113 |
|
|
// Revision 1.2 2001/05/18 13:10:00 mohor
|
| 114 |
|
|
// Headers changed. All additional information is now avaliable in the README.txt file.
|
| 115 |
|
|
//
|
| 116 |
|
|
// Revision 1.1.1.1 2001/05/18 06:35:08 mohor
|
| 117 |
|
|
// Initial release
|
| 118 |
|
|
//
|
| 119 |
|
|
//
|
| 120 |
|
|
|
| 121 |
|
|
|
| 122 |
|
|
// Length of the MODULE ID register
|
| 123 |
|
|
`define DBG_TOP_MODULE_ID_LENGTH 4
|
| 124 |
|
|
|
| 125 |
|
|
// Length of data
|
| 126 |
|
|
`define DBG_TOP_MODULE_DATA_LEN `DBG_TOP_MODULE_ID_LENGTH + 1
|
| 127 |
|
|
`define DBG_TOP_DATA_CNT 3
|
| 128 |
|
|
|
| 129 |
|
|
// Length of status
|
| 130 |
|
|
`define DBG_TOP_STATUS_LEN 3'd4
|
| 131 |
|
|
`define DBG_TOP_STATUS_CNT_WIDTH 3
|
| 132 |
|
|
|
| 133 |
|
|
// Length of the CRC
|
| 134 |
|
|
`define DBG_TOP_CRC_LEN 32
|
| 135 |
|
|
`define DBG_TOP_CRC_CNT 6
|
| 136 |
|
|
|
| 137 |
|
|
// Chains
|
| 138 |
|
|
`define DBG_TOP_WISHBONE_DEBUG_MODULE 4'h0
|
| 139 |
|
|
`define DBG_TOP_CPU0_DEBUG_MODULE 4'h1
|
| 140 |
|
|
`define DBG_TOP_CPU1_DEBUG_MODULE 4'h2
|
| 141 |
|
|
|
| 142 |
|
|
// If WISHBONE sub-module is supported uncomment the folowing line
|
| 143 |
|
|
`define DBG_WISHBONE_SUPPORTED
|
| 144 |
|
|
|
| 145 |
|
|
// If CPU_0 sub-module is supported uncomment the folowing line
|
| 146 |
|
|
`define DBG_CPU0_SUPPORTED
|
| 147 |
|
|
|
| 148 |
|
|
// If CPU_1 sub-module is supported uncomment the folowing line
|
| 149 |
|
|
//`define DBG_CPU1_SUPPORTED
|
| 150 |
|
|
|
| 151 |
|
|
// If more debug info is needed, uncomment the follofing line
|
| 152 |
|
|
//`define DBG_MORE_INFO
|
| 153 |
|
|
|
