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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [include/] [ethmac_defines.v] - Blame information for rev 530

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1 412 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_defines.v                                               ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://opencores.org/project,ethmac                         ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  Modified by:                                                ////
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////      - Julius Baxter (julius@opencores.org)                  ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001, 2002 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//`define ETH_BIST                    // Bist for usage with Virtual Silicon RAMS
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`define ETH_MBIST_CTRL_WIDTH 3        // width of MBIST control bus
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// Generic FIFO implementation - hopefully synthesizable with Synplify
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//`define ETH_FIFO_GENERIC
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                                      // specific elements.
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`define ETH_FIFO_XILINX
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//`define ETH_FIFO_RAMB18
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`define ETH_MODER_ADR         8'h0    // 0x0 
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`define ETH_INT_SOURCE_ADR    8'h1    // 0x4 
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`define ETH_INT_MASK_ADR      8'h2    // 0x8 
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`define ETH_IPGT_ADR          8'h3    // 0xC 
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`define ETH_IPGR1_ADR         8'h4    // 0x10
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`define ETH_IPGR2_ADR         8'h5    // 0x14
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`define ETH_PACKETLEN_ADR     8'h6    // 0x18
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`define ETH_COLLCONF_ADR      8'h7    // 0x1C
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`define ETH_TX_BD_NUM_ADR     8'h8    // 0x20
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`define ETH_CTRLMODER_ADR     8'h9    // 0x24
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`define ETH_MIIMODER_ADR      8'hA    // 0x28
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`define ETH_MIICOMMAND_ADR    8'hB    // 0x2C
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`define ETH_MIIADDRESS_ADR    8'hC    // 0x30
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`define ETH_MIITX_DATA_ADR    8'hD    // 0x34
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`define ETH_MIIRX_DATA_ADR    8'hE    // 0x38
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`define ETH_MIISTATUS_ADR     8'hF    // 0x3C
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`define ETH_MAC_ADDR0_ADR     8'h10   // 0x40
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`define ETH_MAC_ADDR1_ADR     8'h11   // 0x44
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`define ETH_HASH0_ADR         8'h12   // 0x48
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`define ETH_HASH1_ADR         8'h13   // 0x4C
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`define ETH_TX_CTRL_ADR       8'h14   // 0x50
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`define ETH_RX_CTRL_ADR       8'h15   // 0x54
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`define ETH_DBG_ADR           8'h16   // 0x58
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`define ETH_MODER_DEF_0         8'h00
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`define ETH_MODER_DEF_1         8'hA0
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`define ETH_MODER_DEF_2         1'h0
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`define ETH_INT_MASK_DEF_0      7'h0
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`define ETH_IPGT_DEF_0          7'h12
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`define ETH_IPGR1_DEF_0         7'h0C
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`define ETH_IPGR2_DEF_0         7'h12
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`define ETH_PACKETLEN_DEF_0     8'h00
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`define ETH_PACKETLEN_DEF_1     8'h06
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`define ETH_PACKETLEN_DEF_2     8'h40
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`define ETH_PACKETLEN_DEF_3     8'h00
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`define ETH_COLLCONF_DEF_0      6'h3f
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`define ETH_COLLCONF_DEF_2      4'hF
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`define ETH_TX_BD_NUM_DEF_0     8'h40
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`define ETH_CTRLMODER_DEF_0     3'h0
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`define ETH_MIIMODER_DEF_0      8'h64
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`define ETH_MIIMODER_DEF_1      1'h0
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`define ETH_MIIADDRESS_DEF_0    5'h00
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`define ETH_MIIADDRESS_DEF_1    5'h00
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`define ETH_MIITX_DATA_DEF_0    8'h00
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`define ETH_MIITX_DATA_DEF_1    8'h00
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`define ETH_MIIRX_DATA_DEF     16'h0000 // not written from WB
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`define ETH_MAC_ADDR0_DEF_0     8'h00
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`define ETH_MAC_ADDR0_DEF_1     8'h00
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`define ETH_MAC_ADDR0_DEF_2     8'h00
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`define ETH_MAC_ADDR0_DEF_3     8'h00
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`define ETH_MAC_ADDR1_DEF_0     8'h00
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`define ETH_MAC_ADDR1_DEF_1     8'h00
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`define ETH_HASH0_DEF_0         8'h00
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`define ETH_HASH0_DEF_1         8'h00
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`define ETH_HASH0_DEF_2         8'h00
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`define ETH_HASH0_DEF_3         8'h00
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`define ETH_HASH1_DEF_0         8'h00
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`define ETH_HASH1_DEF_1         8'h00
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`define ETH_HASH1_DEF_2         8'h00
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`define ETH_HASH1_DEF_3         8'h00
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`define ETH_TX_CTRL_DEF_0       8'h00 //
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`define ETH_TX_CTRL_DEF_1       8'h00 //
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`define ETH_TX_CTRL_DEF_2       1'h0  //
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`define ETH_RX_CTRL_DEF_0       8'h00
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`define ETH_RX_CTRL_DEF_1       8'h00
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`define ETH_MODER_WIDTH_0       8
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`define ETH_MODER_WIDTH_1       8
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`define ETH_MODER_WIDTH_2       1
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`define ETH_INT_SOURCE_WIDTH_0  7
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`define ETH_INT_MASK_WIDTH_0    7
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`define ETH_IPGT_WIDTH_0        7
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`define ETH_IPGR1_WIDTH_0       7
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`define ETH_IPGR2_WIDTH_0       7
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`define ETH_PACKETLEN_WIDTH_0   8
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`define ETH_PACKETLEN_WIDTH_1   8
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`define ETH_PACKETLEN_WIDTH_2   8
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`define ETH_PACKETLEN_WIDTH_3   8
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`define ETH_COLLCONF_WIDTH_0    6
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`define ETH_COLLCONF_WIDTH_2    4
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`define ETH_TX_BD_NUM_WIDTH_0   8
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`define ETH_CTRLMODER_WIDTH_0   3
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`define ETH_MIIMODER_WIDTH_0    8
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`define ETH_MIIMODER_WIDTH_1    1
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`define ETH_MIICOMMAND_WIDTH_0  3
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`define ETH_MIIADDRESS_WIDTH_0  5
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`define ETH_MIIADDRESS_WIDTH_1  5
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`define ETH_MIITX_DATA_WIDTH_0  8
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`define ETH_MIITX_DATA_WIDTH_1  8
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`define ETH_MIIRX_DATA_WIDTH    16 // not written from WB
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`define ETH_MIISTATUS_WIDTH     3 // not written from WB
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`define ETH_MAC_ADDR0_WIDTH_0   8
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`define ETH_MAC_ADDR0_WIDTH_1   8
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`define ETH_MAC_ADDR0_WIDTH_2   8
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`define ETH_MAC_ADDR0_WIDTH_3   8
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`define ETH_MAC_ADDR1_WIDTH_0   8
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`define ETH_MAC_ADDR1_WIDTH_1   8
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`define ETH_HASH0_WIDTH_0       8
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`define ETH_HASH0_WIDTH_1       8
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`define ETH_HASH0_WIDTH_2       8
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`define ETH_HASH0_WIDTH_3       8
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`define ETH_HASH1_WIDTH_0       8
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`define ETH_HASH1_WIDTH_1       8
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`define ETH_HASH1_WIDTH_2       8
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`define ETH_HASH1_WIDTH_3       8
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`define ETH_TX_CTRL_WIDTH_0     8
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`define ETH_TX_CTRL_WIDTH_1     8
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`define ETH_TX_CTRL_WIDTH_2     1
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`define ETH_RX_CTRL_WIDTH_0     8
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`define ETH_RX_CTRL_WIDTH_1     8
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// Outputs are registered (uncomment when needed)
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`define ETH_REGISTERED_OUTPUTS
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// Settings for TX FIFO
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`define ETH_TX_FIFO_DATA_WIDTH 32
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// Defines for ethernet TX fifo size - impacts FPGA resource usage
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//`define ETH_TX_64BYTE_FIFO     // 64 byte TX buffer - uncomment this
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//`define ETH_TX_128BYTE_FIFO  // 128 byte TX buffer - uncomment this
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`define ETH_TX_256BYTE_FIFO  // 256 byte TX buffer - uncomment this
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//`define ETH_TX_512BYTE_FIFO  // 512 byte TX buffer - uncomment this
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//`define ETH_TX_1KBYTE_FIFO     // 1024 byte TX buffer - uncomment this
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//`define ETH_TX_FULL_PACKET_FIFO  // Full 1500 byte TX buffer - uncomment this
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`ifdef  ETH_TX_FULL_PACKET_FIFO
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 `define ETH_TX_FIFO_CNT_WIDTH  9
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 `define ETH_TX_FIFO_DEPTH      375
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`endif
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`ifdef ETH_TX_1KBYTE_FIFO
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 `define ETH_TX_FIFO_CNT_WIDTH  8
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 `define ETH_TX_FIFO_DEPTH      256
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`endif
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`ifdef ETH_TX_512BYTE_FIFO
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 `define ETH_TX_FIFO_CNT_WIDTH  7
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 `define ETH_TX_FIFO_DEPTH      128
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`endif
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`ifdef ETH_TX_256BYTE_FIFO
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 `define ETH_TX_FIFO_CNT_WIDTH  6
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 `define ETH_TX_FIFO_DEPTH      64
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`endif
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`ifdef ETH_TX_128BYTE_FIFO
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 `define ETH_TX_FIFO_CNT_WIDTH  5
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 `define ETH_TX_FIFO_DEPTH      32
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`endif
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`ifdef ETH_TX_128BYTE_FIFO
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 `define ETH_TX_FIFO_CNT_WIDTH  4
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 `define ETH_TX_FIFO_DEPTH      16
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`endif
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// Settings for RX FIFO
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//`define ETH_RX_FIFO_CNT_WIDTH  8
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//`define ETH_RX_FIFO_DEPTH      256
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//`define ETH_RX_FIFO_CNT_WIDTH  7
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`define ETH_RX_FIFO_DEPTH      128
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`define ETH_RX_FIFO_CNT_WIDTH  6
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//`define ETH_RX_FIFO_DEPTH      64
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//`define ETH_RX_FIFO_CNT_WIDTH  5
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//`define ETH_RX_FIFO_DEPTH      32
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//`define ETH_RX_FIFO_CNT_WIDTH  4
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//`define ETH_RX_FIFO_DEPTH      16
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`define ETH_RX_FIFO_DATA_WIDTH 32
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// Burst length
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`define BURST_4BEAT
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`ifdef BURST_4BEAT
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 `define ETH_BURST_LENGTH       4    // Change also ETH_BURST_CNT_WIDTH
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 `define ETH_BURST_CNT_WIDTH    3    // The counter must be width enough to count to ETH_BURST_LENGTH
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`endif
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//`define ETH_BURST_LENGTH      32    // Change also ETH_BURST_CNT_WIDTH
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//`define ETH_BURST_CNT_WIDTH    7    // The counter must be width enough to count to ETH_BURST_LENGTH
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// Undefine this to enable bursting for RX (writing to memory)
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`define ETH_RX_BURST_EN
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// WISHBONE interface is Revision B3 compliant (uncomment when needed)
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`define ETH_WISHBONE_B3
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// Hack where the transmit logic polls each of the TX buffers instead of having to keep track of what's going on
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//`define TXBD_POLL
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// Define this to allow reading of the Wishbone control state machine on reg
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// address 0x58
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//`define WISHBONE_DEBUG

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