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//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's definitions                                        ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://opencores.org/project,or1k                           ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Defines for the OR1200 core                                 ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - add parameters that are missing                          ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// $Log: or1200_defines.v,v $
45
// Revision 2.0  2010/06/30 11:00:00  ORSoC
46
// Minor update: 
47
// Defines added, bugs fixed. 
48
 
49
//
50
// Dump VCD
51
//
52
//`define OR1200_VCD_DUMP
53
 
54
//
55
// Generate debug messages during simulation
56
//
57
//`define OR1200_VERBOSE
58
 
59
//  `define OR1200_ASIC
60
////////////////////////////////////////////////////////
61
//
62
// Typical configuration for an ASIC
63
//
64
`ifdef OR1200_ASIC
65
 
66
//
67
// Target ASIC memories
68
//
69
//`define OR1200_ARTISAN_SSP
70
//`define OR1200_ARTISAN_SDP
71
//`define OR1200_ARTISAN_STP
72
`define OR1200_VIRTUALSILICON_SSP
73
//`define OR1200_VIRTUALSILICON_STP_T1
74
//`define OR1200_VIRTUALSILICON_STP_T2
75
 
76
//
77
// Do not implement Data cache
78
//
79
//`define OR1200_NO_DC
80
 
81
//
82
// Do not implement Insn cache
83
//
84
//`define OR1200_NO_IC
85
 
86
//
87
// Do not implement Data MMU
88
//
89
//`define OR1200_NO_DMMU
90
 
91
//
92
// Do not implement Insn MMU
93
//
94
//`define OR1200_NO_IMMU
95
 
96
//
97
// Select between ASIC optimized and generic multiplier
98
//
99
//`define OR1200_ASIC_MULTP2_32X32
100
`define OR1200_GENERIC_MULTP2_32X32
101
 
102
//
103
// Size/type of insn/data cache if implemented
104
//
105
// `define OR1200_IC_1W_512B
106
// `define OR1200_IC_1W_4KB
107
`define OR1200_IC_1W_8KB
108
// `define OR1200_DC_1W_4KB
109
`define OR1200_DC_1W_8KB
110
 
111
`else
112
 
113
 
114
/////////////////////////////////////////////////////////
115
//
116
// Typical configuration for an FPGA
117
//
118
 
119
//
120
// Target FPGA memories
121
//
122
//`define OR1200_ALTERA_LPM
123
//`define OR1200_XILINX_RAMB16
124
//`define OR1200_XILINX_RAMB4
125
//`define OR1200_XILINX_RAM32X1D
126
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
127
// Generic models should infer RAM blocks at synthesis time (not only effects 
128
// single port ram.)
129
`define OR1200_GENERIC
130
 
131
//
132
// Do not implement Data cache
133
//
134
//`define OR1200_NO_DC
135
 
136
//
137
// Do not implement Insn cache
138
//
139
//`define OR1200_NO_IC
140
 
141
//
142
// Do not implement Data MMU
143
//
144
//`define OR1200_NO_DMMU
145
 
146
//
147
// Do not implement Insn MMU
148
//
149
//`define OR1200_NO_IMMU
150
 
151
//
152
// Select between ASIC and generic multiplier
153
//
154
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
155
//
156
//`define OR1200_ASIC_MULTP2_32X32
157
`define OR1200_GENERIC_MULTP2_32X32
158
 
159
//
160
// Size/type of insn/data cache if implemented
161
// (consider available FPGA memory resources)
162
//
163
//`define OR1200_IC_1W_512B
164
//`define OR1200_IC_1W_4KB
165
`define OR1200_IC_1W_8KB
166
//`define OR1200_DC_1W_4KB
167
`define OR1200_DC_1W_8KB
168
 
169
`endif
170
 
171
 
172
//////////////////////////////////////////////////////////
173
//
174
// Do not change below unless you know what you are doing
175
//
176
 
177
//
178
// Reset active low
179
//
180
//`define OR1200_RST_ACT_LOW
181
 
182
//
183
// Enable RAM BIST
184
//
185
// At the moment this only works for Virtual Silicon
186
// single port RAMs. For other RAMs it has not effect.
187
// Special wrapper for VS RAMs needs to be provided
188
// with scan flops to facilitate bist scan.
189
//
190
//`define OR1200_BIST
191
 
192
//
193
// Register OR1200 WISHBONE outputs
194
// (must be defined/enabled)
195
//
196
`define OR1200_REGISTERED_OUTPUTS
197
 
198
//
199
// Register OR1200 WISHBONE inputs
200
//
201
// (must be undefined/disabled)
202
//
203
//`define OR1200_REGISTERED_INPUTS
204
 
205
//
206
// Disable bursts if they are not supported by the
207
// memory subsystem (only affect cache line fill)
208
//
209
//`define OR1200_NO_BURSTS
210
//
211
 
212
//
213
// WISHBONE retry counter range
214
//
215
// 2^value range for retry counter. Retry counter
216
// is activated whenever *wb_rty_i is asserted and
217
// until retry counter expires, corresponding
218
// WISHBONE interface is deactivated.
219
//
220
// To disable retry counters and *wb_rty_i all together,
221
// undefine this macro.
222
//
223
//`define OR1200_WB_RETRY 7
224
 
225
//
226
// WISHBONE Consecutive Address Burst
227
//
228
// This was used prior to WISHBONE B3 specification
229
// to identify bursts. It is no longer needed but
230
// remains enabled for compatibility with old designs.
231
//
232
// To remove *wb_cab_o ports undefine this macro.
233
//
234
//`define OR1200_WB_CAB
235
 
236
//
237
// WISHBONE B3 compatible interface
238
//
239
// This follows the WISHBONE B3 specification.
240
// It is not enabled by default because most
241
// designs still don't use WB b3.
242
//
243
// To enable *wb_cti_o/*wb_bte_o ports,
244
// define this macro.
245
//
246
`define OR1200_WB_B3
247
 
248
//
249
// LOG all WISHBONE accesses
250
//
251
`define OR1200_LOG_WB_ACCESS
252
 
253
//
254
// Enable additional synthesis directives if using
255
// _Synopsys_ synthesis tool
256
//
257
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
258
 
259
//
260
// Enables default statement in some case blocks
261
// and disables Synopsys synthesis directive full_case
262
//
263
// By default it is enabled. When disabled it
264
// can increase clock frequency.
265
//
266
`define OR1200_CASE_DEFAULT
267
 
268
//
269
// Operand width / register file address width
270
//
271
// (DO NOT CHANGE)
272
//
273
`define OR1200_OPERAND_WIDTH            32
274
`define OR1200_REGFILE_ADDR_WIDTH       5
275
 
276
//
277
// l.add/l.addi/l.and and optional l.addc/l.addic
278
// also set (compare) flag when result of their
279
// operation equals zero
280
//
281
// At the time of writing this, default or32
282
// C/C++ compiler doesn't generate code that
283
// would benefit from this optimization.
284
//
285
// By default this optimization is disabled to
286
// save area.
287
//
288
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
289
 
290
//
291
// Implement l.addc/l.addic instructions
292
//
293
// By default implementation of l.addc/l.addic
294
// instructions is enabled in case you need them.
295
// If you don't use them, then disable implementation
296
// to save area.
297
//
298
//`define OR1200_IMPL_ADDC
299
 
300
//
301
// Implement l.sub instruction
302
//
303
// By default implementation of l.sub instructions
304
// is enabled to be compliant with the simulator.
305
// If you don't use carry bit, then disable
306
// implementation to save area.
307
//
308
`define OR1200_IMPL_SUB
309
 
310
//
311
// Implement carry bit SR[CY]
312
//
313
//
314
// By default implementation of SR[CY] is enabled
315
// to be compliant with the simulator. However SR[CY]
316
// is explicitly only used by l.addc/l.addic/l.sub
317
// instructions and if these three insns are not
318
// implemented there is not much point having SR[CY].
319
//
320
//`define OR1200_IMPL_CY
321
 
322
//
323
// Implement rotate in the ALU
324
//
325
// At the time of writing this, or32
326
// C/C++ compiler doesn't generate rotate
327
// instructions. However or32 assembler
328
// can assemble code that uses rotate insn.
329
// This means that rotate instructions
330
// must be used manually inserted.
331
//
332
// By default implementation of rotate
333
// is disabled to save area and increase
334
// clock frequency.
335
//
336
//`define OR1200_IMPL_ALU_ROTATE
337
 
338
//
339
// Type of ALU compare to implement
340
//
341
// Try either one to find what yields
342
// higher clock frequencyin your case.
343
//
344
//`define OR1200_IMPL_ALU_COMP1
345
`define OR1200_IMPL_ALU_COMP2
346
 
347
//
348
// Implement Find First/Last '1'
349
//
350
`define OR1200_IMPL_ALU_FFL1
351
 
352
//
353
// Implement multiplier
354
//
355
// By default multiplier is implemented
356
//
357
`define OR1200_MULT_IMPLEMENTED
358
 
359
//
360
// Implement multiply-and-accumulate
361
//
362
// By default MAC is implemented. To
363
// implement MAC, multiplier needs to be
364
// implemented.
365
//
366
`define OR1200_MAC_IMPLEMENTED
367
 
368
//
369
// Implement optional l.div/l.divu instructions
370
//
371
// By default divide instructions are not implemented
372
// to save area and increase clock frequency. or32 C/C++
373
// compiler can use soft library for division.
374
//
375
// To implement divide, both multiplier and MAC needs to be implemented.
376
//
377
`define OR1200_DIV_IMPLEMENTED
378
 
379
//
380
// Low power, slower multiplier
381
//
382
// Select between low-power (larger) multiplier
383
// and faster multiplier. The actual difference
384
// is only AND logic that prevents distribution
385
// of operands into the multiplier when instruction
386
// in execution is not multiply instruction
387
//
388
//`define OR1200_LOWPWR_MULT
389
 
390
//
391
// Implement HW Single Precision FPU
392
//
393
`define OR1200_FPU_IMPLEMENTED
394
 
395
 
396
//
397
// Clock ratio RISC clock versus WB clock
398
//
399
// If you plan to run WB:RISC clock fixed to 1:1, disable
400
// both defines
401
//
402
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
403
// and use clmode to set ratio
404
//
405
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
406
// clmode to set ratio
407
//
408
//`define OR1200_CLKDIV_2_SUPPORTED
409
//`define OR1200_CLKDIV_4_SUPPORTED
410
 
411
//
412
// Type of register file RAM
413
//
414
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
415
//`define OR1200_RFRAM_TWOPORT
416
//
417
// Memory macro dual port (see or1200_dpram.v)
418
`define OR1200_RFRAM_DUALPORT
419
 
420
//
421
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
422
//`define OR1200_RFRAM_GENERIC
423
//  Generic register file supports - 16 registers 
424
`ifdef OR1200_RFRAM_GENERIC
425
//    `define OR1200_RFRAM_16REG
426
`endif
427
 
428
//
429
// Type of mem2reg aligner to implement.
430
//
431
// Once OR1200_IMPL_MEM2REG2 yielded faster
432
// circuit, however with today tools it will
433
// most probably give you slower circuit.
434
//
435
`define OR1200_IMPL_MEM2REG1
436
//`define OR1200_IMPL_MEM2REG2
437
 
438
//
439
// Reset value and event
440
//
441
`ifdef OR1200_RST_ACT_LOW
442
  `define OR1200_RST_VALUE      (1'b0)
443
  `define OR1200_RST_EVENT      negedge
444
`else
445
  `define OR1200_RST_VALUE      (1'b1)
446
  `define OR1200_RST_EVENT      posedge
447
`endif
448
 
449
//
450
// ALUOPs
451
//
452
`define OR1200_ALUOP_WIDTH      4
453
`define OR1200_ALUOP_NOP        4'd4
454
/* Order defined by arith insns that have two source operands both in regs
455
   (see binutils/include/opcode/or32.h) */
456
`define OR1200_ALUOP_ADD        4'd0
457
`define OR1200_ALUOP_ADDC       4'd1
458
`define OR1200_ALUOP_SUB        4'd2
459
`define OR1200_ALUOP_AND        4'd3
460
`define OR1200_ALUOP_OR         4'd4
461
`define OR1200_ALUOP_XOR        4'd5
462
`define OR1200_ALUOP_MUL        4'd6
463
`define OR1200_ALUOP_CUST5      4'd7
464
`define OR1200_ALUOP_SHROT      4'd8
465
`define OR1200_ALUOP_DIV        4'd9
466
`define OR1200_ALUOP_DIVU       4'd10
467
/* Order not specifically defined. */
468
`define OR1200_ALUOP_IMM        4'd11
469
`define OR1200_ALUOP_MOVHI      4'd12
470
`define OR1200_ALUOP_COMP       4'd13
471
`define OR1200_ALUOP_MTSR       4'd14
472
`define OR1200_ALUOP_MFSR       4'd15
473
`define OR1200_ALUOP_CMOV       4'd14
474
`define OR1200_ALUOP_FFL1       4'd15
475
 
476
 
477
// ALU instructions second opcode field (previously multicycle field in 
478
// machine word)
479
`define OR1200_ALUOP2_POS               9:8
480
`define OR1200_ALUOP2_WIDTH     2
481
 
482
 
483
//
484
// MACOPs
485
//
486
`define OR1200_MACOP_WIDTH      3
487
`define OR1200_MACOP_NOP        3'b000
488
`define OR1200_MACOP_MAC        3'b001
489
`define OR1200_MACOP_MSB        3'b010
490
 
491
//
492
// Shift/rotate ops
493
//
494
`define OR1200_SHROTOP_WIDTH    2
495
`define OR1200_SHROTOP_NOP      2'd0
496
`define OR1200_SHROTOP_SLL      2'd0
497
`define OR1200_SHROTOP_SRL      2'd1
498
`define OR1200_SHROTOP_SRA      2'd2
499
`define OR1200_SHROTOP_ROR      2'd3
500
 
501
// Execution cycles per instruction
502
`define OR1200_MULTICYCLE_WIDTH 3
503
`define OR1200_ONE_CYCLE                3'd0
504
`define OR1200_TWO_CYCLES               3'd1
505
 
506
// Execution control which will "wait on" a module to finish
507
`define OR1200_WAIT_ON_WIDTH 2
508
`define OR1200_WAIT_ON_FPU `OR1200_WAIT_ON_WIDTH'd1
509
`define OR1200_WAIT_ON_MTSPR `OR1200_WAIT_ON_WIDTH'd2
510
 
511
// Operand MUX selects
512
`define OR1200_SEL_WIDTH                2
513
`define OR1200_SEL_RF                   2'd0
514
`define OR1200_SEL_IMM                  2'd1
515
`define OR1200_SEL_EX_FORW              2'd2
516
`define OR1200_SEL_WB_FORW              2'd3
517
 
518
//
519
// BRANCHOPs
520
//
521
`define OR1200_BRANCHOP_WIDTH           3
522
`define OR1200_BRANCHOP_NOP             3'd0
523
`define OR1200_BRANCHOP_J               3'd1
524
`define OR1200_BRANCHOP_JR              3'd2
525
`define OR1200_BRANCHOP_BAL             3'd3
526
`define OR1200_BRANCHOP_BF              3'd4
527
`define OR1200_BRANCHOP_BNF             3'd5
528
`define OR1200_BRANCHOP_RFE             3'd6
529
 
530
//
531
// LSUOPs
532
//
533
// Bit 0: sign extend
534
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
535
// Bit 3: 0 load, 1 store
536
`define OR1200_LSUOP_WIDTH              4
537
`define OR1200_LSUOP_NOP                4'b0000
538
`define OR1200_LSUOP_LBZ                4'b0010
539
`define OR1200_LSUOP_LBS                4'b0011
540
`define OR1200_LSUOP_LHZ                4'b0100
541
`define OR1200_LSUOP_LHS                4'b0101
542
`define OR1200_LSUOP_LWZ                4'b0110
543
`define OR1200_LSUOP_LWS                4'b0111
544
`define OR1200_LSUOP_LD                 4'b0001
545
`define OR1200_LSUOP_SD                 4'b1000
546
`define OR1200_LSUOP_SB                 4'b1010
547
`define OR1200_LSUOP_SH                 4'b1100
548
`define OR1200_LSUOP_SW                 4'b1110
549
 
550
// Number of bits of load/store EA precalculated in ID stage
551
// for balancing ID and EX stages.
552
//
553
// Valid range: 2,3,...,30,31
554
`define OR1200_LSUEA_PRECALC            2
555
 
556
// FETCHOPs
557
`define OR1200_FETCHOP_WIDTH            1
558
`define OR1200_FETCHOP_NOP              1'b0
559
`define OR1200_FETCHOP_LW               1'b1
560
 
561
//
562
// Register File Write-Back OPs
563
//
564
// Bit 0: register file write enable
565
// Bits 3-1: write-back mux selects
566
//
567
`define OR1200_RFWBOP_WIDTH             4
568
`define OR1200_RFWBOP_NOP               4'b0000
569
`define OR1200_RFWBOP_ALU               3'b000
570
`define OR1200_RFWBOP_LSU               3'b001
571
`define OR1200_RFWBOP_SPRS              3'b010
572
`define OR1200_RFWBOP_LR                3'b011
573
`define OR1200_RFWBOP_FPU               3'b100
574
 
575
// Compare instructions
576
`define OR1200_COP_SFEQ       3'b000
577
`define OR1200_COP_SFNE       3'b001
578
`define OR1200_COP_SFGT       3'b010
579
`define OR1200_COP_SFGE       3'b011
580
`define OR1200_COP_SFLT       3'b100
581
`define OR1200_COP_SFLE       3'b101
582
`define OR1200_COP_X          3'b111
583
`define OR1200_SIGNED_COMPARE 'd3
584
`define OR1200_COMPOP_WIDTH     4
585
 
586
//
587
// FP OPs
588
//
589
// MSbit indicates FPU operation valid
590
//
591
`define OR1200_FPUOP_WIDTH      8
592
// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles
593
`define OR1200_FPUOP_CYCLES 3'd4
594
// FP instruction is double precision if bit 4 is set. We're a 32-bit 
595
// implementation thus do not support double precision FP 
596
`define OR1200_FPUOP_DOUBLE_BIT 4
597
`define OR1200_FPUOP_ADD  8'b0000_0000
598
`define OR1200_FPUOP_SUB  8'b0000_0001
599
`define OR1200_FPUOP_MUL  8'b0000_0010
600
`define OR1200_FPUOP_DIV  8'b0000_0011
601
`define OR1200_FPUOP_ITOF 8'b0000_0100
602
`define OR1200_FPUOP_FTOI 8'b0000_0101
603
`define OR1200_FPUOP_REM  8'b0000_0110
604
`define OR1200_FPUOP_RESERVED  8'b0000_0111
605
// FP Compare instructions
606
`define OR1200_FPCOP_SFEQ 8'b0000_1000
607
`define OR1200_FPCOP_SFNE 8'b0000_1001
608
`define OR1200_FPCOP_SFGT 8'b0000_1010
609
`define OR1200_FPCOP_SFGE 8'b0000_1011
610
`define OR1200_FPCOP_SFLT 8'b0000_1100
611
`define OR1200_FPCOP_SFLE 8'b0000_1101
612
 
613
//
614
// TAGs for instruction bus
615
//
616
`define OR1200_ITAG_IDLE        4'h0    // idle bus
617
`define OR1200_ITAG_NI          4'h1    // normal insn
618
`define OR1200_ITAG_BE          4'hb    // Bus error exception
619
`define OR1200_ITAG_PE          4'hc    // Page fault exception
620
`define OR1200_ITAG_TE          4'hd    // TLB miss exception
621
 
622
//
623
// TAGs for data bus
624
//
625
`define OR1200_DTAG_IDLE        4'h0    // idle bus
626
`define OR1200_DTAG_ND          4'h1    // normal data
627
`define OR1200_DTAG_AE          4'ha    // Alignment exception
628
`define OR1200_DTAG_BE          4'hb    // Bus error exception
629
`define OR1200_DTAG_PE          4'hc    // Page fault exception
630
`define OR1200_DTAG_TE          4'hd    // TLB miss exception
631
 
632
 
633
//////////////////////////////////////////////
634
//
635
// ORBIS32 ISA specifics
636
//
637
 
638
// SHROT_OP position in machine word
639
`define OR1200_SHROTOP_POS              7:6
640
 
641
//
642
// Instruction opcode groups (basic)
643
//
644
`define OR1200_OR32_J                 6'b000000
645
`define OR1200_OR32_JAL               6'b000001
646
`define OR1200_OR32_BNF               6'b000011
647
`define OR1200_OR32_BF                6'b000100
648
`define OR1200_OR32_NOP               6'b000101
649
`define OR1200_OR32_MOVHI             6'b000110
650
`define OR1200_OR32_XSYNC             6'b001000
651
`define OR1200_OR32_RFE               6'b001001
652
/* */
653
`define OR1200_OR32_JR                6'b010001
654
`define OR1200_OR32_JALR              6'b010010
655
`define OR1200_OR32_MACI              6'b010011
656
/* */
657
`define OR1200_OR32_LWZ               6'b100001
658
`define OR1200_OR32_LBZ               6'b100011
659
`define OR1200_OR32_LBS               6'b100100
660
`define OR1200_OR32_LHZ               6'b100101
661
`define OR1200_OR32_LHS               6'b100110
662
`define OR1200_OR32_ADDI              6'b100111
663
`define OR1200_OR32_ADDIC             6'b101000
664
`define OR1200_OR32_ANDI              6'b101001
665
`define OR1200_OR32_ORI               6'b101010
666
`define OR1200_OR32_XORI              6'b101011
667
`define OR1200_OR32_MULI              6'b101100
668
`define OR1200_OR32_MFSPR             6'b101101
669
`define OR1200_OR32_SH_ROTI           6'b101110
670
`define OR1200_OR32_SFXXI             6'b101111
671
/* */
672
`define OR1200_OR32_MTSPR             6'b110000
673
`define OR1200_OR32_MACMSB            6'b110001
674
`define OR1200_OR32_FLOAT             6'b110010
675
/* */
676
`define OR1200_OR32_SW                6'b110101
677
`define OR1200_OR32_SB                6'b110110
678
`define OR1200_OR32_SH                6'b110111
679
`define OR1200_OR32_ALU               6'b111000
680
`define OR1200_OR32_SFXX              6'b111001
681
//`define OR1200_OR32_CUST5             6'b111100
682
 
683
 
684
/////////////////////////////////////////////////////
685
//
686
// Exceptions
687
//
688
 
689
//
690
// Exception vectors per OR1K architecture:
691
// 0xPPPPP100 - reset
692
// 0xPPPPP200 - bus error
693
// ... etc
694
// where P represents exception prefix.
695
//
696
// Exception vectors can be customized as per
697
// the following formula:
698
// 0xPPPPPNVV - exception N
699
//
700
// P represents exception prefix
701
// N represents exception N
702
// VV represents length of the individual vector space,
703
//   usually it is 8 bits wide and starts with all bits zero
704
//
705
 
706
//
707
// PPPPP and VV parts
708
//
709
// Sum of these two defines needs to be 28
710
//
711
`define OR1200_EXCEPT_EPH0_P    20'h00000
712
`define OR1200_EXCEPT_EPH1_P    20'hF0000
713
`define OR1200_EXCEPT_V             8'h00
714
 
715
//
716
// N part width
717
//
718
`define OR1200_EXCEPT_WIDTH 4
719
 
720
//
721
// Definition of exception vectors
722
//
723
// To avoid implementation of a certain exception,
724
// simply comment out corresponding line
725
//
726
`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf
727
`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he
728
`define OR1200_EXCEPT_FLOAT             `OR1200_EXCEPT_WIDTH'hd
729
`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc
730
`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb
731
`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha
732
`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9
733
`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8
734
`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7
735
`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6
736
`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5
737
`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4
738
`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3
739
`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2
740
`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1
741
`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0
742
 
743
 
744
/////////////////////////////////////////////////////
745
//
746
// SPR groups
747
//
748
 
749
// Bits that define the group
750
`define OR1200_SPR_GROUP_BITS   15:11
751
 
752
// Width of the group bits
753
`define OR1200_SPR_GROUP_WIDTH  5
754
 
755
// Bits that define offset inside the group
756
`define OR1200_SPR_OFS_BITS 10:0
757
 
758
// List of groups
759
`define OR1200_SPR_GROUP_SYS    5'd00
760
`define OR1200_SPR_GROUP_DMMU   5'd01
761
`define OR1200_SPR_GROUP_IMMU   5'd02
762
`define OR1200_SPR_GROUP_DC     5'd03
763
`define OR1200_SPR_GROUP_IC     5'd04
764
`define OR1200_SPR_GROUP_MAC    5'd05
765
`define OR1200_SPR_GROUP_DU     5'd06
766
`define OR1200_SPR_GROUP_PM     5'd08
767
`define OR1200_SPR_GROUP_PIC    5'd09
768
`define OR1200_SPR_GROUP_TT     5'd10
769
`define OR1200_SPR_GROUP_FPU    5'd11
770
 
771
/////////////////////////////////////////////////////
772
//
773
// System group
774
//
775
 
776
//
777
// System registers
778
//
779
`define OR1200_SPR_CFGR         7'd0
780
`define OR1200_SPR_RF           6'd32   // 1024 >> 5
781
`define OR1200_SPR_NPC          11'd16
782
`define OR1200_SPR_SR           11'd17
783
`define OR1200_SPR_PPC          11'd18
784
`define OR1200_SPR_FPCSR        11'd20
785
`define OR1200_SPR_EPCR         11'd32
786
`define OR1200_SPR_EEAR         11'd48
787
`define OR1200_SPR_ESR          11'd64
788
 
789
//
790
// SR bits
791
//
792
`define OR1200_SR_WIDTH 17
793
`define OR1200_SR_SM   0
794
`define OR1200_SR_TEE  1
795
`define OR1200_SR_IEE  2
796
`define OR1200_SR_DCE  3
797
`define OR1200_SR_ICE  4
798
`define OR1200_SR_DME  5
799
`define OR1200_SR_IME  6
800
`define OR1200_SR_LEE  7
801
`define OR1200_SR_CE   8
802
`define OR1200_SR_F    9
803
`define OR1200_SR_CY   10       // Unused
804
`define OR1200_SR_OV   11       // Unused
805
`define OR1200_SR_OVE  12       // Unused
806
`define OR1200_SR_DSX  13       // Unused
807
`define OR1200_SR_EPH  14
808
`define OR1200_SR_FO   15
809
`define OR1200_SR_TED  16
810
`define OR1200_SR_CID  31:28    // Unimplemented
811
 
812
//
813
// Bits that define offset inside the group
814
//
815
`define OR1200_SPROFS_BITS 10:0
816
 
817
//
818
// Default Exception Prefix
819
//
820
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
821
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
822
//
823
`define OR1200_SR_EPH_DEF       1'b0
824
 
825
 
826
//
827
// FPCSR bits
828
//
829
`define OR1200_FPCSR_WIDTH 12
830
`define OR1200_FPCSR_FPEE  0
831
`define OR1200_FPCSR_RM    2:1
832
`define OR1200_FPCSR_OVF   3
833
`define OR1200_FPCSR_UNF   4
834
`define OR1200_FPCSR_SNF   5
835
`define OR1200_FPCSR_QNF   6
836
`define OR1200_FPCSR_ZF    7
837
`define OR1200_FPCSR_IXF   8
838
`define OR1200_FPCSR_IVF   9
839
`define OR1200_FPCSR_INF   10
840
`define OR1200_FPCSR_DZF   11
841
`define OR1200_FPCSR_RES   31:12
842
 
843
/////////////////////////////////////////////////////
844
//
845
// Power Management (PM)
846
//
847
 
848
// Define it if you want PM implemented
849
//`define OR1200_PM_IMPLEMENTED
850
 
851
// Bit positions inside PMR (don't change)
852
`define OR1200_PM_PMR_SDF 3:0
853
`define OR1200_PM_PMR_DME 4
854
`define OR1200_PM_PMR_SME 5
855
`define OR1200_PM_PMR_DCGE 6
856
`define OR1200_PM_PMR_UNUSED 31:7
857
 
858
// PMR offset inside PM group of registers
859
`define OR1200_PM_OFS_PMR 11'b0
860
 
861
// PM group
862
`define OR1200_SPRGRP_PM 5'd8
863
 
864
// Define if PMR can be read/written at any address inside PM group
865
`define OR1200_PM_PARTIAL_DECODING
866
 
867
// Define if reading PMR is allowed
868
`define OR1200_PM_READREGS
869
 
870
// Define if unused PMR bits should be zero
871
`define OR1200_PM_UNUSED_ZERO
872
 
873
 
874
/////////////////////////////////////////////////////
875
//
876
// Debug Unit (DU)
877
//
878
 
879
// Define it if you want DU implemented
880
`define OR1200_DU_IMPLEMENTED
881
 
882
//
883
// Define if you want HW Breakpoints
884
// (if HW breakpoints are not implemented
885
// only default software trapping is
886
// possible with l.trap insn - this is
887
// however already enough for use
888
// with or32 gdb)
889
//
890
//`define OR1200_DU_HWBKPTS
891
 
892
// Number of DVR/DCR pairs if HW breakpoints enabled
893
//      Comment / uncomment DU_DVRn / DU_DCRn pairs bellow according to this number ! 
894
//      DU_DVR0..DU_DVR7 should be uncommented for 8 DU_DVRDCR_PAIRS 
895
`define OR1200_DU_DVRDCR_PAIRS 8
896
 
897
// Define if you want trace buffer
898
//      (for now only available for Xilinx Virtex FPGAs)
899
//`define OR1200_DU_TB_IMPLEMENTED
900
 
901
 
902
//
903
// Address offsets of DU registers inside DU group
904
//
905
// To not implement a register, doq not define its address
906
//
907
`ifdef OR1200_DU_HWBKPTS
908
`define OR1200_DU_DVR0          11'd0
909
`define OR1200_DU_DVR1          11'd1
910
`define OR1200_DU_DVR2          11'd2
911
`define OR1200_DU_DVR3          11'd3
912
`define OR1200_DU_DVR4          11'd4
913
`define OR1200_DU_DVR5          11'd5
914
`define OR1200_DU_DVR6          11'd6
915
`define OR1200_DU_DVR7          11'd7
916
`define OR1200_DU_DCR0          11'd8
917
`define OR1200_DU_DCR1          11'd9
918
`define OR1200_DU_DCR2          11'd10
919
`define OR1200_DU_DCR3          11'd11
920
`define OR1200_DU_DCR4          11'd12
921
`define OR1200_DU_DCR5          11'd13
922
`define OR1200_DU_DCR6          11'd14
923
`define OR1200_DU_DCR7          11'd15
924
`endif
925
`define OR1200_DU_DMR1          11'd16
926
`ifdef OR1200_DU_HWBKPTS
927
`define OR1200_DU_DMR2          11'd17
928
`define OR1200_DU_DWCR0         11'd18
929
`define OR1200_DU_DWCR1         11'd19
930
`endif
931
`define OR1200_DU_DSR           11'd20
932
`define OR1200_DU_DRR           11'd21
933
`ifdef OR1200_DU_TB_IMPLEMENTED
934
`define OR1200_DU_TBADR         11'h0ff
935
`define OR1200_DU_TBIA          11'h1??
936
`define OR1200_DU_TBIM          11'h2??
937
`define OR1200_DU_TBAR          11'h3??
938
`define OR1200_DU_TBTS          11'h4??
939
`endif
940
 
941
// Position of offset bits inside SPR address
942
`define OR1200_DUOFS_BITS       10:0
943
 
944
// DCR bits
945
`define OR1200_DU_DCR_DP        0
946
`define OR1200_DU_DCR_CC        3:1
947
`define OR1200_DU_DCR_SC        4
948
`define OR1200_DU_DCR_CT        7:5
949
 
950
// DMR1 bits
951
`define OR1200_DU_DMR1_CW0      1:0
952
`define OR1200_DU_DMR1_CW1      3:2
953
`define OR1200_DU_DMR1_CW2      5:4
954
`define OR1200_DU_DMR1_CW3      7:6
955
`define OR1200_DU_DMR1_CW4      9:8
956
`define OR1200_DU_DMR1_CW5      11:10
957
`define OR1200_DU_DMR1_CW6      13:12
958
`define OR1200_DU_DMR1_CW7      15:14
959
`define OR1200_DU_DMR1_CW8      17:16
960
`define OR1200_DU_DMR1_CW9      19:18
961
`define OR1200_DU_DMR1_CW10     21:20
962
`define OR1200_DU_DMR1_ST       22
963
`define OR1200_DU_DMR1_BT       23
964
`define OR1200_DU_DMR1_DXFW     24
965
`define OR1200_DU_DMR1_ETE      25
966
 
967
// DMR2 bits
968
`define OR1200_DU_DMR2_WCE0     0
969
`define OR1200_DU_DMR2_WCE1     1
970
`define OR1200_DU_DMR2_AWTC     12:2
971
`define OR1200_DU_DMR2_WGB      23:13
972
 
973
// DWCR bits
974
`define OR1200_DU_DWCR_COUNT    15:0
975
`define OR1200_DU_DWCR_MATCH    31:16
976
 
977
// DSR bits
978
`define OR1200_DU_DSR_WIDTH     14
979
`define OR1200_DU_DSR_RSTE      0
980
`define OR1200_DU_DSR_BUSEE     1
981
`define OR1200_DU_DSR_DPFE      2
982
`define OR1200_DU_DSR_IPFE      3
983
`define OR1200_DU_DSR_TTE       4
984
`define OR1200_DU_DSR_AE        5
985
`define OR1200_DU_DSR_IIE       6
986
`define OR1200_DU_DSR_IE        7
987
`define OR1200_DU_DSR_DME       8
988
`define OR1200_DU_DSR_IME       9
989
`define OR1200_DU_DSR_RE        10
990
`define OR1200_DU_DSR_SCE       11
991
`define OR1200_DU_DSR_FPE       12
992
`define OR1200_DU_DSR_TE        13
993
 
994
// DRR bits
995
`define OR1200_DU_DRR_RSTE      0
996
`define OR1200_DU_DRR_BUSEE     1
997
`define OR1200_DU_DRR_DPFE      2
998
`define OR1200_DU_DRR_IPFE      3
999
`define OR1200_DU_DRR_TTE       4
1000
`define OR1200_DU_DRR_AE        5
1001
`define OR1200_DU_DRR_IIE       6
1002
`define OR1200_DU_DRR_IE        7
1003
`define OR1200_DU_DRR_DME       8
1004
`define OR1200_DU_DRR_IME       9
1005
`define OR1200_DU_DRR_RE        10
1006
`define OR1200_DU_DRR_SCE       11
1007
`define OR1200_DU_DRR_FPE       12
1008
`define OR1200_DU_DRR_TE        13
1009
 
1010
// Define if reading DU regs is allowed
1011
`define OR1200_DU_READREGS
1012
 
1013
// Define if unused DU registers bits should be zero
1014
`define OR1200_DU_UNUSED_ZERO
1015
 
1016
// Define if IF/LSU status is not needed by devel i/f
1017
`define OR1200_DU_STATUS_UNIMPLEMENTED
1018
 
1019
/////////////////////////////////////////////////////
1020
//
1021
// Programmable Interrupt Controller (PIC)
1022
//
1023
 
1024
// Define it if you want PIC implemented
1025
`define OR1200_PIC_IMPLEMENTED
1026
 
1027
// Define number of interrupt inputs (2-31)
1028
`define OR1200_PIC_INTS 31
1029
 
1030
// Address offsets of PIC registers inside PIC group
1031
`define OR1200_PIC_OFS_PICMR 2'd0
1032
`define OR1200_PIC_OFS_PICSR 2'd2
1033
 
1034
// Position of offset bits inside SPR address
1035
`define OR1200_PICOFS_BITS 1:0
1036
 
1037
// Define if you want these PIC registers to be implemented
1038
`define OR1200_PIC_PICMR
1039
`define OR1200_PIC_PICSR
1040
 
1041
// Define if reading PIC registers is allowed
1042
`define OR1200_PIC_READREGS
1043
 
1044
// Define if unused PIC register bits should be zero
1045
`define OR1200_PIC_UNUSED_ZERO
1046
 
1047
 
1048
/////////////////////////////////////////////////////
1049
//
1050
// Tick Timer (TT)
1051
//
1052
 
1053
// Define it if you want TT implemented
1054
`define OR1200_TT_IMPLEMENTED
1055
 
1056
// Address offsets of TT registers inside TT group
1057
`define OR1200_TT_OFS_TTMR 1'd0
1058
`define OR1200_TT_OFS_TTCR 1'd1
1059
 
1060
// Position of offset bits inside SPR group
1061
`define OR1200_TTOFS_BITS 0
1062
 
1063
// Define if you want these TT registers to be implemented
1064
`define OR1200_TT_TTMR
1065
`define OR1200_TT_TTCR
1066
 
1067
// TTMR bits
1068
`define OR1200_TT_TTMR_TP 27:0
1069
`define OR1200_TT_TTMR_IP 28
1070
`define OR1200_TT_TTMR_IE 29
1071
`define OR1200_TT_TTMR_M 31:30
1072
 
1073
// Define if reading TT registers is allowed
1074
`define OR1200_TT_READREGS
1075
 
1076
 
1077
//////////////////////////////////////////////
1078
//
1079
// MAC
1080
//
1081
`define OR1200_MAC_ADDR         0        // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
1082
`define OR1200_MAC_SPR_WE               // Define if MACLO/MACHI are SPR writable
1083
 
1084
//
1085
// Shift {MACHI,MACLO} into destination register when executing l.macrc
1086
//
1087
// According to architecture manual there is no shift, so default value is 0.
1088
// However the implementation has deviated in this from the arch manual and had
1089
// hard coded shift by 28 bits which is a useful optimization for MP3 decoding 
1090
// (if using libmad fixed point library). Shifts are no longer default setup, 
1091
// but if you need to remain backward compatible, define your shift bits, which
1092
// were normally
1093
// dest_GPR = {MACHI,MACLO}[59:28]
1094
`define OR1200_MAC_SHIFTBY      0        // 0 = According to arch manual, 28 = obsolete backward compatibility
1095
 
1096
 
1097
//////////////////////////////////////////////
1098
//
1099
// Data MMU (DMMU)
1100
//
1101
 
1102
//
1103
// Address that selects between TLB TR and MR
1104
//
1105
`define OR1200_DTLB_TM_ADDR     7
1106
 
1107
//
1108
// DTLBMR fields
1109
//
1110
`define OR1200_DTLBMR_V_BITS    0
1111
`define OR1200_DTLBMR_CID_BITS  4:1
1112
`define OR1200_DTLBMR_RES_BITS  11:5
1113
`define OR1200_DTLBMR_VPN_BITS  31:13
1114
 
1115
//
1116
// DTLBTR fields
1117
//
1118
`define OR1200_DTLBTR_CC_BITS   0
1119
`define OR1200_DTLBTR_CI_BITS   1
1120
`define OR1200_DTLBTR_WBC_BITS  2
1121
`define OR1200_DTLBTR_WOM_BITS  3
1122
`define OR1200_DTLBTR_A_BITS    4
1123
`define OR1200_DTLBTR_D_BITS    5
1124
`define OR1200_DTLBTR_URE_BITS  6
1125
`define OR1200_DTLBTR_UWE_BITS  7
1126
`define OR1200_DTLBTR_SRE_BITS  8
1127
`define OR1200_DTLBTR_SWE_BITS  9
1128
`define OR1200_DTLBTR_RES_BITS  11:10
1129
`define OR1200_DTLBTR_PPN_BITS  31:13
1130
 
1131
//
1132
// DTLB configuration
1133
//
1134
`define OR1200_DMMU_PS          13                                      // 13 for 8KB page size
1135
`define OR1200_DTLB_INDXW       6                                       // 6 for 64 entry DTLB  7 for 128 entries
1136
`define OR1200_DTLB_INDXL       `OR1200_DMMU_PS                         // 13                   13
1137
`define OR1200_DTLB_INDXH       `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1    // 18                   19
1138
`define OR1200_DTLB_INDX        `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL   // 18:13                19:13
1139
`define OR1200_DTLB_TAGW        32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS   // 13                   12
1140
`define OR1200_DTLB_TAGL        `OR1200_DTLB_INDXH+1                    // 19                   20
1141
`define OR1200_DTLB_TAG         31:`OR1200_DTLB_TAGL                    // 31:19                31:20
1142
`define OR1200_DTLBMRW          `OR1200_DTLB_TAGW+1                     // +1 because of V bit
1143
`define OR1200_DTLBTRW          32-`OR1200_DMMU_PS+5                    // +5 because of protection bits and CI
1144
 
1145
//
1146
// Cache inhibit while DMMU is not enabled/implemented
1147
//
1148
// cache inhibited 0GB-4GB              1'b1
1149
// cache inhibited 0GB-2GB              !dcpu_adr_i[31]
1150
// cache inhibited 0GB-1GB 2GB-3GB      !dcpu_adr_i[30]
1151
// cache inhibited 1GB-2GB 3GB-4GB      dcpu_adr_i[30]
1152
// cache inhibited 2GB-4GB (default)    dcpu_adr_i[31]
1153
// cached 0GB-4GB                       1'b0
1154
//
1155
`define OR1200_DMMU_CI                  dcpu_adr_i[31]
1156
 
1157
 
1158
//////////////////////////////////////////////
1159
//
1160
// Insn MMU (IMMU)
1161
//
1162
 
1163
//
1164
// Address that selects between TLB TR and MR
1165
//
1166
`define OR1200_ITLB_TM_ADDR     7
1167
 
1168
//
1169
// ITLBMR fields
1170
//
1171
`define OR1200_ITLBMR_V_BITS    0
1172
`define OR1200_ITLBMR_CID_BITS  4:1
1173
`define OR1200_ITLBMR_RES_BITS  11:5
1174
`define OR1200_ITLBMR_VPN_BITS  31:13
1175
 
1176
//
1177
// ITLBTR fields
1178
//
1179
`define OR1200_ITLBTR_CC_BITS   0
1180
`define OR1200_ITLBTR_CI_BITS   1
1181
`define OR1200_ITLBTR_WBC_BITS  2
1182
`define OR1200_ITLBTR_WOM_BITS  3
1183
`define OR1200_ITLBTR_A_BITS    4
1184
`define OR1200_ITLBTR_D_BITS    5
1185
`define OR1200_ITLBTR_SXE_BITS  6
1186
`define OR1200_ITLBTR_UXE_BITS  7
1187
`define OR1200_ITLBTR_RES_BITS  11:8
1188
`define OR1200_ITLBTR_PPN_BITS  31:13
1189
 
1190
//
1191
// ITLB configuration
1192
//
1193
`define OR1200_IMMU_PS          13                                      // 13 for 8KB page size
1194
`define OR1200_ITLB_INDXW       6                                       // 6 for 64 entry ITLB  7 for 128 entries
1195
`define OR1200_ITLB_INDXL       `OR1200_IMMU_PS                         // 13                   13
1196
`define OR1200_ITLB_INDXH       `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1    // 18                   19
1197
`define OR1200_ITLB_INDX        `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL   // 18:13                19:13
1198
`define OR1200_ITLB_TAGW        32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS   // 13                   12
1199
`define OR1200_ITLB_TAGL        `OR1200_ITLB_INDXH+1                    // 19                   20
1200
`define OR1200_ITLB_TAG         31:`OR1200_ITLB_TAGL                    // 31:19                31:20
1201
`define OR1200_ITLBMRW          `OR1200_ITLB_TAGW+1                     // +1 because of V bit
1202
`define OR1200_ITLBTRW          32-`OR1200_IMMU_PS+3                    // +3 because of protection bits and CI
1203
 
1204
//
1205
// Cache inhibit while IMMU is not enabled/implemented
1206
// Note: all combinations that use icpu_adr_i cause async loop
1207
//
1208
// cache inhibited 0GB-4GB              1'b1
1209
// cache inhibited 0GB-2GB              !icpu_adr_i[31]
1210
// cache inhibited 0GB-1GB 2GB-3GB      !icpu_adr_i[30]
1211
// cache inhibited 1GB-2GB 3GB-4GB      icpu_adr_i[30]
1212
// cache inhibited 2GB-4GB (default)    icpu_adr_i[31]
1213
// cached 0GB-4GB                       1'b0
1214
//
1215
`define OR1200_IMMU_CI                  1'b0
1216
 
1217
 
1218
/////////////////////////////////////////////////
1219
//
1220
// Insn cache (IC)
1221
//
1222
 
1223
// 3 for 8 bytes, 4 for 16 bytes etc
1224
`define OR1200_ICLS             4
1225
 
1226
//
1227
// IC configurations
1228
//
1229
`ifdef OR1200_IC_1W_512B
1230
`define OR1200_ICSIZE   9     // 512
1231
`define OR1200_ICINDX   `OR1200_ICSIZE-2 // 7
1232
`define OR1200_ICINDXH  `OR1200_ICSIZE-1 // 8
1233
`define OR1200_ICTAGL   `OR1200_ICINDXH+1 // 9
1234
`define OR1200_ICTAG    `OR1200_ICSIZE-`OR1200_ICLS // 5
1235
`define OR1200_ICTAG_W  24
1236
`endif
1237
`ifdef OR1200_IC_1W_4KB
1238
`define OR1200_ICSIZE                   12                      // 4096
1239
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 10
1240
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 11
1241
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 12
1242
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 8
1243
`define OR1200_ICTAG_W                  21
1244
`endif
1245
`ifdef OR1200_IC_1W_8KB
1246
`define OR1200_ICSIZE                   13                      // 8192
1247
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 11
1248
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 12
1249
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 13
1250
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 9
1251
`define OR1200_ICTAG_W                  20
1252
`endif
1253
 
1254
 
1255
/////////////////////////////////////////////////
1256
//
1257
// Data cache (DC)
1258
//
1259
 
1260
// 3 for 8 bytes, 4 for 16 bytes etc
1261
`define OR1200_DCLS             4
1262
 
1263
// Define to enable default behavior of cache as write through
1264
// Turning this off enabled write back statergy
1265
//
1266
`define OR1200_DC_WRITETHROUGH
1267
 
1268
// Define to enable stores from the stack not doing writethrough.
1269
// EXPERIMENTAL
1270
//`define OR1200_DC_NOSTACKWRITETHROUGH
1271
 
1272
// Data cache SPR definitions
1273
`define OR1200_SPRGRP_DC_ADR_WIDTH 3
1274
// Data cache group SPR addresses
1275
`define OR1200_SPRGRP_DC_DCCR           3'd0 // Not implemented
1276
`define OR1200_SPRGRP_DC_DCBPR          3'd1 // Not implemented
1277
`define OR1200_SPRGRP_DC_DCBFR          3'd2
1278
`define OR1200_SPRGRP_DC_DCBIR          3'd3
1279
`define OR1200_SPRGRP_DC_DCBWR          3'd4 // Not implemented
1280
`define OR1200_SPRGRP_DC_DCBLR          3'd5 // Not implemented
1281
 
1282
//
1283
// DC configurations
1284
//
1285
`ifdef OR1200_DC_1W_4KB
1286
`define OR1200_DCSIZE                   12                      // 4096
1287
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 10
1288
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 11
1289
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 12
1290
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 8
1291
`define OR1200_DCTAG_W                  21
1292
`endif
1293
`ifdef OR1200_DC_1W_8KB
1294
`define OR1200_DCSIZE                   13                      // 8192
1295
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 11
1296
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 12
1297
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 13
1298
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 9
1299
`define OR1200_DCTAG_W                  20
1300
`endif
1301
 
1302
 
1303
/////////////////////////////////////////////////
1304
//
1305
// Store buffer (SB)
1306
//
1307
 
1308
//
1309
// Store buffer
1310
//
1311
// It will improve performance by "caching" CPU stores
1312
// using store buffer. This is most important for function
1313
// prologues because DC can only work in write though mode
1314
// and all stores would have to complete external WB writes
1315
// to memory.
1316
// Store buffer is between DC and data BIU.
1317
// All stores will be stored into store buffer and immediately
1318
// completed by the CPU, even though actual external writes
1319
// will be performed later. As a consequence store buffer masks
1320
// all data bus errors related to stores (data bus errors
1321
// related to loads are delivered normally).
1322
// All pending CPU loads will wait until store buffer is empty to
1323
// ensure strict memory model. Right now this is necessary because
1324
// we don't make destinction between cached and cache inhibited
1325
// address space, so we simply empty store buffer until loads
1326
// can begin.
1327
//
1328
// It makes design a bit bigger, depending what is the number of
1329
// entries in SB FIFO. Number of entries can be changed further
1330
// down.
1331
//
1332
//`define OR1200_SB_IMPLEMENTED
1333
 
1334
//
1335
// Number of store buffer entries
1336
//
1337
// Verified number of entries are 4 and 8 entries
1338
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
1339
// always match 2**OR1200_SB_LOG.
1340
// To disable store buffer, undefine
1341
// OR1200_SB_IMPLEMENTED.
1342
//
1343
`define OR1200_SB_LOG           2       // 2 or 3
1344
`define OR1200_SB_ENTRIES       4       // 4 or 8
1345
 
1346
 
1347
/////////////////////////////////////////////////
1348
//
1349
// Quick Embedded Memory (QMEM)
1350
//
1351
 
1352
//
1353
// Quick Embedded Memory
1354
//
1355
// Instantiation of dedicated insn/data memory (RAM or ROM).
1356
// Insn fetch has effective throughput 1insn / clock cycle.
1357
// Data load takes two clock cycles / access, data store
1358
// takes 1 clock cycle / access (if there is no insn fetch)).
1359
// Memory instantiation is shared between insn and data,
1360
// meaning if insn fetch are performed, data load/store
1361
// performance will be lower.
1362
//
1363
// Main reason for QMEM is to put some time critical functions
1364
// into this memory and to have predictable and fast access
1365
// to these functions. (soft fpu, context switch, exception
1366
// handlers, stack, etc)
1367
//
1368
// It makes design a bit bigger and slower. QMEM sits behind
1369
// IMMU/DMMU so all addresses are physical (so the MMUs can be
1370
// used with QMEM and QMEM is seen by the CPU just like any other
1371
// memory in the system). IC/DC are sitting behind QMEM so the
1372
// whole design timing might be worse with QMEM implemented.
1373
//
1374
//`define OR1200_QMEM_IMPLEMENTED
1375
 
1376
//
1377
// Base address and mask of QMEM
1378
//
1379
// Base address defines first address of QMEM. Mask defines
1380
// QMEM range in address space. Actual size of QMEM is however
1381
// determined with instantiated RAM/ROM. However bigger
1382
// mask will reserve more address space for QMEM, but also
1383
// make design faster, while more tight mask will take
1384
// less address space but also make design slower. If
1385
// instantiated RAM/ROM is smaller than space reserved with
1386
// the mask, instatiated RAM/ROM will also be shadowed
1387
// at higher addresses in reserved space.
1388
//
1389
`define OR1200_QMEM_IADDR       32'h0080_0000
1390
`define OR1200_QMEM_IMASK       32'hfff0_0000 // Max QMEM size 1MB
1391
`define OR1200_QMEM_DADDR       32'h0080_0000
1392
`define OR1200_QMEM_DMASK       32'hfff0_0000 // Max QMEM size 1MB
1393
 
1394
//
1395
// QMEM interface byte-select capability
1396
//
1397
// To enable qmem_sel* ports, define this macro.
1398
//
1399
//`define OR1200_QMEM_BSEL
1400
 
1401
//
1402
// QMEM interface acknowledge
1403
//
1404
// To enable qmem_ack port, define this macro.
1405
//
1406
//`define OR1200_QMEM_ACK
1407
 
1408
/////////////////////////////////////////////////////
1409
//
1410
// VR, UPR and Configuration Registers
1411
//
1412
//
1413
// VR, UPR and configuration registers are optional. If 
1414
// implemented, operating system can automatically figure
1415
// out how to use the processor because it knows 
1416
// what units are available in the processor and how they
1417
// are configured.
1418
//
1419
// This section must be last in or1200_defines.v file so
1420
// that all units are already configured and thus
1421
// configuration registers are properly set.
1422
// 
1423
 
1424
// Define if you want configuration registers implemented
1425
`define OR1200_CFGR_IMPLEMENTED
1426
 
1427
// Define if you want full address decode inside SYS group
1428
`define OR1200_SYS_FULL_DECODE
1429
 
1430
// Offsets of VR, UPR and CFGR registers
1431
`define OR1200_SPRGRP_SYS_VR            4'h0
1432
`define OR1200_SPRGRP_SYS_UPR           4'h1
1433
`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2
1434
`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3
1435
`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4
1436
`define OR1200_SPRGRP_SYS_DCCFGR        4'h5
1437
`define OR1200_SPRGRP_SYS_ICCFGR        4'h6
1438
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
1439
 
1440
// VR fields
1441
`define OR1200_VR_REV_BITS              5:0
1442
`define OR1200_VR_RES1_BITS             15:6
1443
`define OR1200_VR_CFG_BITS              23:16
1444
`define OR1200_VR_VER_BITS              31:24
1445
 
1446
// VR values
1447
`define OR1200_VR_REV                   6'h08
1448
`define OR1200_VR_RES1                  10'h000
1449
`define OR1200_VR_CFG                   8'h00
1450
`define OR1200_VR_VER                   8'h12
1451
 
1452
// UPR fields
1453
`define OR1200_UPR_UP_BITS              0
1454
`define OR1200_UPR_DCP_BITS             1
1455
`define OR1200_UPR_ICP_BITS             2
1456
`define OR1200_UPR_DMP_BITS             3
1457
`define OR1200_UPR_IMP_BITS             4
1458
`define OR1200_UPR_MP_BITS              5
1459
`define OR1200_UPR_DUP_BITS             6
1460
`define OR1200_UPR_PCUP_BITS            7
1461
`define OR1200_UPR_PMP_BITS             8
1462
`define OR1200_UPR_PICP_BITS            9
1463
`define OR1200_UPR_TTP_BITS             10
1464
`define OR1200_UPR_FPP_BITS             11
1465
`define OR1200_UPR_RES1_BITS            23:12
1466
`define OR1200_UPR_CUP_BITS             31:24
1467
 
1468
// UPR values
1469
`define OR1200_UPR_UP                   1'b1
1470
`ifdef OR1200_NO_DC
1471
`define OR1200_UPR_DCP                  1'b0
1472
`else
1473
`define OR1200_UPR_DCP                  1'b1
1474
`endif
1475
`ifdef OR1200_NO_IC
1476
`define OR1200_UPR_ICP                  1'b0
1477
`else
1478
`define OR1200_UPR_ICP                  1'b1
1479
`endif
1480
`ifdef OR1200_NO_DMMU
1481
`define OR1200_UPR_DMP                  1'b0
1482
`else
1483
`define OR1200_UPR_DMP                  1'b1
1484
`endif
1485
`ifdef OR1200_NO_IMMU
1486
`define OR1200_UPR_IMP                  1'b0
1487
`else
1488
`define OR1200_UPR_IMP                  1'b1
1489
`endif
1490
`ifdef OR1200_MAC_IMPLEMENTED
1491
`define OR1200_UPR_MP                   1'b1
1492
`else
1493
`define OR1200_UPR_MP                   1'b0
1494
`endif
1495
`ifdef OR1200_DU_IMPLEMENTED
1496
`define OR1200_UPR_DUP                  1'b1
1497
`else
1498
`define OR1200_UPR_DUP                  1'b0
1499
`endif
1500
`define OR1200_UPR_PCUP                 1'b0    // Performance counters not present
1501
`ifdef OR1200_PM_IMPLEMENTED
1502
`define OR1200_UPR_PMP                  1'b1
1503
`else
1504
`define OR1200_UPR_PMP                  1'b0
1505
`endif
1506
`ifdef OR1200_PIC_IMPLEMENTED
1507
`define OR1200_UPR_PICP                 1'b1
1508
`else
1509
`define OR1200_UPR_PICP                 1'b0
1510
`endif
1511
`ifdef OR1200_TT_IMPLEMENTED
1512
`define OR1200_UPR_TTP                  1'b1
1513
`else
1514
`define OR1200_UPR_TTP                  1'b0
1515
`endif
1516
`ifdef OR1200_FPU_IMPLEMENTED
1517
`define OR1200_UPR_FPP                  1'b1
1518
`else
1519
`define OR1200_UPR_FPP                  1'b0
1520
`endif
1521
`define OR1200_UPR_RES1                 12'h000
1522
`define OR1200_UPR_CUP                  8'h00
1523
 
1524
// CPUCFGR fields
1525
`define OR1200_CPUCFGR_NSGF_BITS        3:0
1526
`define OR1200_CPUCFGR_HGF_BITS     4
1527
`define OR1200_CPUCFGR_OB32S_BITS       5
1528
`define OR1200_CPUCFGR_OB64S_BITS       6
1529
`define OR1200_CPUCFGR_OF32S_BITS       7
1530
`define OR1200_CPUCFGR_OF64S_BITS       8
1531
`define OR1200_CPUCFGR_OV64S_BITS       9
1532
`define OR1200_CPUCFGR_RES1_BITS        31:10
1533
 
1534
// CPUCFGR values
1535
`define OR1200_CPUCFGR_NSGF                 4'h0
1536
`ifdef OR1200_RFRAM_16REG
1537
    `define OR1200_CPUCFGR_HGF                  1'b1
1538
`else
1539
    `define OR1200_CPUCFGR_HGF                  1'b0
1540
`endif
1541
`define OR1200_CPUCFGR_OB32S            1'b1
1542
`define OR1200_CPUCFGR_OB64S            1'b0
1543
`ifdef OR1200_FPU_IMPLEMENTED
1544
 `define OR1200_CPUCFGR_OF32S           1'b1
1545
`else
1546
 `define OR1200_CPUCFGR_OF32S           1'b0
1547
`endif
1548
 
1549
`define OR1200_CPUCFGR_OF64S            1'b0
1550
`define OR1200_CPUCFGR_OV64S            1'b0
1551
`define OR1200_CPUCFGR_RES1             22'h000000
1552
 
1553
// DMMUCFGR fields
1554
`define OR1200_DMMUCFGR_NTW_BITS        1:0
1555
`define OR1200_DMMUCFGR_NTS_BITS        4:2
1556
`define OR1200_DMMUCFGR_NAE_BITS        7:5
1557
`define OR1200_DMMUCFGR_CRI_BITS        8
1558
`define OR1200_DMMUCFGR_PRI_BITS        9
1559
`define OR1200_DMMUCFGR_TEIRI_BITS      10
1560
`define OR1200_DMMUCFGR_HTR_BITS        11
1561
`define OR1200_DMMUCFGR_RES1_BITS       31:12
1562
 
1563
// DMMUCFGR values
1564
`ifdef OR1200_NO_DMMU
1565
`define OR1200_DMMUCFGR_NTW             2'h0    // Irrelevant
1566
`define OR1200_DMMUCFGR_NTS             3'h0    // Irrelevant
1567
`define OR1200_DMMUCFGR_NAE             3'h0    // Irrelevant
1568
`define OR1200_DMMUCFGR_CRI             1'b0    // Irrelevant
1569
`define OR1200_DMMUCFGR_PRI             1'b0    // Irrelevant
1570
`define OR1200_DMMUCFGR_TEIRI           1'b0    // Irrelevant
1571
`define OR1200_DMMUCFGR_HTR             1'b0    // Irrelevant
1572
`define OR1200_DMMUCFGR_RES1            20'h00000
1573
`else
1574
`define OR1200_DMMUCFGR_NTW             2'h0    // 1 TLB way
1575
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW       // Num TLB sets
1576
`define OR1200_DMMUCFGR_NAE             3'h0    // No ATB entries
1577
`define OR1200_DMMUCFGR_CRI             1'b0    // No control register
1578
`define OR1200_DMMUCFGR_PRI             1'b0    // No protection reg
1579
`define OR1200_DMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl.
1580
`define OR1200_DMMUCFGR_HTR             1'b0    // No HW TLB reload
1581
`define OR1200_DMMUCFGR_RES1            20'h00000
1582
`endif
1583
 
1584
// IMMUCFGR fields
1585
`define OR1200_IMMUCFGR_NTW_BITS        1:0
1586
`define OR1200_IMMUCFGR_NTS_BITS        4:2
1587
`define OR1200_IMMUCFGR_NAE_BITS        7:5
1588
`define OR1200_IMMUCFGR_CRI_BITS        8
1589
`define OR1200_IMMUCFGR_PRI_BITS        9
1590
`define OR1200_IMMUCFGR_TEIRI_BITS      10
1591
`define OR1200_IMMUCFGR_HTR_BITS        11
1592
`define OR1200_IMMUCFGR_RES1_BITS       31:12
1593
 
1594
// IMMUCFGR values
1595
`ifdef OR1200_NO_IMMU
1596
`define OR1200_IMMUCFGR_NTW             2'h0    // Irrelevant
1597
`define OR1200_IMMUCFGR_NTS             3'h0    // Irrelevant
1598
`define OR1200_IMMUCFGR_NAE             3'h0    // Irrelevant
1599
`define OR1200_IMMUCFGR_CRI             1'b0    // Irrelevant
1600
`define OR1200_IMMUCFGR_PRI             1'b0    // Irrelevant
1601
`define OR1200_IMMUCFGR_TEIRI           1'b0    // Irrelevant
1602
`define OR1200_IMMUCFGR_HTR             1'b0    // Irrelevant
1603
`define OR1200_IMMUCFGR_RES1            20'h00000
1604
`else
1605
`define OR1200_IMMUCFGR_NTW             2'h0    // 1 TLB way
1606
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW       // Num TLB sets
1607
`define OR1200_IMMUCFGR_NAE             3'h0    // No ATB entry
1608
`define OR1200_IMMUCFGR_CRI             1'b0    // No control reg
1609
`define OR1200_IMMUCFGR_PRI             1'b0    // No protection reg
1610
`define OR1200_IMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl
1611
`define OR1200_IMMUCFGR_HTR             1'b0    // No HW TLB reload
1612
`define OR1200_IMMUCFGR_RES1            20'h00000
1613
`endif
1614
 
1615
// DCCFGR fields
1616
`define OR1200_DCCFGR_NCW_BITS          2:0
1617
`define OR1200_DCCFGR_NCS_BITS          6:3
1618
`define OR1200_DCCFGR_CBS_BITS          7
1619
`define OR1200_DCCFGR_CWS_BITS          8
1620
`define OR1200_DCCFGR_CCRI_BITS         9
1621
`define OR1200_DCCFGR_CBIRI_BITS        10
1622
`define OR1200_DCCFGR_CBPRI_BITS        11
1623
`define OR1200_DCCFGR_CBLRI_BITS        12
1624
`define OR1200_DCCFGR_CBFRI_BITS        13
1625
`define OR1200_DCCFGR_CBWBRI_BITS       14
1626
`define OR1200_DCCFGR_RES1_BITS 31:15
1627
 
1628
// DCCFGR values
1629
`ifdef OR1200_NO_DC
1630
`define OR1200_DCCFGR_NCW               3'h0    // Irrelevant
1631
`define OR1200_DCCFGR_NCS               4'h0    // Irrelevant
1632
`define OR1200_DCCFGR_CBS               1'b0    // Irrelevant
1633
`define OR1200_DCCFGR_CWS               1'b0    // Irrelevant
1634
`define OR1200_DCCFGR_CCRI              1'b0    // Irrelevant
1635
`define OR1200_DCCFGR_CBIRI             1'b0    // Irrelevant
1636
`define OR1200_DCCFGR_CBPRI             1'b0    // Irrelevant
1637
`define OR1200_DCCFGR_CBLRI             1'b0    // Irrelevant
1638
`define OR1200_DCCFGR_CBFRI             1'b0    // Irrelevant
1639
`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
1640
`define OR1200_DCCFGR_RES1              17'h00000
1641
`else
1642
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
1643
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
1644
`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block
1645
`ifdef OR1200_DC_WRITETHROUGH
1646
 `define OR1200_DCCFGR_CWS              1'b0    // Write-through strategy
1647
`else
1648
 `define OR1200_DCCFGR_CWS              1'b1    // Write-back strategy
1649
`endif
1650
`define OR1200_DCCFGR_CCRI              1'b1    // Cache control reg impl.
1651
`define OR1200_DCCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1652
`define OR1200_DCCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1653
`define OR1200_DCCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1654
`define OR1200_DCCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1655
`ifdef OR1200_DC_WRITETHROUGH
1656
 `define OR1200_DCCFGR_CBWBRI           1'b0    // Cache block WB reg not impl.
1657
`else
1658
 `define OR1200_DCCFGR_CBWBRI           1'b1    // Cache block WB reg impl.
1659
`endif
1660
`define OR1200_DCCFGR_RES1              17'h00000
1661
`endif
1662
 
1663
// ICCFGR fields
1664
`define OR1200_ICCFGR_NCW_BITS          2:0
1665
`define OR1200_ICCFGR_NCS_BITS          6:3
1666
`define OR1200_ICCFGR_CBS_BITS          7
1667
`define OR1200_ICCFGR_CWS_BITS          8
1668
`define OR1200_ICCFGR_CCRI_BITS         9
1669
`define OR1200_ICCFGR_CBIRI_BITS        10
1670
`define OR1200_ICCFGR_CBPRI_BITS        11
1671
`define OR1200_ICCFGR_CBLRI_BITS        12
1672
`define OR1200_ICCFGR_CBFRI_BITS        13
1673
`define OR1200_ICCFGR_CBWBRI_BITS       14
1674
`define OR1200_ICCFGR_RES1_BITS 31:15
1675
 
1676
// ICCFGR values
1677
`ifdef OR1200_NO_IC
1678
`define OR1200_ICCFGR_NCW               3'h0    // Irrelevant
1679
`define OR1200_ICCFGR_NCS               4'h0    // Irrelevant
1680
`define OR1200_ICCFGR_CBS               1'b0    // Irrelevant
1681
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1682
`define OR1200_ICCFGR_CCRI              1'b0    // Irrelevant
1683
`define OR1200_ICCFGR_CBIRI             1'b0    // Irrelevant
1684
`define OR1200_ICCFGR_CBPRI             1'b0    // Irrelevant
1685
`define OR1200_ICCFGR_CBLRI             1'b0    // Irrelevant
1686
`define OR1200_ICCFGR_CBFRI             1'b0    // Irrelevant
1687
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1688
`define OR1200_ICCFGR_RES1              17'h00000
1689
`else
1690
`define OR1200_ICCFGR_NCW               3'h0    // 1 cache way
1691
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)       // Num cache sets
1692
`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1  // 16 byte cache block
1693
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1694
`define OR1200_ICCFGR_CCRI              1'b1    // Cache control reg impl.
1695
`define OR1200_ICCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1696
`define OR1200_ICCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1697
`define OR1200_ICCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1698
`define OR1200_ICCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1699
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1700
`define OR1200_ICCFGR_RES1              17'h00000
1701
`endif
1702
 
1703
// DCFGR fields
1704
`define OR1200_DCFGR_NDP_BITS           3:0
1705
`define OR1200_DCFGR_WPCI_BITS          4
1706
`define OR1200_DCFGR_RES1_BITS          31:5
1707
 
1708
// DCFGR values
1709
`ifdef OR1200_DU_HWBKPTS
1710
`define OR1200_DCFGR_NDP                4'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
1711
`ifdef OR1200_DU_DWCR0
1712
`define OR1200_DCFGR_WPCI               1'b1
1713
`else
1714
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1715
`endif
1716
`else
1717
`define OR1200_DCFGR_NDP                4'h0    // Zero DVR/DCR pairs
1718
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1719
`endif
1720
`define OR1200_DCFGR_RES1               27'd0
1721
 
1722
///////////////////////////////////////////////////////////////////////////////
1723
// Boot Address Selection                                                    //
1724
// This only changes where the initial reset occurs. EPH setting is still    //
1725
// used to determine where vectors are located.                              //
1726
///////////////////////////////////////////////////////////////////////////////
1727
 // Boot from 0xf0000100
1728
//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
1729
//`define OR1200_BOOT_ADR 32'hf0000100
1730
// Boot from 0x100
1731
 `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
1732
 `define OR1200_BOOT_ADR 32'h00000100

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