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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [include/] [orpsoc-defines.v] - Blame information for rev 480

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1 412 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// orpsoc-defines                                               ////
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////                                                              ////
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//// Top level ORPSoC defines file                                ////
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////                                                              ////
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//// Included in toplevel and testbench                           ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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// Uncomment a `define BOARD_XYZ to configure design RTL for it.
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//
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// Mainly presets are for internal frequency settings, and what
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// external oscillator is expected (ordb1's were made with various
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// XTALs.)
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//
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//////////////////////////////////////////////////////////////////////
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 `define XILINX
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 `define XILINX_PLL
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 `define FPGA_BOARD_XILINX_ML501
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 `define IOCONFIG_XILINX_ML501
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 `define BOARD_CLOCK_PERIOD 5000 // 200MHz (pS accuracy for Xilinx sims.) 
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 `define JTAG_DEBUG
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// `define RAM_WB
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// `define XILINX_SSRAM
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 `define XILINX_DDR2
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 `define UART0
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 `define GPIO0
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 `define SPI0
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 `define I2C0
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 `define I2C1
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 `define ETH0
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 `define ETH0_PHY_RST
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// end of included module defines - keep this comment line here, scripts depend on it!!
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//
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// Arbiter defines
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//
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// Uncomment to register things through arbiter (hopefully quicker design)
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// Instruction bus arbiter
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//`define ARBITER_IBUS_REGISTERING
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`define ARBITER_IBUS_WATCHDOG
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// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles
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// This has to be kind of long, as DDR2 initialisation can take a little while
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// and after reset, and if this is too short we'll always get bus error.
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`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 20
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// Data bus arbiter
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//`define ARBITER_DBUS_REGISTERING
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`define ARBITER_DBUS_WATCHDOG
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// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles
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`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 20
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// Byte bus (peripheral bus) arbiter
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// Don't really need the watchdog here - the databus will pick it up
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//`define ARBITER_BYTEBUS_WATCHDOG
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// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles
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`define ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH 9
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