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julius |
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// memory controller parameters
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parameter BANK_WIDTH = 2; // # of memory bank addr bits
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parameter CKE_WIDTH = 2; // # of memory clock enable outputs
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parameter CLK_WIDTH = 2; // # of clock outputs
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parameter CLK_TYPE = "SINGLE_ENDED"; // # of clock type
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parameter COL_WIDTH = 10; // # of memory column bits
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parameter CS_NUM = 1; // # of separate memory chip selects
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parameter CS_WIDTH = 2; // # of total memory chip selects
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parameter CS_BITS = 0; // set to log2(CS_NUM) (rounded up)
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parameter DM_WIDTH = 8; // # of data mask bits
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parameter DQ_WIDTH = 64; // # of data width
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parameter DQ_PER_DQS = 8; // # of DQ data bits per strobe
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parameter DQS_WIDTH = 8; // # of DQS strobes
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parameter DQ_BITS = 6; // set to log2(DQS_WIDTH*DQ_PER_DQS)
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parameter DQS_BITS = 3; // set to log2(DQS_WIDTH)
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parameter HIGH_PERFORMANCE_MODE = "TRUE"; // Sets the performance mode for IODELAY elements
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parameter ODT_WIDTH = 2; // # of memory on-die term enables
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parameter ROW_WIDTH = 13; // # of memory row & # of addr bits
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// Can't change this!!
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parameter APPDATA_WIDTH = 128; // # of usr read/write data bus bits
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//parameter APPDATA_WIDTH = 32; // # of usr read/write data bus bits
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parameter ADDITIVE_LAT = 0; // additive write latency
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// Controller with cache!
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parameter BURST_LEN = 8; // burst length (in double words)
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// Old controller
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// parameter BURST_LEN = 4; // burst length (in double words)
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parameter BURST_TYPE = 0; // burst type (=0 seq; =1 interlved)
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parameter CAS_LAT = 4; // CAS latency
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parameter ECC_ENABLE = 0; // enable ECC (=1 enable)
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parameter MULTI_BANK_EN = 1; // enable bank management
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parameter TWO_T_TIME_EN = 1; // 2t timing for unbuffered dimms
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parameter ODT_TYPE = 1; // ODT (=0(none),=1(75),=2(150),=3(50))
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parameter REDUCE_DRV = 0; // reduced strength mem I/O (=1 yes)
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parameter REG_ENABLE = 0; // registered addr/ctrl (=1 yes)
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parameter TREFI_NS = 7800; // auto refresh interval (ns)
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parameter TRAS = 40000; // active->precharge delay
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parameter TRCD = 15000; // active->read/write delay
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parameter TRFC = 105000; // ref->ref, ref->active delay
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parameter TRP = 15000; // precharge->command delay
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parameter TRTP = 7500; // read->precharge delay
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parameter TWR = 15000; // used to determine wr->prech
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parameter TWTR = 7500; // write->read delay
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// Synthesize with this set to one if running post-synthesis simulations (don't have to wait forever for powerup delay on DDR2 controller)
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// parameter SIM_ONLY = 1; // = 0 to allow power up delay
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parameter SIM_ONLY = 0; // = 0 to allow power up delay
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parameter DEBUG_EN = 0; // Enable debug signals/controls
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parameter RST_ACT_LOW = 0; // =1 for active low reset, =0 for active high
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parameter DLL_FREQ_MODE = "HIGH"; // DCM Frequency range
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parameter CLK_PERIOD = 3750; // 266MHz Core/Mem clk period (in ps)
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// parameter CLK_PERIOD = 5000; // 200MHz Core/Mem clk period (in ps)
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