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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [lfsr/] [lfsr.v] - Blame information for rev 478

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1 412 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Linear feedback shift register with Wishbone interface       ////
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////                                                              ////
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//// Description                                                  ////
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//// Simple LFSR module (feedback hardcoded)                      ////
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//// Two accessible registers:                                    ////
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//// Address 0: LFSR Register (R/W)                               ////
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//// Address 4: Control register, active high, self resetting (WO)////
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////            Bit[0]: lfsr shift enable                         ////
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////            Bit[1]: lfsr reset                                ////
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////                                                              ////
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////  To Do:                                                      ////
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////        Perhaps make feedback parameterisable                 ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Julius Baxter, julius.baxter@orsoc.se                 ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module wb_lfsr( wb_clk, wb_rst, wb_adr_i, wb_dat_i, wb_cyc_i, wb_stb_i, wb_we_i,
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                wb_dat_o, wb_ack_o);
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   parameter width = 32;
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   parameter lfsr_rst_value = 32'b0011_0001_0000_1010;
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   input wb_clk;
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   input wb_rst;
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   input [2:0] wb_adr_i;
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   input [width-1:0] wb_dat_i;
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   input             wb_cyc_i, wb_stb_i, wb_we_i;
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   output [width-1:0] wb_dat_o;
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   output reg         wb_ack_o;
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   wire               wb_req;
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   assign wb_req = wb_stb_i & wb_cyc_i;
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   reg [width-1:0]    lfsr;
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   wire                   lfsr_feedback;
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   assign wb_dat_o = lfsr;
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   // Only 2 registers here, the lfsr itself and 
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   wire                   lfsr_sel;
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   assign lfsr_sel = !wb_adr_i[2];
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   wire                   lfsr_control_reg_sel;
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   assign lfsr_control_reg_sel = wb_adr_i[2];
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   // [0]: shift enable, [1]: reset
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   reg [1:0]               lfsr_control_reg;
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   wire                   lfsr_control_enable;
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   wire                   lfsr_control_rst;
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   // Load the control reg when required, 
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   always @(posedge wb_clk)
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     begin
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        if (wb_rst)
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          lfsr_control_reg <= 0;
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        else if (wb_req & wb_we_i & lfsr_control_reg_sel & wb_ack_o)
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          lfsr_control_reg <= wb_dat_i;
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        if (lfsr_control_reg[0])
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          lfsr_control_reg[0] <= 0;
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        if (lfsr_control_reg[1])
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          lfsr_control_reg[1] <= 0;
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     end // always @ (posedge wb_clk)
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   assign lfsr_control_enable = lfsr_control_reg[0];
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   assign lfsr_control_rst = lfsr_control_reg[1];
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   assign lfsr_feedback = !(((lfsr[27] ^ lfsr[13]) ^ lfsr[8]) ^ lfsr[5]);
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   always @(posedge wb_clk)
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     if (wb_rst)
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       lfsr <= lfsr_rst_value;
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     else if (lfsr_control_rst)
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       lfsr <= lfsr_rst_value;
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     else if (wb_req & wb_we_i & lfsr_sel & wb_ack_o) // Set lfsr
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       lfsr <= wb_dat_i;
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     else if (lfsr_control_enable)
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       lfsr <= {lfsr[width-2:0], lfsr_feedback};
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   always @(posedge wb_clk)
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     if (wb_rst)
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       wb_ack_o <= 0;
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     else if (wb_req & !wb_ack_o)
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       wb_ack_o <= 1;
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     else if (wb_ack_o)
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       wb_ack_o <= 0;
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endmodule // lfsr

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