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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [xilinx_ddr2/] [ddr2_idelay_ctrl.v] - Blame information for rev 412

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1 412 julius
//*****************************************************************************
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// DISCLAIMER OF LIABILITY
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//
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// This file contains proprietary and confidential information of
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// Xilinx, Inc. ("Xilinx"), that is distributed under a license
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// from Xilinx, and may be used, copied and/or disclosed only
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// pursuant to the terms of a valid license agreement with Xilinx.
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//
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// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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// does not warrant that functions included in the Materials will
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// meet the requirements of Licensee, or that the operation of the
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// Materials will be uninterrupted or error-free, or that defects
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// in the Materials will be corrected. Furthermore, Xilinx does
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// not warrant or make any representations regarding use, or the
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// results of the use, of the Materials in terms of correctness,
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// accuracy, reliability or otherwise.
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//
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// Xilinx products are not designed or intended to be fail-safe,
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// or for use in any application requiring fail-safe performance,
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// such as life-support or safety devices or systems, Class III
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// medical devices, nuclear facilities, applications related to
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// the deployment of airbags, or any other applications that could
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// lead to death, personal injury or severe property or
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// environmental damage (individually and collectively, "critical
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// applications"). Customer assumes the sole risk and liability
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// of any use of Xilinx products in critical applications,
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// subject only to applicable laws and regulations governing
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// limitations on product liability.
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//
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// Copyright 2006, 2007, 2008 Xilinx, Inc.
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// All rights reserved.
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//
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// This disclaimer and copyright notice must be retained as part
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// of this file at all times.
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//*****************************************************************************
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//   ____  ____
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//  /   /\/   /
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// /___/  \  /    Vendor: Xilinx
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// \   \   \/     Version: 3.0
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//  \   \         Application: MIG
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//  /   /         Filename: ddr2_idelay_ctrl.v
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// /___/   /\     Date Last Modified: $Date: 2008/12/23 14:26:00 $
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// \   \  /  \    Date Created: Wed Aug 16 2006
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//  \___\/\___\
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//
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//Device: Virtex-5
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//Design Name: DDR2
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//Purpose:
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//   This module instantiates the IDELAYCTRL primitive of the Virtex-5 device
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//   which continuously calibrates the IDELAY elements in the region in case of
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//   varying operating conditions. It takes a 200MHz clock as an input
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//Reference:
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//Revision History:
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//   Rev 1.1 - Parameter IODELAY_GRP added and constraint IODELAY_GROUP added
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//             on IOELAYCTRL primitive. Generate logic on IDELAYCTRL removed
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//             since tools will replicate idelactrl primitives.PK. 11/27/08
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//*****************************************************************************
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`timescale 1ns/1ps
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module ddr2_idelay_ctrl #
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  (
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   // Following parameters are for 72-bit RDIMM design (for ML561 Reference
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   // board design). Actual values may be different. Actual parameters values
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   // are passed from design top module ddr2_mig module. Please refer to
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   // the ddr2_mig module for actual values.
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   parameter IODELAY_GRP     = "IODELAY_MIG"
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   )
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  (
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   input  clk200,
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   input  rst200,
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   output idelay_ctrl_rdy
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   );
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  (* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl
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    (
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     .RDY(idelay_ctrl_rdy),
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     .REFCLK(clk200),
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     .RST(rst200)
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     );
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endmodule

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