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//*****************************************************************************

//   ____  ____

//  /   /\/   /

// /___/  \  /    Vendor: Xilinx

// \   \   \/     Version: 3.0

//  \   \         Application: MIG

//  /   /         Filename: ddr2_idelay_ctrl.v

// /___/   /\     Date Last Modified: $Date: 2008/12/23 14:26:00 $

// \   \  /  \    Date Created: Wed Aug 16 2006

//  \___\/\___\

//

//Device: Virtex-5

//Design Name: DDR2

//Purpose:

//   This module instantiates the IDELAYCTRL primitive of the Virtex-5 device

//   which continuously calibrates the IDELAY elements in the region in case of

//   varying operating conditions. It takes a 200MHz clock as an input

//Reference:

//Revision History:

//   Rev 1.1 - Parameter IODELAY_GRP added and constraint IODELAY_GROUP added

//             on IOELAYCTRL primitive. Generate logic on IDELAYCTRL removed

//             since tools will replicate idelactrl primitives.PK. 11/27/08

//*****************************************************************************

`timescale 1ns/1ps

module ddr2_idelay_ctrl #

  (

   // Following parameters are for 72-bit RDIMM design (for ML561 Reference

   // board design). Actual values may be different. Actual parameters values

   // are passed from design top module ddr2_mig module. Please refer to

   // the ddr2_mig module for actual values.

   parameter IODELAY_GRP     = "IODELAY_MIG"

   )

  (

   input  clk200,

   input  rst200,

   output idelay_ctrl_rdy

   );

  (* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl

    (

     .RDY(idelay_ctrl_rdy),

     .REFCLK(clk200),

     .RST(rst200)

     );

endmodule