OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [xilinx_ddr2/] [ddr2_infrastructure.v] - Blame information for rev 412

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 412 julius
//*****************************************************************************
2
// DISCLAIMER OF LIABILITY
3
//
4
// This file contains proprietary and confidential information of
5
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
6
// from Xilinx, and may be used, copied and/or disclosed only
7
// pursuant to the terms of a valid license agreement with Xilinx.
8
//
9
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
10
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
11
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
12
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
13
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
14
// does not warrant that functions included in the Materials will
15
// meet the requirements of Licensee, or that the operation of the
16
// Materials will be uninterrupted or error-free, or that defects
17
// in the Materials will be corrected. Furthermore, Xilinx does
18
// not warrant or make any representations regarding use, or the
19
// results of the use, of the Materials in terms of correctness,
20
// accuracy, reliability or otherwise.
21
//
22
// Xilinx products are not designed or intended to be fail-safe,
23
// or for use in any application requiring fail-safe performance,
24
// such as life-support or safety devices or systems, Class III
25
// medical devices, nuclear facilities, applications related to
26
// the deployment of airbags, or any other applications that could
27
// lead to death, personal injury or severe property or
28
// environmental damage (individually and collectively, "critical
29
// applications"). Customer assumes the sole risk and liability
30
// of any use of Xilinx products in critical applications,
31
// subject only to applicable laws and regulations governing
32
// limitations on product liability.
33
//
34
// Copyright 2006, 2007, 2008 Xilinx, Inc.
35
// All rights reserved.
36
//
37
// This disclaimer and copyright notice must be retained as part
38
// of this file at all times.
39
//*****************************************************************************
40
//   ____  ____
41
//  /   /\/   /
42
// /___/  \  /    Vendor: Xilinx
43
// \   \   \/     Version: 3.0
44
//  \   \         Application: MIG
45
//  /   /         Filename: ddr2_infrastructure.v
46
// /___/   /\     Date Last Modified: $Date: 2008/12/23 14:26:00 $
47
// \   \  /  \    Date Created: Wed Aug 16 2006
48
//  \___\/\___\
49
//
50
//Device: Virtex-5
51
//Design Name: DDR2
52
//Purpose:
53
//   Clock generation/distribution and reset synchronization
54
//Reference:
55
//Revision History:
56
//   Rev 1.1 - Parameter CLK_TYPE added and logic for  DIFFERENTIAL and
57
//             SINGLE_ENDED added. PK. 6/20/08
58
//   Rev 1.2 - Loacalparam CLK_GENERATOR added and logic for clocks generation
59
//             using PLL or DCM added as generic code. PK. 10/14/08
60
//*****************************************************************************
61
 
62
`timescale 1ns/1ps
63
 
64
module ddr2_infrastructure #
65
  (
66
   // Following parameters are for 72-bit RDIMM design (for ML561 Reference
67
   // board design). Actual values may be different. Actual parameters values
68
   // are passed from design top module ddr2_mig module. Please refer to
69
   // the ddr2_mig module for actual values.
70
   parameter CLK_PERIOD    = 3000,
71
   parameter CLK_TYPE      = "DIFFERENTIAL",
72
   parameter DLL_FREQ_MODE = "HIGH",
73
   parameter RST_ACT_LOW  = 1
74
   )
75
  (
76
   input  sys_clk_p,
77
   input  sys_clk_n,
78
   input  sys_clk,
79
   input  clk200_p,
80
   input  clk200_n,
81
   input  idly_clk_200,
82
   output clk0,
83
   output clk90,
84
   output clk200,
85
   output clkdiv0,
86
   input  sys_rst_n,
87
   input  idelay_ctrl_rdy,
88
   output rst0,
89
   output rst90,
90
   output rst200,
91
   output rstdiv0
92
   );
93
 
94
  // # of clock cycles to delay deassertion of reset. Needs to be a fairly
95
  // high number not so much for metastability protection, but to give time
96
  // for reset (i.e. stable clock cycles) to propagate through all state
97
  // machines and to all control signals (i.e. not all control signals have
98
  // resets, instead they rely on base state logic being reset, and the effect
99
  // of that reset propagating through the logic). Need this because we may not
100
  // be getting stable clock cycles while reset asserted (i.e. since reset
101
  // depends on PLL/DCM lock status)
102
  localparam RST_SYNC_NUM = 25;
103
  localparam CLK_PERIOD_NS = CLK_PERIOD / 1000.0;
104
  localparam CLK_PERIOD_INT = CLK_PERIOD/1000;
105
 
106
  // By default this Parameter (CLK_GENERATOR) value is "PLL". If this
107
  // Parameter is set to "PLL", PLL is used to generate the design clocks.
108
  // If this Parameter is set to "DCM",
109
  // DCM is used to generate the design clocks.
110
  localparam CLK_GENERATOR = "PLL";
111
 
112
  wire                       clk0_bufg;
113
  wire                       clk0_bufg_in;
114
  wire                       clk90_bufg;
115
  wire                       clk90_bufg_in;
116
  wire                       clk200_bufg;
117
  wire                       clk200_ibufg;
118
  wire                       clkdiv0_bufg;
119
  wire                       clkdiv0_bufg_in;
120
  wire                       clkfbout_clkfbin;
121
  wire                       locked;
122
  reg [RST_SYNC_NUM-1:0]     rst0_sync_r    /* synthesis syn_maxfan = 10 */;
123
  reg [RST_SYNC_NUM-1:0]     rst200_sync_r  /* synthesis syn_maxfan = 10 */;
124
  reg [RST_SYNC_NUM-1:0]     rst90_sync_r   /* synthesis syn_maxfan = 10 */;
125
  reg [(RST_SYNC_NUM/2)-1:0] rstdiv0_sync_r /* synthesis syn_maxfan = 10 */;
126
  wire                       rst_tmp;
127
  wire                       sys_clk_ibufg;
128
  wire                       sys_rst;
129
 
130
  assign sys_rst = RST_ACT_LOW ? ~sys_rst_n: sys_rst_n;
131
 
132
  assign clk0    = clk0_bufg;
133
  assign clk90   = clk90_bufg;
134
  assign clk200  = clk200_bufg;
135
  assign clkdiv0 = clkdiv0_bufg;
136
 
137
  generate
138
  if(CLK_TYPE == "DIFFERENTIAL") begin : DIFF_ENDED_CLKS_INST
139
    //***************************************************************************
140
    // Differential input clock input buffers
141
    //***************************************************************************
142
 
143
    IBUFGDS_LVPECL_25 SYS_CLK_INST
144
      (
145
       .I  (sys_clk_p),
146
       .IB (sys_clk_n),
147
       .O  (sys_clk_ibufg)
148
       );
149
 
150
    IBUFGDS_LVPECL_25 IDLY_CLK_INST
151
      (
152
       .I  (clk200_p),
153
       .IB (clk200_n),
154
       .O  (clk200_ibufg)
155
       );
156
 
157
  end/* else if(CLK_TYPE == "SINGLE_ENDED") begin : SINGLE_ENDED_CLKS_INST
158
    //**************************************************************************
159
    // Single ended input clock input buffers
160
    //**************************************************************************
161
 
162
    IBUFG SYS_CLK_INST
163
      (
164
       .I  (sys_clk),
165
       .O  (sys_clk_ibufg)
166
       );
167
 
168
    IBUFG IDLY_CLK_INST
169
      (
170
       .I  (idly_clk_200),
171
       .O  (clk200_ibufg)
172
       );
173
      // This is being instantiated inside another design. these signals are properly generated elsewhere -- jb
174
  end*/
175
  endgenerate
176
   assign sys_clk_ibufg = sys_clk;
177
   //assign idly_clk_200 = clk200_ibufg;
178
   assign clk200_bufg = idly_clk_200;
179
 
180
/*
181
  BUFG CLK_200_BUFG
182
    (
183
     .O (clk200_bufg),
184
     .I (clk200_ibufg)
185
     );
186
*/
187
  //***************************************************************************
188
  // Global clock generation and distribution
189
  //***************************************************************************
190
 
191
  generate
192
    if (CLK_GENERATOR == "PLL") begin : gen_pll_adv
193
      PLL_ADV #
194
        (
195
         .BANDWIDTH          ("OPTIMIZED"),
196
         .CLKIN1_PERIOD      (CLK_PERIOD_NS),
197
         .CLKIN2_PERIOD      (10.000),
198
         .CLKOUT0_DIVIDE     (CLK_PERIOD_INT),
199
         .CLKOUT1_DIVIDE     (CLK_PERIOD_INT),
200
         .CLKOUT2_DIVIDE     (CLK_PERIOD_INT*2),
201
         .CLKOUT3_DIVIDE     (1),
202
         .CLKOUT4_DIVIDE     (1),
203
         .CLKOUT5_DIVIDE     (1),
204
         .CLKOUT0_PHASE      (0.000),
205
         .CLKOUT1_PHASE      (90.000),
206
         .CLKOUT2_PHASE      (0.000),
207
         .CLKOUT3_PHASE      (0.000),
208
         .CLKOUT4_PHASE      (0.000),
209
         .CLKOUT5_PHASE      (0.000),
210
         .CLKOUT0_DUTY_CYCLE (0.500),
211
         .CLKOUT1_DUTY_CYCLE (0.500),
212
         .CLKOUT2_DUTY_CYCLE (0.500),
213
         .CLKOUT3_DUTY_CYCLE (0.500),
214
         .CLKOUT4_DUTY_CYCLE (0.500),
215
         .CLKOUT5_DUTY_CYCLE (0.500),
216
         .COMPENSATION       ("SYSTEM_SYNCHRONOUS"),
217
         .DIVCLK_DIVIDE      (1),
218
         .CLKFBOUT_MULT      (CLK_PERIOD_INT),
219
         .CLKFBOUT_PHASE     (0.0),
220
         .REF_JITTER         (0.005000)
221
         )
222
        u_pll_adv
223
          (
224
           .CLKFBIN     (clkfbout_clkfbin),
225
           .CLKINSEL    (1'b1),
226
           .CLKIN1      (sys_clk_ibufg),
227
           .CLKIN2      (1'b0),
228
           .DADDR       (5'b0),
229
           .DCLK        (1'b0),
230
           .DEN         (1'b0),
231
           .DI          (16'b0),
232
           .DWE         (1'b0),
233
           .REL         (1'b0),
234
           .RST         (sys_rst),
235
           .CLKFBDCM    (),
236
           .CLKFBOUT    (clkfbout_clkfbin),
237
           .CLKOUTDCM0  (),
238
           .CLKOUTDCM1  (),
239
           .CLKOUTDCM2  (),
240
           .CLKOUTDCM3  (),
241
           .CLKOUTDCM4  (),
242
           .CLKOUTDCM5  (),
243
           .CLKOUT0     (clk0_bufg_in),
244
           .CLKOUT1     (clk90_bufg_in),
245
           .CLKOUT2     (clkdiv0_bufg_in),
246
           .CLKOUT3     (),
247
           .CLKOUT4     (),
248
           .CLKOUT5     (),
249
           .DO          (),
250
           .DRDY        (),
251
           .LOCKED      (locked)
252
           );
253
    end else if (CLK_GENERATOR == "DCM") begin: gen_dcm_base
254
      DCM_BASE #
255
        (
256
         .CLKIN_PERIOD          (CLK_PERIOD_NS),
257
         .CLKDV_DIVIDE          (2.0),
258
         .DLL_FREQUENCY_MODE    (DLL_FREQ_MODE),
259
         .DUTY_CYCLE_CORRECTION ("TRUE"),
260
         .FACTORY_JF            (16'hF0F0)
261
         )
262
        u_dcm_base
263
          (
264
           .CLK0      (clk0_bufg_in),
265
           .CLK180    (),
266
           .CLK270    (),
267
           .CLK2X     (),
268
           .CLK2X180  (),
269
           .CLK90     (clk90_bufg_in),
270
           .CLKDV     (clkdiv0_bufg_in),
271
           .CLKFX     (),
272
           .CLKFX180  (),
273
           .LOCKED    (locked),
274
           .CLKFB     (clk0_bufg),
275
           .CLKIN     (sys_clk_ibufg),
276
           .RST       (sys_rst)
277
           );
278
    end
279
  endgenerate
280
 
281
  BUFG U_BUFG_CLK0
282
    (
283
     .O (clk0_bufg),
284
     .I (clk0_bufg_in)
285
     );
286
 
287
  BUFG U_BUFG_CLK90
288
    (
289
     .O (clk90_bufg),
290
     .I (clk90_bufg_in)
291
     );
292
 
293
   BUFG U_BUFG_CLKDIV0
294
    (
295
     .O (clkdiv0_bufg),
296
     .I (clkdiv0_bufg_in)
297
     );
298
 
299
 
300
  //***************************************************************************
301
  // Reset synchronization
302
  // NOTES:
303
  //   1. shut down the whole operation if the PLL/ DCM hasn't yet locked (and
304
  //      by inference, this means that external SYS_RST_IN has been asserted -
305
  //      PLL/DCM deasserts LOCKED as soon as SYS_RST_IN asserted)
306
  //   2. In the case of all resets except rst200, also assert reset if the
307
  //      IDELAY master controller is not yet ready
308
  //   3. asynchronously assert reset. This was we can assert reset even if
309
  //      there is no clock (needed for things like 3-stating output buffers).
310
  //      reset deassertion is synchronous.
311
  //***************************************************************************
312
 
313
  assign rst_tmp = sys_rst | ~locked | ~idelay_ctrl_rdy;
314
 
315
  // synthesis attribute max_fanout of rst0_sync_r is 10
316
  always @(posedge clk0_bufg or posedge rst_tmp)
317
    if (rst_tmp)
318
      rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
319
    else
320
      // logical left shift by one (pads with 0)
321
      rst0_sync_r <= rst0_sync_r << 1;
322
 
323
  // synthesis attribute max_fanout of rstdiv0_sync_r is 10
324
  always @(posedge clkdiv0_bufg or posedge rst_tmp)
325
    if (rst_tmp)
326
      rstdiv0_sync_r <= {(RST_SYNC_NUM/2){1'b1}};
327
    else
328
      // logical left shift by one (pads with 0)
329
      rstdiv0_sync_r <= rstdiv0_sync_r << 1;
330
 
331
  // synthesis attribute max_fanout of rst90_sync_r is 10
332
  always @(posedge clk90_bufg or posedge rst_tmp)
333
    if (rst_tmp)
334
      rst90_sync_r <= {RST_SYNC_NUM{1'b1}};
335
    else
336
      rst90_sync_r <= rst90_sync_r << 1;
337
 
338
  // make sure CLK200 doesn't depend on IDELAY_CTRL_RDY, else chicken n' egg
339
  // synthesis attribute max_fanout of rst200_sync_r is 10
340
  always @(posedge clk200_bufg or negedge locked)
341
    if (!locked)
342
      rst200_sync_r <= {RST_SYNC_NUM{1'b1}};
343
    else
344
      rst200_sync_r <= rst200_sync_r << 1;
345
 
346
 
347
  assign rst0    = rst0_sync_r[RST_SYNC_NUM-1];
348
  assign rst90   = rst90_sync_r[RST_SYNC_NUM-1];
349
  assign rst200  = rst200_sync_r[RST_SYNC_NUM-1];
350
  assign rstdiv0 = rstdiv0_sync_r[(RST_SYNC_NUM/2)-1];
351
 
352
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.