URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [xilinx_ddr2/] [ddr2_phy_io.v] - Blame information for rev 412

Details | Compare with Previous | View Log


//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 3.0
//  \   \         Application: MIG
//  /   /         Filename: ddr2_phy_io.v
// /___/   /\     Date Last Modified: $Date: 2009/01/15 14:22:14 $
// \   \  /  \    Date Created: Wed Aug 16 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//   This module instantiates calibration logic, data, data strobe and the
//   data mask iobs.
//Reference:
//Revision History:
//   Rev 1.1 - DM_IOB instance made based on USE_DM_PORT value . PK. 25/6/08
//   Rev 1.2 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
//   Rev 1.3 - Parameter IODELAY_GRP added. PK. 11/27/08
//*****************************************************************************
 
`timescale 1ns/1ps
 
module ddr2_phy_io #
  (
   // Following parameters are for 72-bit RDIMM design (for ML561 Reference
   // board design). Actual values may be different. Actual parameters values
   // are passed from design top module ddr2_mig module. Please refer to
   // the ddr2_mig module for actual values.
   parameter CLK_WIDTH             = 1,
   parameter USE_DM_PORT           = 1,
   parameter DM_WIDTH              = 9,
   parameter DQ_WIDTH              = 72,
   parameter DQ_BITS               = 7,
   parameter DQ_PER_DQS            = 8,
   parameter DQS_BITS              = 4,
   parameter DQS_WIDTH             = 9,
   parameter HIGH_PERFORMANCE_MODE = "TRUE",
   parameter IODELAY_GRP           = "IODELAY_MIG",
   parameter ODT_WIDTH             = 1,
   parameter ADDITIVE_LAT          = 0,
   parameter CAS_LAT               = 5,
   parameter REG_ENABLE            = 1,
   parameter CLK_PERIOD            = 3000,
   parameter DDR_TYPE              = 1,
   parameter SIM_ONLY              = 0,
   parameter DEBUG_EN              = 0,
   parameter FPGA_SPEED_GRADE      = 2
   )
  (
   input                                clk0,
   input                                clk90,
   input                                clkdiv0,
   input                                rst0,
   input                                rst90,
   input                                rstdiv0,
   input                                dm_ce,
   input [1:0]                          dq_oe_n,
   input                                dqs_oe_n,
   input                                dqs_rst_n,
   input [3:0]                          calib_start,
   input                                ctrl_rden,
   input                                phy_init_rden,
   input                                calib_ref_done,
   output [3:0]                         calib_done,
   output                               calib_ref_req,
   output [DQS_WIDTH-1:0]               calib_rden,
   output [DQS_WIDTH-1:0]               calib_rden_sel,
   input [DQ_WIDTH-1:0]                 wr_data_rise,
   input [DQ_WIDTH-1:0]                 wr_data_fall,
   input [(DQ_WIDTH/8)-1:0]             mask_data_rise,
   input [(DQ_WIDTH/8)-1:0]             mask_data_fall,
   output [(DQ_WIDTH)-1:0]              rd_data_rise,
   output [(DQ_WIDTH)-1:0]              rd_data_fall,
   output [CLK_WIDTH-1:0]               ddr_ck,
   output [CLK_WIDTH-1:0]               ddr_ck_n,
   output [DM_WIDTH-1:0]                ddr_dm,
   inout [DQS_WIDTH-1:0]                ddr_dqs,
   inout [DQS_WIDTH-1:0]                ddr_dqs_n,
   inout [DQ_WIDTH-1:0]                 ddr_dq,
   // Debug signals (optional use)
   input                                dbg_idel_up_all,
   input                                dbg_idel_down_all,
   input                                dbg_idel_up_dq,
   input                                dbg_idel_down_dq,
   input                                dbg_idel_up_dqs,
   input                                dbg_idel_down_dqs,
   input                                dbg_idel_up_gate,
   input                                dbg_idel_down_gate,
   input [DQ_BITS-1:0]                  dbg_sel_idel_dq,
   input                                dbg_sel_all_idel_dq,
   input [DQS_BITS:0]                   dbg_sel_idel_dqs,
   input                                dbg_sel_all_idel_dqs,
   input [DQS_BITS:0]                   dbg_sel_idel_gate,
   input                                dbg_sel_all_idel_gate,
   output [3:0]                         dbg_calib_done,
   output [3:0]                         dbg_calib_err,
   output [(6*DQ_WIDTH)-1:0]            dbg_calib_dq_tap_cnt,
   output [(6*DQS_WIDTH)-1:0]           dbg_calib_dqs_tap_cnt,
   output [(6*DQS_WIDTH)-1:0]           dbg_calib_gate_tap_cnt,
   output [DQS_WIDTH-1:0]               dbg_calib_rd_data_sel,
   output [(5*DQS_WIDTH)-1:0]           dbg_calib_rden_dly,
   output [(5*DQS_WIDTH)-1:0]           dbg_calib_gate_dly
   );
 
  // ratio of # of physical DM outputs to bytes in data bus
  // may be different - e.g. if using x4 components
  localparam DM_TO_BYTE_RATIO = DM_WIDTH / (DQ_WIDTH/8);
 
  wire [CLK_WIDTH-1:0]                     ddr_ck_q;
  wire [DQS_WIDTH-1:0]                     delayed_dqs;
  wire [DQ_WIDTH-1:0]                      dlyce_dq;
  wire [DQS_WIDTH-1:0]                     dlyce_dqs;
  wire [DQS_WIDTH-1:0]                     dlyce_gate;
  wire [DQ_WIDTH-1:0]                      dlyinc_dq;
  wire [DQS_WIDTH-1:0]                     dlyinc_dqs;
  wire [DQS_WIDTH-1:0]                     dlyinc_gate;
  wire                                     dlyrst_dq;
  wire                                     dlyrst_dqs;
  wire [DQS_WIDTH-1:0]                     dlyrst_gate;
  wire [DQS_WIDTH-1:0]                     dq_ce;
  (* KEEP = "TRUE" *) wire [DQS_WIDTH-1:0] en_dqs /* synthesis syn_keep = 1 */;
  wire [DQS_WIDTH-1:0]                     rd_data_sel;
 
  //***************************************************************************
 
  ddr2_phy_calib #
    (
     .DQ_WIDTH      (DQ_WIDTH),
     .DQ_BITS       (DQ_BITS),
     .DQ_PER_DQS    (DQ_PER_DQS),
     .DQS_BITS      (DQS_BITS),
     .DQS_WIDTH     (DQS_WIDTH),
     .ADDITIVE_LAT  (ADDITIVE_LAT),
     .CAS_LAT       (CAS_LAT),
     .REG_ENABLE    (REG_ENABLE),
     .CLK_PERIOD    (CLK_PERIOD),
     .SIM_ONLY      (SIM_ONLY),
     .DEBUG_EN      (DEBUG_EN)
     )
    u_phy_calib
      (
       .clk                    (clk0),
       .clkdiv                 (clkdiv0),
       .rstdiv                 (rstdiv0),
       .calib_start            (calib_start),
       .ctrl_rden              (ctrl_rden),
       .phy_init_rden          (phy_init_rden),
       .rd_data_rise           (rd_data_rise),
       .rd_data_fall           (rd_data_fall),
       .calib_ref_done         (calib_ref_done),
       .calib_done             (calib_done),
       .calib_ref_req          (calib_ref_req),
       .calib_rden             (calib_rden),
       .calib_rden_sel         (calib_rden_sel),
       .dlyrst_dq              (dlyrst_dq),
       .dlyce_dq               (dlyce_dq),
       .dlyinc_dq              (dlyinc_dq),
       .dlyrst_dqs             (dlyrst_dqs),
       .dlyce_dqs              (dlyce_dqs),
       .dlyinc_dqs             (dlyinc_dqs),
       .dlyrst_gate            (dlyrst_gate),
       .dlyce_gate             (dlyce_gate),
       .dlyinc_gate            (dlyinc_gate),
       .en_dqs                 (en_dqs),
       .rd_data_sel            (rd_data_sel),
       .dbg_idel_up_all        (dbg_idel_up_all),
       .dbg_idel_down_all      (dbg_idel_down_all),
       .dbg_idel_up_dq         (dbg_idel_up_dq),
       .dbg_idel_down_dq       (dbg_idel_down_dq),
       .dbg_idel_up_dqs        (dbg_idel_up_dqs),
       .dbg_idel_down_dqs      (dbg_idel_down_dqs),
       .dbg_idel_up_gate       (dbg_idel_up_gate),
       .dbg_idel_down_gate     (dbg_idel_down_gate),
       .dbg_sel_idel_dq        (dbg_sel_idel_dq),
       .dbg_sel_all_idel_dq    (dbg_sel_all_idel_dq),
       .dbg_sel_idel_dqs       (dbg_sel_idel_dqs),
       .dbg_sel_all_idel_dqs   (dbg_sel_all_idel_dqs),
       .dbg_sel_idel_gate      (dbg_sel_idel_gate),
       .dbg_sel_all_idel_gate  (dbg_sel_all_idel_gate),
       .dbg_calib_done         (dbg_calib_done),
       .dbg_calib_err          (dbg_calib_err),
       .dbg_calib_dq_tap_cnt   (dbg_calib_dq_tap_cnt),
       .dbg_calib_dqs_tap_cnt  (dbg_calib_dqs_tap_cnt),
       .dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
       .dbg_calib_rd_data_sel  (dbg_calib_rd_data_sel),
       .dbg_calib_rden_dly     (dbg_calib_rden_dly),
       .dbg_calib_gate_dly     (dbg_calib_gate_dly)
       );
 
  //***************************************************************************
  // Memory clock generation
  //***************************************************************************
 
  genvar ck_i;
  generate
    for(ck_i = 0; ck_i < CLK_WIDTH; ck_i = ck_i+1) begin: gen_ck
      ODDR #
        (
         .SRTYPE       ("SYNC"),
         .DDR_CLK_EDGE ("OPPOSITE_EDGE")
         )
        u_oddr_ck_i
          (
           .Q   (ddr_ck_q[ck_i]),
           .C   (clk0),
           .CE  (1'b1),
           .D1  (1'b0),
           .D2  (1'b1),
           .R   (1'b0),
           .S   (1'b0)
           );
      // Can insert ODELAY here if required
      OBUFDS u_obuf_ck_i
        (
         .I   (ddr_ck_q[ck_i]),
         .O   (ddr_ck[ck_i]),
         .OB  (ddr_ck_n[ck_i])
         );
    end
  endgenerate
 
  //***************************************************************************
  // DQS instances
  //***************************************************************************
 
  genvar dqs_i;
  generate
    for(dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i+1) begin: gen_dqs
      ddr2_phy_dqs_iob #
        (
         .DDR_TYPE              (DDR_TYPE),
         .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
         .IODELAY_GRP           (IODELAY_GRP)
         )
        u_iob_dqs
          (
           .clk0           (clk0),
           .clkdiv0        (clkdiv0),
           .rst0           (rst0),
           .dlyinc_dqs     (dlyinc_dqs[dqs_i]),
           .dlyce_dqs      (dlyce_dqs[dqs_i]),
           .dlyrst_dqs     (dlyrst_dqs),
           .dlyinc_gate    (dlyinc_gate[dqs_i]),
           .dlyce_gate     (dlyce_gate[dqs_i]),
           .dlyrst_gate    (dlyrst_gate[dqs_i]),
           .dqs_oe_n       (dqs_oe_n),
           .dqs_rst_n      (dqs_rst_n),
           .en_dqs         (en_dqs[dqs_i]),
           .ddr_dqs        (ddr_dqs[dqs_i]),
           .ddr_dqs_n      (ddr_dqs_n[dqs_i]),
           .dq_ce          (dq_ce[dqs_i]),
           .delayed_dqs    (delayed_dqs[dqs_i])
           );
    end
  endgenerate
 
  //***************************************************************************
  // DM instances
  //***************************************************************************
 
  genvar dm_i;
  generate
    if (USE_DM_PORT) begin: gen_dm_inst
      for(dm_i = 0; dm_i < DM_WIDTH; dm_i = dm_i+1) begin: gen_dm
        ddr2_phy_dm_iob u_iob_dm
          (
           .clk90           (clk90),
           .dm_ce           (dm_ce),
           .mask_data_rise  (mask_data_rise[dm_i/DM_TO_BYTE_RATIO]),
           .mask_data_fall  (mask_data_fall[dm_i/DM_TO_BYTE_RATIO]),
           .ddr_dm          (ddr_dm[dm_i])
           );
      end
    end
  endgenerate
 
  //***************************************************************************
  // DQ IOB instances
  //***************************************************************************
 
  genvar dq_i;
  generate
    for(dq_i = 0; dq_i < DQ_WIDTH; dq_i = dq_i+1) begin: gen_dq
      ddr2_phy_dq_iob #
        (
         .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
         .IODELAY_GRP           (IODELAY_GRP),
         .FPGA_SPEED_GRADE      (FPGA_SPEED_GRADE)
         )
        u_iob_dq
        (
         .clk0         (clk0),
         .clk90        (clk90),
         .clkdiv0      (clkdiv0),
         .rst90        (rst90),
         .dlyinc       (dlyinc_dq[dq_i]),
         .dlyce        (dlyce_dq[dq_i]),
         .dlyrst       (dlyrst_dq),
         .dq_oe_n      (dq_oe_n),
         .dqs          (delayed_dqs[dq_i/DQ_PER_DQS]),
         .ce           (dq_ce[dq_i/DQ_PER_DQS]),
         .rd_data_sel  (rd_data_sel[dq_i/DQ_PER_DQS]),
         .wr_data_rise (wr_data_rise[dq_i]),
         .wr_data_fall (wr_data_fall[dq_i]),
         .rd_data_rise (rd_data_rise[dq_i]),
         .rd_data_fall (rd_data_fall[dq_i]),
         .ddr_dq       (ddr_dq[dq_i])
         );
    end
  endgenerate
 
endmodule

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [xilinx_ddr2/] [ddr2_phy_io.v] - Blame information for rev 412

Line No.	Rev	Author	Line
1	412	julius	`//*****************************************************************************`
2			`// DISCLAIMER OF LIABILITY`
3			`//`
4			`// This file contains proprietary and confidential information of`
5			`// Xilinx, Inc. ("Xilinx"), that is distributed under a license`
6			`// from Xilinx, and may be used, copied and/or disclosed only`
7			`// pursuant to the terms of a valid license agreement with Xilinx.`
8			`//`
9			`// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION`
10			`// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER`
11			`// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT`
12			`// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,`
13			`// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx`
14			`// does not warrant that functions included in the Materials will`
15			`// meet the requirements of Licensee, or that the operation of the`
16			`// Materials will be uninterrupted or error-free, or that defects`
17			`// in the Materials will be corrected. Furthermore, Xilinx does`
18			`// not warrant or make any representations regarding use, or the`
19			`// results of the use, of the Materials in terms of correctness,`
20			`// accuracy, reliability or otherwise.`
21			`//`
22			`// Xilinx products are not designed or intended to be fail-safe,`
23			`// or for use in any application requiring fail-safe performance,`
24			`// such as life-support or safety devices or systems, Class III`
25			`// medical devices, nuclear facilities, applications related to`
26			`// the deployment of airbags, or any other applications that could`
27			`// lead to death, personal injury or severe property or`
28			`// environmental damage (individually and collectively, "critical`
29			`// applications"). Customer assumes the sole risk and liability`
30			`// of any use of Xilinx products in critical applications,`
31			`// subject only to applicable laws and regulations governing`
32			`// limitations on product liability.`
33			`//`
34			`// Copyright 2006, 2007, 2008 Xilinx, Inc.`
35			`// All rights reserved.`
36			`//`
37			`// This disclaimer and copyright notice must be retained as part`
38			`// of this file at all times.`
39			`//*****************************************************************************`
40			`// ____ ____`
41			`// / /\/ /`
42			`// /___/ \ / Vendor: Xilinx`
43			`// \ \ \/ Version: 3.0`
44			`// \ \ Application: MIG`
45			`// / / Filename: ddr2_phy_io.v`
46			`// /___/ /\ Date Last Modified: $Date: 2009/01/15 14:22:14 $`
47			`// \ \ / \ Date Created: Wed Aug 16 2006`
48			`// \___\/\___\`
49			`//`
50			`//Device: Virtex-5`
51			`//Design Name: DDR2`
52			`//Purpose:`
53			`// This module instantiates calibration logic, data, data strobe and the`
54			`// data mask iobs.`
55			`//Reference:`
56			`//Revision History:`
57			`// Rev 1.1 - DM_IOB instance made based on USE_DM_PORT value . PK. 25/6/08`
58			`// Rev 1.2 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08`
59			`// Rev 1.3 - Parameter IODELAY_GRP added. PK. 11/27/08`
60			`//*****************************************************************************`
61
62			`timescale 1ns/1ps
63
64			`module ddr2_phy_io #`
65			`(`
66			`// Following parameters are for 72-bit RDIMM design (for ML561 Reference`
67			`// board design). Actual values may be different. Actual parameters values`
68			`// are passed from design top module ddr2_mig module. Please refer to`
69			`// the ddr2_mig module for actual values.`
70			`parameter CLK_WIDTH = 1,`
71			`parameter USE_DM_PORT = 1,`
72			`parameter DM_WIDTH = 9,`
73			`parameter DQ_WIDTH = 72,`
74			`parameter DQ_BITS = 7,`
75			`parameter DQ_PER_DQS = 8,`
76			`parameter DQS_BITS = 4,`
77			`parameter DQS_WIDTH = 9,`
78			`parameter HIGH_PERFORMANCE_MODE = "TRUE",`
79			`parameter IODELAY_GRP = "IODELAY_MIG",`
80			`parameter ODT_WIDTH = 1,`
81			`parameter ADDITIVE_LAT = 0,`
82			`parameter CAS_LAT = 5,`
83			`parameter REG_ENABLE = 1,`
84			`parameter CLK_PERIOD = 3000,`
85			`parameter DDR_TYPE = 1,`
86			`parameter SIM_ONLY = 0,`
87			`parameter DEBUG_EN = 0,`
88			`parameter FPGA_SPEED_GRADE = 2`
89			`)`
90			`(`
91			`input clk0,`
92			`input clk90,`
93			`input clkdiv0,`
94			`input rst0,`
95			`input rst90,`
96			`input rstdiv0,`
97			`input dm_ce,`
98			`input [1:0] dq_oe_n,`
99			`input dqs_oe_n,`
100			`input dqs_rst_n,`
101			`input [3:0] calib_start,`
102			`input ctrl_rden,`
103			`input phy_init_rden,`
104			`input calib_ref_done,`
105			`output [3:0] calib_done,`
106			`output calib_ref_req,`
107			`output [DQS_WIDTH-1:0] calib_rden,`
108			`output [DQS_WIDTH-1:0] calib_rden_sel,`
109			`input [DQ_WIDTH-1:0] wr_data_rise,`
110			`input [DQ_WIDTH-1:0] wr_data_fall,`
111			`input [(DQ_WIDTH/8)-1:0] mask_data_rise,`
112			`input [(DQ_WIDTH/8)-1:0] mask_data_fall,`
113			`output [(DQ_WIDTH)-1:0] rd_data_rise,`
114			`output [(DQ_WIDTH)-1:0] rd_data_fall,`
115			`output [CLK_WIDTH-1:0] ddr_ck,`
116			`output [CLK_WIDTH-1:0] ddr_ck_n,`
117			`output [DM_WIDTH-1:0] ddr_dm,`
118			`inout [DQS_WIDTH-1:0] ddr_dqs,`
119			`inout [DQS_WIDTH-1:0] ddr_dqs_n,`
120			`inout [DQ_WIDTH-1:0] ddr_dq,`
121			`// Debug signals (optional use)`
122			`input dbg_idel_up_all,`
123			`input dbg_idel_down_all,`
124			`input dbg_idel_up_dq,`
125			`input dbg_idel_down_dq,`
126			`input dbg_idel_up_dqs,`
127			`input dbg_idel_down_dqs,`
128			`input dbg_idel_up_gate,`
129			`input dbg_idel_down_gate,`
130			`input [DQ_BITS-1:0] dbg_sel_idel_dq,`
131			`input dbg_sel_all_idel_dq,`
132			`input [DQS_BITS:0] dbg_sel_idel_dqs,`
133			`input dbg_sel_all_idel_dqs,`
134			`input [DQS_BITS:0] dbg_sel_idel_gate,`
135			`input dbg_sel_all_idel_gate,`
136			`output [3:0] dbg_calib_done,`
137			`output [3:0] dbg_calib_err,`
138			`output [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt,`
139			`output [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt,`
140			`output [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt,`
141			`output [DQS_WIDTH-1:0] dbg_calib_rd_data_sel,`
142			`output [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly,`
143			`output [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly`
144			`);`
145
146			`// ratio of # of physical DM outputs to bytes in data bus`
147			`// may be different - e.g. if using x4 components`
148			`localparam DM_TO_BYTE_RATIO = DM_WIDTH / (DQ_WIDTH/8);`
149
150			`wire [CLK_WIDTH-1:0] ddr_ck_q;`
151			`wire [DQS_WIDTH-1:0] delayed_dqs;`
152			`wire [DQ_WIDTH-1:0] dlyce_dq;`
153			`wire [DQS_WIDTH-1:0] dlyce_dqs;`
154			`wire [DQS_WIDTH-1:0] dlyce_gate;`
155			`wire [DQ_WIDTH-1:0] dlyinc_dq;`
156			`wire [DQS_WIDTH-1:0] dlyinc_dqs;`
157			`wire [DQS_WIDTH-1:0] dlyinc_gate;`
158			`wire dlyrst_dq;`
159			`wire dlyrst_dqs;`
160			`wire [DQS_WIDTH-1:0] dlyrst_gate;`
161			`wire [DQS_WIDTH-1:0] dq_ce;`
162			`(* KEEP = "TRUE" ) wire [DQS_WIDTH-1:0] en_dqs / synthesis syn_keep = 1 */;`
163			`wire [DQS_WIDTH-1:0] rd_data_sel;`
164
165			`//***************************************************************************`
166
167			`ddr2_phy_calib #`
168			`(`
169			`.DQ_WIDTH (DQ_WIDTH),`
170			`.DQ_BITS (DQ_BITS),`
171			`.DQ_PER_DQS (DQ_PER_DQS),`
172			`.DQS_BITS (DQS_BITS),`
173			`.DQS_WIDTH (DQS_WIDTH),`
174			`.ADDITIVE_LAT (ADDITIVE_LAT),`
175			`.CAS_LAT (CAS_LAT),`
176			`.REG_ENABLE (REG_ENABLE),`
177			`.CLK_PERIOD (CLK_PERIOD),`
178			`.SIM_ONLY (SIM_ONLY),`
179			`.DEBUG_EN (DEBUG_EN)`
180			`)`
181			`u_phy_calib`
182			`(`
183			`.clk (clk0),`
184			`.clkdiv (clkdiv0),`
185			`.rstdiv (rstdiv0),`
186			`.calib_start (calib_start),`
187			`.ctrl_rden (ctrl_rden),`
188			`.phy_init_rden (phy_init_rden),`
189			`.rd_data_rise (rd_data_rise),`
190			`.rd_data_fall (rd_data_fall),`
191			`.calib_ref_done (calib_ref_done),`
192			`.calib_done (calib_done),`
193			`.calib_ref_req (calib_ref_req),`
194			`.calib_rden (calib_rden),`
195			`.calib_rden_sel (calib_rden_sel),`
196			`.dlyrst_dq (dlyrst_dq),`
197			`.dlyce_dq (dlyce_dq),`
198			`.dlyinc_dq (dlyinc_dq),`
199			`.dlyrst_dqs (dlyrst_dqs),`
200			`.dlyce_dqs (dlyce_dqs),`
201			`.dlyinc_dqs (dlyinc_dqs),`
202			`.dlyrst_gate (dlyrst_gate),`
203			`.dlyce_gate (dlyce_gate),`
204			`.dlyinc_gate (dlyinc_gate),`
205			`.en_dqs (en_dqs),`
206			`.rd_data_sel (rd_data_sel),`
207			`.dbg_idel_up_all (dbg_idel_up_all),`
208			`.dbg_idel_down_all (dbg_idel_down_all),`
209			`.dbg_idel_up_dq (dbg_idel_up_dq),`
210			`.dbg_idel_down_dq (dbg_idel_down_dq),`
211			`.dbg_idel_up_dqs (dbg_idel_up_dqs),`
212			`.dbg_idel_down_dqs (dbg_idel_down_dqs),`
213			`.dbg_idel_up_gate (dbg_idel_up_gate),`
214			`.dbg_idel_down_gate (dbg_idel_down_gate),`
215			`.dbg_sel_idel_dq (dbg_sel_idel_dq),`
216			`.dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),`
217			`.dbg_sel_idel_dqs (dbg_sel_idel_dqs),`
218			`.dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),`
219			`.dbg_sel_idel_gate (dbg_sel_idel_gate),`
220			`.dbg_sel_all_idel_gate (dbg_sel_all_idel_gate),`
221			`.dbg_calib_done (dbg_calib_done),`
222			`.dbg_calib_err (dbg_calib_err),`
223			`.dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),`
224			`.dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),`
225			`.dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),`
226			`.dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),`
227			`.dbg_calib_rden_dly (dbg_calib_rden_dly),`
228			`.dbg_calib_gate_dly (dbg_calib_gate_dly)`
229			`);`
230
231			`//***************************************************************************`
232			`// Memory clock generation`
233			`//***************************************************************************`
234
235			`genvar ck_i;`
236			`generate`
237			`for(ck_i = 0; ck_i < CLK_WIDTH; ck_i = ck_i+1) begin: gen_ck`
238			`ODDR #`
239			`(`
240			`.SRTYPE ("SYNC"),`
241			`.DDR_CLK_EDGE ("OPPOSITE_EDGE")`
242			`)`
243			`u_oddr_ck_i`
244			`(`
245			`.Q (ddr_ck_q[ck_i]),`
246			`.C (clk0),`
247			`.CE (1'b1),`
248			`.D1 (1'b0),`
249			`.D2 (1'b1),`
250			`.R (1'b0),`
251			`.S (1'b0)`
252			`);`
253			`// Can insert ODELAY here if required`
254			`OBUFDS u_obuf_ck_i`
255			`(`
256			`.I (ddr_ck_q[ck_i]),`
257			`.O (ddr_ck[ck_i]),`
258			`.OB (ddr_ck_n[ck_i])`
259			`);`
260			`end`
261			`endgenerate`
262
263			`//***************************************************************************`
264			`// DQS instances`
265			`//***************************************************************************`
266
267			`genvar dqs_i;`
268			`generate`
269			`for(dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i+1) begin: gen_dqs`
270			`ddr2_phy_dqs_iob #`
271			`(`
272			`.DDR_TYPE (DDR_TYPE),`
273			`.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),`
274			`.IODELAY_GRP (IODELAY_GRP)`
275			`)`
276			`u_iob_dqs`
277			`(`
278			`.clk0 (clk0),`
279			`.clkdiv0 (clkdiv0),`
280			`.rst0 (rst0),`
281			`.dlyinc_dqs (dlyinc_dqs[dqs_i]),`
282			`.dlyce_dqs (dlyce_dqs[dqs_i]),`
283			`.dlyrst_dqs (dlyrst_dqs),`
284			`.dlyinc_gate (dlyinc_gate[dqs_i]),`
285			`.dlyce_gate (dlyce_gate[dqs_i]),`
286			`.dlyrst_gate (dlyrst_gate[dqs_i]),`
287			`.dqs_oe_n (dqs_oe_n),`
288			`.dqs_rst_n (dqs_rst_n),`
289			`.en_dqs (en_dqs[dqs_i]),`
290			`.ddr_dqs (ddr_dqs[dqs_i]),`
291			`.ddr_dqs_n (ddr_dqs_n[dqs_i]),`
292			`.dq_ce (dq_ce[dqs_i]),`
293			`.delayed_dqs (delayed_dqs[dqs_i])`
294			`);`
295			`end`
296			`endgenerate`
297
298			`//***************************************************************************`
299			`// DM instances`
300			`//***************************************************************************`
301
302			`genvar dm_i;`
303			`generate`
304			`if (USE_DM_PORT) begin: gen_dm_inst`
305			`for(dm_i = 0; dm_i < DM_WIDTH; dm_i = dm_i+1) begin: gen_dm`
306			`ddr2_phy_dm_iob u_iob_dm`
307			`(`
308			`.clk90 (clk90),`
309			`.dm_ce (dm_ce),`
310			`.mask_data_rise (mask_data_rise[dm_i/DM_TO_BYTE_RATIO]),`
311			`.mask_data_fall (mask_data_fall[dm_i/DM_TO_BYTE_RATIO]),`
312			`.ddr_dm (ddr_dm[dm_i])`
313			`);`
314			`end`
315			`end`
316			`endgenerate`
317
318			`//***************************************************************************`
319			`// DQ IOB instances`
320			`//***************************************************************************`
321
322			`genvar dq_i;`
323			`generate`
324			`for(dq_i = 0; dq_i < DQ_WIDTH; dq_i = dq_i+1) begin: gen_dq`
325			`ddr2_phy_dq_iob #`
326			`(`
327			`.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),`
328			`.IODELAY_GRP (IODELAY_GRP),`
329			`.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE)`
330			`)`
331			`u_iob_dq`
332			`(`
333			`.clk0 (clk0),`
334			`.clk90 (clk90),`
335			`.clkdiv0 (clkdiv0),`
336			`.rst90 (rst90),`
337			`.dlyinc (dlyinc_dq[dq_i]),`
338			`.dlyce (dlyce_dq[dq_i]),`
339			`.dlyrst (dlyrst_dq),`
340			`.dq_oe_n (dq_oe_n),`
341			`.dqs (delayed_dqs[dq_i/DQ_PER_DQS]),`
342			`.ce (dq_ce[dq_i/DQ_PER_DQS]),`
343			`.rd_data_sel (rd_data_sel[dq_i/DQ_PER_DQS]),`
344			`.wr_data_rise (wr_data_rise[dq_i]),`
345			`.wr_data_fall (wr_data_fall[dq_i]),`
346			`.rd_data_rise (rd_data_rise[dq_i]),`
347			`.rd_data_fall (rd_data_fall[dq_i]),`
348			`.ddr_dq (ddr_dq[dq_i])`
349			`);`
350			`end`
351			`endgenerate`
352
353			`endmodule`