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//*****************************************************************************
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// DISCLAIMER OF LIABILITY
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//
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// This file contains proprietary and confidential information of
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// Xilinx, Inc. ("Xilinx"), that is distributed under a license
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// from Xilinx, and may be used, copied and/or disclosed only
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// pursuant to the terms of a valid license agreement with Xilinx.
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//
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// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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// does not warrant that functions included in the Materials will
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// meet the requirements of Licensee, or that the operation of the
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// Materials will be uninterrupted or error-free, or that defects
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// in the Materials will be corrected. Furthermore, Xilinx does
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// not warrant or make any representations regarding use, or the
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// results of the use, of the Materials in terms of correctness,
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// accuracy, reliability or otherwise.
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//
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// Xilinx products are not designed or intended to be fail-safe,
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// or for use in any application requiring fail-safe performance,
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// such as life-support or safety devices or systems, Class III
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// medical devices, nuclear facilities, applications related to
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// the deployment of airbags, or any other applications that could
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// lead to death, personal injury or severe property or
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// environmental damage (individually and collectively, "critical
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// applications"). Customer assumes the sole risk and liability
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// of any use of Xilinx products in critical applications,
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// subject only to applicable laws and regulations governing
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// limitations on product liability.
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//
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// Copyright 2006, 2007, 2008 Xilinx, Inc.
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// All rights reserved.
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//
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// This disclaimer and copyright notice must be retained as part
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// of this file at all times.
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: 3.0
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// \ \ Application: MIG
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// / / Filename: ddr2_phy_io.v
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// /___/ /\ Date Last Modified: $Date: 2009/01/15 14:22:14 $
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// \ \ / \ Date Created: Wed Aug 16 2006
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// \___\/\___\
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//
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//Device: Virtex-5
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//Design Name: DDR2
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//Purpose:
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// This module instantiates calibration logic, data, data strobe and the
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// data mask iobs.
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//Reference:
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//Revision History:
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// Rev 1.1 - DM_IOB instance made based on USE_DM_PORT value . PK. 25/6/08
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// Rev 1.2 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
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// Rev 1.3 - Parameter IODELAY_GRP added. PK. 11/27/08
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//*****************************************************************************
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`timescale 1ns/1ps
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module ddr2_phy_io #
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(
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// Following parameters are for 72-bit RDIMM design (for ML561 Reference
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// board design). Actual values may be different. Actual parameters values
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// are passed from design top module ddr2_mig module. Please refer to
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// the ddr2_mig module for actual values.
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parameter CLK_WIDTH = 1,
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parameter USE_DM_PORT = 1,
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parameter DM_WIDTH = 9,
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parameter DQ_WIDTH = 72,
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parameter DQ_BITS = 7,
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parameter DQ_PER_DQS = 8,
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parameter DQS_BITS = 4,
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parameter DQS_WIDTH = 9,
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parameter HIGH_PERFORMANCE_MODE = "TRUE",
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parameter IODELAY_GRP = "IODELAY_MIG",
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parameter ODT_WIDTH = 1,
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parameter ADDITIVE_LAT = 0,
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parameter CAS_LAT = 5,
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parameter REG_ENABLE = 1,
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parameter CLK_PERIOD = 3000,
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parameter DDR_TYPE = 1,
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parameter SIM_ONLY = 0,
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parameter DEBUG_EN = 0,
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parameter FPGA_SPEED_GRADE = 2
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)
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(
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input clk0,
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input clk90,
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input clkdiv0,
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input rst0,
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input rst90,
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input rstdiv0,
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input dm_ce,
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input [1:0] dq_oe_n,
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input dqs_oe_n,
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input dqs_rst_n,
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input [3:0] calib_start,
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input ctrl_rden,
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input phy_init_rden,
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input calib_ref_done,
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output [3:0] calib_done,
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output calib_ref_req,
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output [DQS_WIDTH-1:0] calib_rden,
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output [DQS_WIDTH-1:0] calib_rden_sel,
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input [DQ_WIDTH-1:0] wr_data_rise,
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input [DQ_WIDTH-1:0] wr_data_fall,
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input [(DQ_WIDTH/8)-1:0] mask_data_rise,
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input [(DQ_WIDTH/8)-1:0] mask_data_fall,
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output [(DQ_WIDTH)-1:0] rd_data_rise,
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output [(DQ_WIDTH)-1:0] rd_data_fall,
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output [CLK_WIDTH-1:0] ddr_ck,
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output [CLK_WIDTH-1:0] ddr_ck_n,
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output [DM_WIDTH-1:0] ddr_dm,
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inout [DQS_WIDTH-1:0] ddr_dqs,
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inout [DQS_WIDTH-1:0] ddr_dqs_n,
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inout [DQ_WIDTH-1:0] ddr_dq,
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// Debug signals (optional use)
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input dbg_idel_up_all,
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input dbg_idel_down_all,
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input dbg_idel_up_dq,
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input dbg_idel_down_dq,
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input dbg_idel_up_dqs,
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input dbg_idel_down_dqs,
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input dbg_idel_up_gate,
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input dbg_idel_down_gate,
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input [DQ_BITS-1:0] dbg_sel_idel_dq,
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input dbg_sel_all_idel_dq,
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input [DQS_BITS:0] dbg_sel_idel_dqs,
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input dbg_sel_all_idel_dqs,
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input [DQS_BITS:0] dbg_sel_idel_gate,
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input dbg_sel_all_idel_gate,
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output [3:0] dbg_calib_done,
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output [3:0] dbg_calib_err,
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output [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt,
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output [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt,
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output [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt,
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output [DQS_WIDTH-1:0] dbg_calib_rd_data_sel,
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output [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly,
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output [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly
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);
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// ratio of # of physical DM outputs to bytes in data bus
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// may be different - e.g. if using x4 components
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localparam DM_TO_BYTE_RATIO = DM_WIDTH / (DQ_WIDTH/8);
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wire [CLK_WIDTH-1:0] ddr_ck_q;
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wire [DQS_WIDTH-1:0] delayed_dqs;
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wire [DQ_WIDTH-1:0] dlyce_dq;
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wire [DQS_WIDTH-1:0] dlyce_dqs;
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wire [DQS_WIDTH-1:0] dlyce_gate;
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wire [DQ_WIDTH-1:0] dlyinc_dq;
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wire [DQS_WIDTH-1:0] dlyinc_dqs;
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wire [DQS_WIDTH-1:0] dlyinc_gate;
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wire dlyrst_dq;
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wire dlyrst_dqs;
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wire [DQS_WIDTH-1:0] dlyrst_gate;
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wire [DQS_WIDTH-1:0] dq_ce;
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(* KEEP = "TRUE" *) wire [DQS_WIDTH-1:0] en_dqs /* synthesis syn_keep = 1 */;
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wire [DQS_WIDTH-1:0] rd_data_sel;
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//***************************************************************************
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ddr2_phy_calib #
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(
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.DQ_WIDTH (DQ_WIDTH),
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.DQ_BITS (DQ_BITS),
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.DQ_PER_DQS (DQ_PER_DQS),
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.DQS_BITS (DQS_BITS),
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.DQS_WIDTH (DQS_WIDTH),
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.ADDITIVE_LAT (ADDITIVE_LAT),
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.CAS_LAT (CAS_LAT),
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.REG_ENABLE (REG_ENABLE),
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.CLK_PERIOD (CLK_PERIOD),
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.SIM_ONLY (SIM_ONLY),
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.DEBUG_EN (DEBUG_EN)
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)
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u_phy_calib
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(
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.clk (clk0),
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.clkdiv (clkdiv0),
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.rstdiv (rstdiv0),
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.calib_start (calib_start),
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.ctrl_rden (ctrl_rden),
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.phy_init_rden (phy_init_rden),
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.rd_data_rise (rd_data_rise),
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.rd_data_fall (rd_data_fall),
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.calib_ref_done (calib_ref_done),
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.calib_done (calib_done),
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.calib_ref_req (calib_ref_req),
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.calib_rden (calib_rden),
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.calib_rden_sel (calib_rden_sel),
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.dlyrst_dq (dlyrst_dq),
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.dlyce_dq (dlyce_dq),
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.dlyinc_dq (dlyinc_dq),
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.dlyrst_dqs (dlyrst_dqs),
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.dlyce_dqs (dlyce_dqs),
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.dlyinc_dqs (dlyinc_dqs),
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.dlyrst_gate (dlyrst_gate),
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.dlyce_gate (dlyce_gate),
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.dlyinc_gate (dlyinc_gate),
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.en_dqs (en_dqs),
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.rd_data_sel (rd_data_sel),
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.dbg_idel_up_all (dbg_idel_up_all),
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.dbg_idel_down_all (dbg_idel_down_all),
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.dbg_idel_up_dq (dbg_idel_up_dq),
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.dbg_idel_down_dq (dbg_idel_down_dq),
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.dbg_idel_up_dqs (dbg_idel_up_dqs),
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.dbg_idel_down_dqs (dbg_idel_down_dqs),
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.dbg_idel_up_gate (dbg_idel_up_gate),
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.dbg_idel_down_gate (dbg_idel_down_gate),
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.dbg_sel_idel_dq (dbg_sel_idel_dq),
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.dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),
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.dbg_sel_idel_dqs (dbg_sel_idel_dqs),
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.dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),
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.dbg_sel_idel_gate (dbg_sel_idel_gate),
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.dbg_sel_all_idel_gate (dbg_sel_all_idel_gate),
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.dbg_calib_done (dbg_calib_done),
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.dbg_calib_err (dbg_calib_err),
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.dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),
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.dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),
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.dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
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.dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),
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.dbg_calib_rden_dly (dbg_calib_rden_dly),
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.dbg_calib_gate_dly (dbg_calib_gate_dly)
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);
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//***************************************************************************
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// Memory clock generation
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//***************************************************************************
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genvar ck_i;
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generate
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for(ck_i = 0; ck_i < CLK_WIDTH; ck_i = ck_i+1) begin: gen_ck
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ODDR #
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(
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.SRTYPE ("SYNC"),
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.DDR_CLK_EDGE ("OPPOSITE_EDGE")
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)
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u_oddr_ck_i
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(
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.Q (ddr_ck_q[ck_i]),
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.C (clk0),
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.CE (1'b1),
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.D1 (1'b0),
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.D2 (1'b1),
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.R (1'b0),
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.S (1'b0)
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);
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// Can insert ODELAY here if required
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OBUFDS u_obuf_ck_i
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(
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.I (ddr_ck_q[ck_i]),
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.O (ddr_ck[ck_i]),
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.OB (ddr_ck_n[ck_i])
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);
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end
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endgenerate
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//***************************************************************************
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// DQS instances
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| 265 |
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//***************************************************************************
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| 266 |
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genvar dqs_i;
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generate
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for(dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i+1) begin: gen_dqs
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ddr2_phy_dqs_iob #
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| 271 |
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(
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| 272 |
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.DDR_TYPE (DDR_TYPE),
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| 273 |
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.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
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| 274 |
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.IODELAY_GRP (IODELAY_GRP)
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| 275 |
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)
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u_iob_dqs
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| 277 |
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(
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| 278 |
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.clk0 (clk0),
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| 279 |
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.clkdiv0 (clkdiv0),
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| 280 |
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.rst0 (rst0),
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| 281 |
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.dlyinc_dqs (dlyinc_dqs[dqs_i]),
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| 282 |
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.dlyce_dqs (dlyce_dqs[dqs_i]),
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| 283 |
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.dlyrst_dqs (dlyrst_dqs),
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| 284 |
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.dlyinc_gate (dlyinc_gate[dqs_i]),
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| 285 |
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.dlyce_gate (dlyce_gate[dqs_i]),
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| 286 |
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.dlyrst_gate (dlyrst_gate[dqs_i]),
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| 287 |
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.dqs_oe_n (dqs_oe_n),
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| 288 |
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.dqs_rst_n (dqs_rst_n),
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| 289 |
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.en_dqs (en_dqs[dqs_i]),
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.ddr_dqs (ddr_dqs[dqs_i]),
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.ddr_dqs_n (ddr_dqs_n[dqs_i]),
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| 292 |
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.dq_ce (dq_ce[dqs_i]),
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| 293 |
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.delayed_dqs (delayed_dqs[dqs_i])
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| 294 |
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);
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| 295 |
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end
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endgenerate
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//***************************************************************************
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| 299 |
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// DM instances
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| 300 |
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//***************************************************************************
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| 301 |
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genvar dm_i;
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generate
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|
if (USE_DM_PORT) begin: gen_dm_inst
|
| 305 |
|
|
for(dm_i = 0; dm_i < DM_WIDTH; dm_i = dm_i+1) begin: gen_dm
|
| 306 |
|
|
ddr2_phy_dm_iob u_iob_dm
|
| 307 |
|
|
(
|
| 308 |
|
|
.clk90 (clk90),
|
| 309 |
|
|
.dm_ce (dm_ce),
|
| 310 |
|
|
.mask_data_rise (mask_data_rise[dm_i/DM_TO_BYTE_RATIO]),
|
| 311 |
|
|
.mask_data_fall (mask_data_fall[dm_i/DM_TO_BYTE_RATIO]),
|
| 312 |
|
|
.ddr_dm (ddr_dm[dm_i])
|
| 313 |
|
|
);
|
| 314 |
|
|
end
|
| 315 |
|
|
end
|
| 316 |
|
|
endgenerate
|
| 317 |
|
|
|
| 318 |
|
|
//***************************************************************************
|
| 319 |
|
|
// DQ IOB instances
|
| 320 |
|
|
//***************************************************************************
|
| 321 |
|
|
|
| 322 |
|
|
genvar dq_i;
|
| 323 |
|
|
generate
|
| 324 |
|
|
for(dq_i = 0; dq_i < DQ_WIDTH; dq_i = dq_i+1) begin: gen_dq
|
| 325 |
|
|
ddr2_phy_dq_iob #
|
| 326 |
|
|
(
|
| 327 |
|
|
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
|
| 328 |
|
|
.IODELAY_GRP (IODELAY_GRP),
|
| 329 |
|
|
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE)
|
| 330 |
|
|
)
|
| 331 |
|
|
u_iob_dq
|
| 332 |
|
|
(
|
| 333 |
|
|
.clk0 (clk0),
|
| 334 |
|
|
.clk90 (clk90),
|
| 335 |
|
|
.clkdiv0 (clkdiv0),
|
| 336 |
|
|
.rst90 (rst90),
|
| 337 |
|
|
.dlyinc (dlyinc_dq[dq_i]),
|
| 338 |
|
|
.dlyce (dlyce_dq[dq_i]),
|
| 339 |
|
|
.dlyrst (dlyrst_dq),
|
| 340 |
|
|
.dq_oe_n (dq_oe_n),
|
| 341 |
|
|
.dqs (delayed_dqs[dq_i/DQ_PER_DQS]),
|
| 342 |
|
|
.ce (dq_ce[dq_i/DQ_PER_DQS]),
|
| 343 |
|
|
.rd_data_sel (rd_data_sel[dq_i/DQ_PER_DQS]),
|
| 344 |
|
|
.wr_data_rise (wr_data_rise[dq_i]),
|
| 345 |
|
|
.wr_data_fall (wr_data_fall[dq_i]),
|
| 346 |
|
|
.rd_data_rise (rd_data_rise[dq_i]),
|
| 347 |
|
|
.rd_data_fall (rd_data_fall[dq_i]),
|
| 348 |
|
|
.ddr_dq (ddr_dq[dq_i])
|
| 349 |
|
|
);
|
| 350 |
|
|
end
|
| 351 |
|
|
endgenerate
|
| 352 |
|
|
|
| 353 |
|
|
endmodule
|
