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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [xilinx_ddr2/] [ddr2_phy_top.v] - Blame information for rev 412

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//*****************************************************************************
2
// DISCLAIMER OF LIABILITY
3
//
4
// This file contains proprietary and confidential information of
5
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
6
// from Xilinx, and may be used, copied and/or disclosed only
7
// pursuant to the terms of a valid license agreement with Xilinx.
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//
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// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
11
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
12
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
13
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
14
// does not warrant that functions included in the Materials will
15
// meet the requirements of Licensee, or that the operation of the
16
// Materials will be uninterrupted or error-free, or that defects
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// in the Materials will be corrected. Furthermore, Xilinx does
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// not warrant or make any representations regarding use, or the
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// results of the use, of the Materials in terms of correctness,
20
// accuracy, reliability or otherwise.
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//
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// Xilinx products are not designed or intended to be fail-safe,
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// or for use in any application requiring fail-safe performance,
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// such as life-support or safety devices or systems, Class III
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// medical devices, nuclear facilities, applications related to
26
// the deployment of airbags, or any other applications that could
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// lead to death, personal injury or severe property or
28
// environmental damage (individually and collectively, "critical
29
// applications"). Customer assumes the sole risk and liability
30
// of any use of Xilinx products in critical applications,
31
// subject only to applicable laws and regulations governing
32
// limitations on product liability.
33
//
34
// Copyright 2006, 2007, 2008 Xilinx, Inc.
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// All rights reserved.
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//
37
// This disclaimer and copyright notice must be retained as part
38
// of this file at all times.
39
//*****************************************************************************
40
//   ____  ____
41
//  /   /\/   /
42
// /___/  \  /    Vendor: Xilinx
43
// \   \   \/     Version: 3.0
44
//  \   \         Application: MIG
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//  /   /         Filename: ddr2_phy_top.v
46
// /___/   /\     Date Last Modified: $Date: 2009/02/03 18:50:12 $
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// \   \  /  \    Date Created: Wed Aug 16 2006
48
//  \___\/\___\
49
//
50
//Device: Virtex-5
51
//Design Name: DDR2
52
//Purpose:
53
//   Top-level for memory physical layer (PHY) interface
54
//Reference:
55
//Revision History:
56
//   Rev 1.1 - Parameter USE_DM_PORT added. PK. 6/25/08
57
//   Rev 1.2 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
58
//   Rev 1.3 - Parameter CS_BITS added. PK. 10/8/08
59
//   Rev 1.4 - Parameter IODELAY_GRP added. PK. 11/27/08
60
//*****************************************************************************
61
 
62
`timescale 1ns/1ps
63
 
64
(* X_CORE_INFO = "mig_v3_0_ddr2_sdram_v5, Coregen 11.1" , CORE_GENERATION_INFO = "ddr2_sdram_v5,mig_v3_0,{component_name=ddr2_phy_top, BANK_WIDTH=2, CKE_WIDTH=1, CLK_WIDTH=2, COL_WIDTH=10, CS_NUM=1, CS_WIDTH=1, DM_WIDTH=8, DQ_WIDTH=64, DQ_PER_DQS=8, DQS_WIDTH=8, ODT_WIDTH=1, ROW_WIDTH=13, ADDITIVE_LAT=0, BURST_LEN=4, BURST_TYPE=0, CAS_LAT=4, ECC_ENABLE=0, MULTI_BANK_EN=1, TWO_T_TIME_EN=1, ODT_TYPE=1, REDUCE_DRV=0, REG_ENABLE=0, TREFI_NS=7800, TRAS=40000, TRCD=15000, TRFC=105000, TRP=15000, TRTP=7500, TWR=15000, TWTR=7500, DDR2_CLK_PERIOD=3750, RST_ACT_LOW=1}" *)
65
module ddr2_phy_top #
66
  (
67
   // Following parameters are for 72-bit RDIMM design (for ML561 Reference
68
   // board design). Actual values may be different. Actual parameters values
69
   // are passed from design top module ddr2_mig module. Please refer to
70
   // the ddr2_mig module for actual values.
71
   parameter BANK_WIDTH            = 2,
72
   parameter CLK_WIDTH             = 1,
73
   parameter CKE_WIDTH             = 1,
74
   parameter COL_WIDTH             = 10,
75
   parameter CS_BITS               = 0,
76
   parameter CS_NUM                = 1,
77
   parameter CS_WIDTH              = 1,
78
   parameter USE_DM_PORT           = 1,
79
   parameter DM_WIDTH              = 9,
80
   parameter DQ_WIDTH              = 72,
81
   parameter DQ_BITS               = 7,
82
   parameter DQ_PER_DQS            = 8,
83
   parameter DQS_WIDTH             = 9,
84
   parameter DQS_BITS              = 4,
85
   parameter HIGH_PERFORMANCE_MODE = "TRUE",
86
   parameter IODELAY_GRP           = "IODELAY_MIG",
87
   parameter ODT_WIDTH             = 1,
88
   parameter ROW_WIDTH             = 14,
89
   parameter ADDITIVE_LAT          = 0,
90
   parameter TWO_T_TIME_EN         = 0,
91
   parameter BURST_LEN             = 4,
92
   parameter BURST_TYPE            = 0,
93
   parameter CAS_LAT               = 5,
94
   parameter TWR                   = 15000,
95
   parameter ECC_ENABLE            = 0,
96
   parameter ODT_TYPE              = 1,
97
   parameter DDR_TYPE              = 1,
98
   parameter REDUCE_DRV            = 0,
99
   parameter REG_ENABLE            = 1,
100
   parameter CLK_PERIOD            = 3000,
101
   parameter SIM_ONLY              = 0,
102
   parameter DEBUG_EN              = 0,
103
   parameter FPGA_SPEED_GRADE      = 2
104
   )
105
  (
106
   input                                  clk0,
107
   input                                  clk90,
108
   input                                  clkdiv0,
109
   input                                  rst0,
110
   input                                  rst90,
111
   input                                  rstdiv0,
112
   input                                  ctrl_wren,
113
   input [ROW_WIDTH-1:0]                  ctrl_addr,
114
   input [BANK_WIDTH-1:0]                 ctrl_ba,
115
   input                                  ctrl_ras_n,
116
   input                                  ctrl_cas_n,
117
   input                                  ctrl_we_n,
118
   input [CS_NUM-1:0]                     ctrl_cs_n,
119
   input                                  ctrl_rden,
120
   input                                  ctrl_ref_flag,
121
   input [(2*DQ_WIDTH)-1:0]               wdf_data,
122
   input [(2*DQ_WIDTH/8)-1:0]             wdf_mask_data,
123
   output                                 wdf_rden,
124
   output                                 phy_init_done,
125
   output [DQS_WIDTH-1:0]                 phy_calib_rden,
126
   output [DQS_WIDTH-1:0]                 phy_calib_rden_sel,
127
   output [DQ_WIDTH-1:0]                  rd_data_rise,
128
   output [DQ_WIDTH-1:0]                  rd_data_fall,
129
   output [CLK_WIDTH-1:0]                 ddr_ck,
130
   output [CLK_WIDTH-1:0]                 ddr_ck_n,
131
   output [ROW_WIDTH-1:0]                 ddr_addr,
132
   output [BANK_WIDTH-1:0]                ddr_ba,
133
   output                                 ddr_ras_n,
134
   output                                 ddr_cas_n,
135
   output                                 ddr_we_n,
136
   output [CS_WIDTH-1:0]                  ddr_cs_n,
137
   output [CKE_WIDTH-1:0]                 ddr_cke,
138
   output [ODT_WIDTH-1:0]                 ddr_odt,
139
   output [DM_WIDTH-1:0]                  ddr_dm,
140
   inout [DQS_WIDTH-1:0]                  ddr_dqs,
141
   inout [DQS_WIDTH-1:0]                  ddr_dqs_n,
142
   inout [DQ_WIDTH-1:0]                   ddr_dq,
143
   // Debug signals (optional use)
144
   input                                  dbg_idel_up_all,
145
   input                                  dbg_idel_down_all,
146
   input                                  dbg_idel_up_dq,
147
   input                                  dbg_idel_down_dq,
148
   input                                  dbg_idel_up_dqs,
149
   input                                  dbg_idel_down_dqs,
150
   input                                  dbg_idel_up_gate,
151
   input                                  dbg_idel_down_gate,
152
   input [DQ_BITS-1:0]                    dbg_sel_idel_dq,
153
   input                                  dbg_sel_all_idel_dq,
154
   input [DQS_BITS:0]                     dbg_sel_idel_dqs,
155
   input                                  dbg_sel_all_idel_dqs,
156
   input [DQS_BITS:0]                     dbg_sel_idel_gate,
157
   input                                  dbg_sel_all_idel_gate,
158
   output [3:0]                           dbg_calib_done,
159
   output [3:0]                           dbg_calib_err,
160
   output [(6*DQ_WIDTH)-1:0]              dbg_calib_dq_tap_cnt,
161
   output [(6*DQS_WIDTH)-1:0]             dbg_calib_dqs_tap_cnt,
162
   output [(6*DQS_WIDTH)-1:0]             dbg_calib_gate_tap_cnt,
163
   output [DQS_WIDTH-1:0]                 dbg_calib_rd_data_sel,
164
   output [(5*DQS_WIDTH)-1:0]             dbg_calib_rden_dly,
165
   output [(5*DQS_WIDTH)-1:0]             dbg_calib_gate_dly
166
   );
167
 
168
  wire [3:0]               calib_done;
169
  wire                     calib_ref_done;
170
  wire                     calib_ref_req;
171
  wire [3:0]               calib_start;
172
  wire                     dm_ce;
173
  wire [1:0]               dq_oe_n;
174
  wire                     dqs_oe_n;
175
  wire                     dqs_rst_n;
176
  wire [(DQ_WIDTH/8)-1:0]  mask_data_fall;
177
  wire [(DQ_WIDTH/8)-1:0]  mask_data_rise;
178
  wire [CS_NUM-1:0]        odt;
179
  wire [ROW_WIDTH-1:0]     phy_init_addr;
180
  wire [BANK_WIDTH-1:0]    phy_init_ba;
181
  wire                     phy_init_cas_n;
182
  wire [CKE_WIDTH-1:0]     phy_init_cke;
183
  wire [CS_NUM-1:0]        phy_init_cs_n;
184
  wire                     phy_init_data_sel;
185
  wire                     phy_init_ras_n;
186
  wire                     phy_init_rden;
187
  wire                     phy_init_we_n;
188
  wire                     phy_init_wren;
189
  wire [DQ_WIDTH-1:0]      wr_data_fall;
190
  wire [DQ_WIDTH-1:0]      wr_data_rise;
191
 
192
  //***************************************************************************
193
 
194
  ddr2_phy_write #
195
    (
196
     .DQ_WIDTH     (DQ_WIDTH),
197
     .CS_NUM       (CS_NUM),
198
     .ADDITIVE_LAT (ADDITIVE_LAT),
199
     .CAS_LAT      (CAS_LAT),
200
     .ECC_ENABLE   (ECC_ENABLE),
201
     .ODT_TYPE     (ODT_TYPE),
202
     .REG_ENABLE   (REG_ENABLE),
203
     .DDR_TYPE     (DDR_TYPE)
204
     )
205
    u_phy_write
206
      (
207
       .clk0                    (clk0),
208
       .clk90                   (clk90),
209
       .rst90                   (rst90),
210
       .wdf_data                (wdf_data),
211
       .wdf_mask_data           (wdf_mask_data),
212
       .ctrl_wren               (ctrl_wren),
213
       .phy_init_wren           (phy_init_wren),
214
       .phy_init_data_sel       (phy_init_data_sel),
215
       .dm_ce                   (dm_ce),
216
       .dq_oe_n                 (dq_oe_n),
217
       .dqs_oe_n                (dqs_oe_n),
218
       .dqs_rst_n               (dqs_rst_n),
219
       .wdf_rden                (wdf_rden),
220
       .odt                     (odt),
221
       .wr_data_rise            (wr_data_rise),
222
       .wr_data_fall            (wr_data_fall),
223
       .mask_data_rise          (mask_data_rise),
224
       .mask_data_fall          (mask_data_fall)
225
       );
226
 
227
  ddr2_phy_io #
228
    (
229
     .CLK_WIDTH             (CLK_WIDTH),
230
     .USE_DM_PORT           (USE_DM_PORT),
231
     .DM_WIDTH              (DM_WIDTH),
232
     .DQ_WIDTH              (DQ_WIDTH),
233
     .DQ_BITS               (DQ_BITS),
234
     .DQ_PER_DQS            (DQ_PER_DQS),
235
     .DQS_BITS              (DQS_BITS),
236
     .DQS_WIDTH             (DQS_WIDTH),
237
     .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
238
     .IODELAY_GRP           (IODELAY_GRP),
239
     .ODT_WIDTH             (ODT_WIDTH),
240
     .ADDITIVE_LAT          (ADDITIVE_LAT),
241
     .CAS_LAT               (CAS_LAT),
242
     .REG_ENABLE            (REG_ENABLE),
243
     .CLK_PERIOD            (CLK_PERIOD),
244
     .DDR_TYPE              (DDR_TYPE),
245
     .SIM_ONLY              (SIM_ONLY),
246
     .DEBUG_EN              (DEBUG_EN),
247
     .FPGA_SPEED_GRADE      (FPGA_SPEED_GRADE)
248
     )
249
    u_phy_io
250
      (
251
       .clk0                   (clk0),
252
       .clk90                  (clk90),
253
       .clkdiv0                (clkdiv0),
254
       .rst0                   (rst0),
255
       .rst90                  (rst90),
256
       .rstdiv0                (rstdiv0),
257
       .dm_ce                  (dm_ce),
258
       .dq_oe_n                (dq_oe_n),
259
       .dqs_oe_n               (dqs_oe_n),
260
       .dqs_rst_n              (dqs_rst_n),
261
       .calib_start            (calib_start),
262
       .ctrl_rden              (ctrl_rden),
263
       .phy_init_rden          (phy_init_rden),
264
       .calib_ref_done         (calib_ref_done),
265
       .calib_done             (calib_done),
266
       .calib_ref_req          (calib_ref_req),
267
       .calib_rden             (phy_calib_rden),
268
       .calib_rden_sel         (phy_calib_rden_sel),
269
       .wr_data_rise           (wr_data_rise),
270
       .wr_data_fall           (wr_data_fall),
271
       .mask_data_rise         (mask_data_rise),
272
       .mask_data_fall         (mask_data_fall),
273
       .rd_data_rise           (rd_data_rise),
274
       .rd_data_fall           (rd_data_fall),
275
       .ddr_ck                 (ddr_ck),
276
       .ddr_ck_n               (ddr_ck_n),
277
       .ddr_dm                 (ddr_dm),
278
       .ddr_dqs                (ddr_dqs),
279
       .ddr_dqs_n              (ddr_dqs_n),
280
       .ddr_dq                 (ddr_dq),
281
       .dbg_idel_up_all        (dbg_idel_up_all),
282
       .dbg_idel_down_all      (dbg_idel_down_all),
283
       .dbg_idel_up_dq         (dbg_idel_up_dq),
284
       .dbg_idel_down_dq       (dbg_idel_down_dq),
285
       .dbg_idel_up_dqs        (dbg_idel_up_dqs),
286
       .dbg_idel_down_dqs      (dbg_idel_down_dqs),
287
       .dbg_idel_up_gate       (dbg_idel_up_gate),
288
       .dbg_idel_down_gate     (dbg_idel_down_gate),
289
       .dbg_sel_idel_dq        (dbg_sel_idel_dq),
290
       .dbg_sel_all_idel_dq    (dbg_sel_all_idel_dq),
291
       .dbg_sel_idel_dqs       (dbg_sel_idel_dqs),
292
       .dbg_sel_all_idel_dqs   (dbg_sel_all_idel_dqs),
293
       .dbg_sel_idel_gate      (dbg_sel_idel_gate),
294
       .dbg_sel_all_idel_gate  (dbg_sel_all_idel_gate),
295
       .dbg_calib_done         (dbg_calib_done),
296
       .dbg_calib_err          (dbg_calib_err),
297
       .dbg_calib_dq_tap_cnt   (dbg_calib_dq_tap_cnt),
298
       .dbg_calib_dqs_tap_cnt  (dbg_calib_dqs_tap_cnt),
299
       .dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
300
       .dbg_calib_rd_data_sel  (dbg_calib_rd_data_sel),
301
       .dbg_calib_rden_dly     (dbg_calib_rden_dly),
302
       .dbg_calib_gate_dly     (dbg_calib_gate_dly)
303
       );
304
 
305
  ddr2_phy_ctl_io #
306
    (
307
     .BANK_WIDTH    (BANK_WIDTH),
308
     .CKE_WIDTH     (CKE_WIDTH),
309
     .COL_WIDTH     (COL_WIDTH),
310
     .CS_NUM        (CS_NUM),
311
     .CS_WIDTH      (CS_WIDTH),
312
     .TWO_T_TIME_EN (TWO_T_TIME_EN),
313
     .ODT_WIDTH     (ODT_WIDTH),
314
     .ROW_WIDTH     (ROW_WIDTH),
315
     .DDR_TYPE      (DDR_TYPE)
316
     )
317
    u_phy_ctl_io
318
      (
319
       .clk0                    (clk0),
320
       .clk90                   (clk90),
321
       .rst0                    (rst0),
322
       .rst90                   (rst90),
323
       .ctrl_addr               (ctrl_addr),
324
       .ctrl_ba                 (ctrl_ba),
325
       .ctrl_ras_n              (ctrl_ras_n),
326
       .ctrl_cas_n              (ctrl_cas_n),
327
       .ctrl_we_n               (ctrl_we_n),
328
       .ctrl_cs_n               (ctrl_cs_n),
329
       .phy_init_addr           (phy_init_addr),
330
       .phy_init_ba             (phy_init_ba),
331
       .phy_init_ras_n          (phy_init_ras_n),
332
       .phy_init_cas_n          (phy_init_cas_n),
333
       .phy_init_we_n           (phy_init_we_n),
334
       .phy_init_cs_n           (phy_init_cs_n),
335
       .phy_init_cke            (phy_init_cke),
336
       .phy_init_data_sel       (phy_init_data_sel),
337
       .odt                     (odt),
338
       .ddr_addr                (ddr_addr),
339
       .ddr_ba                  (ddr_ba),
340
       .ddr_ras_n               (ddr_ras_n),
341
       .ddr_cas_n               (ddr_cas_n),
342
       .ddr_we_n                (ddr_we_n),
343
       .ddr_cke                 (ddr_cke),
344
       .ddr_cs_n                (ddr_cs_n),
345
       .ddr_odt                 (ddr_odt)
346
       );
347
 
348
  ddr2_phy_init #
349
    (
350
     .BANK_WIDTH   (BANK_WIDTH),
351
     .CKE_WIDTH    (CKE_WIDTH),
352
     .COL_WIDTH    (COL_WIDTH),
353
     .CS_BITS      (CS_BITS),
354
     .CS_NUM       (CS_NUM),
355
     .DQ_WIDTH     (DQ_WIDTH),
356
     .ODT_WIDTH    (ODT_WIDTH),
357
     .ROW_WIDTH    (ROW_WIDTH),
358
     .ADDITIVE_LAT (ADDITIVE_LAT),
359
     .BURST_LEN    (BURST_LEN),
360
     .BURST_TYPE   (BURST_TYPE),
361
     .TWO_T_TIME_EN(TWO_T_TIME_EN),
362
     .CAS_LAT      (CAS_LAT),
363
     .ODT_TYPE     (ODT_TYPE),
364
     .REDUCE_DRV   (REDUCE_DRV),
365
     .REG_ENABLE   (REG_ENABLE),
366
     .TWR          (TWR),
367
     .CLK_PERIOD   (CLK_PERIOD),
368
     .DDR_TYPE     (DDR_TYPE),
369
     .SIM_ONLY     (SIM_ONLY)
370
     )
371
    u_phy_init
372
      (
373
       .clk0                    (clk0),
374
       .clkdiv0                 (clkdiv0),
375
       .rst0                    (rst0),
376
       .rstdiv0                 (rstdiv0),
377
       .calib_done              (calib_done),
378
       .ctrl_ref_flag           (ctrl_ref_flag),
379
       .calib_ref_req           (calib_ref_req),
380
       .calib_start             (calib_start),
381
       .calib_ref_done          (calib_ref_done),
382
       .phy_init_wren           (phy_init_wren),
383
       .phy_init_rden           (phy_init_rden),
384
       .phy_init_addr           (phy_init_addr),
385
       .phy_init_ba             (phy_init_ba),
386
       .phy_init_ras_n          (phy_init_ras_n),
387
       .phy_init_cas_n          (phy_init_cas_n),
388
       .phy_init_we_n           (phy_init_we_n),
389
       .phy_init_cs_n           (phy_init_cs_n),
390
       .phy_init_cke            (phy_init_cke),
391
       .phy_init_done           (phy_init_done),
392
       .phy_init_data_sel       (phy_init_data_sel)
393
       );
394
 
395
endmodule

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