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//*****************************************************************************
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// DISCLAIMER OF LIABILITY
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//
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// This file contains proprietary and confidential information of
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// Xilinx, Inc. ("Xilinx"), that is distributed under a license
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// from Xilinx, and may be used, copied and/or disclosed only
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// pursuant to the terms of a valid license agreement with Xilinx.
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//
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// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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// does not warrant that functions included in the Materials will
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// meet the requirements of Licensee, or that the operation of the
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// Materials will be uninterrupted or error-free, or that defects
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// in the Materials will be corrected. Furthermore, Xilinx does
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// not warrant or make any representations regarding use, or the
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// results of the use, of the Materials in terms of correctness,
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// accuracy, reliability or otherwise.
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//
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// Xilinx products are not designed or intended to be fail-safe,
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// or for use in any application requiring fail-safe performance,
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// such as life-support or safety devices or systems, Class III
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// medical devices, nuclear facilities, applications related to
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// the deployment of airbags, or any other applications that could
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// lead to death, personal injury or severe property or
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// environmental damage (individually and collectively, "critical
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// applications"). Customer assumes the sole risk and liability
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// of any use of Xilinx products in critical applications,
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// subject only to applicable laws and regulations governing
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// limitations on product liability.
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//
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// Copyright 2006, 2007, 2008 Xilinx, Inc.
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// All rights reserved.
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//
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// This disclaimer and copyright notice must be retained as part
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// of this file at all times.
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: 3.0
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// \ \ Application: MIG
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// / / Filename: ddr2_top.v
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// /___/ /\ Date Last Modified: $Date: 2009/01/15 14:22:14 $
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// \ \ / \ Date Created: Wed Aug 16 2006
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// \___\/\___\
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//
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//Device: Virtex-5
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//Design Name: DDR2
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//Purpose:
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// System level module. This level contains just the memory controller.
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// This level will be intiantated when the user wants to remove the
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// synthesizable test bench, IDELAY control block and the clock
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// generation modules.
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//Reference:
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//Revision History:
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// Rev 1.1 - Parameter USE_DM_PORT added. PK. 6/25/08
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// Rev 1.2 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
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// Rev 1.3 - Parameter IODELAY_GRP added. PK. 11/27/08
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//*****************************************************************************
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`timescale 1ns/1ps
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module ddr2_top #
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(
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// Following parameters are for 72-bit RDIMM design (for ML561 Reference
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// board design). Actual values may be different. Actual parameters values
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// are passed from design top module ddr2_mig module. Please refer to
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// the ddr2_mig module for actual values.
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parameter BANK_WIDTH = 2, // # of memory bank addr bits
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parameter CKE_WIDTH = 1, // # of memory clock enable outputs
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parameter CLK_WIDTH = 1, // # of clock outputs
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parameter COL_WIDTH = 10, // # of memory column bits
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parameter CS_NUM = 1, // # of separate memory chip selects
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parameter CS_BITS = 0, // set to log2(CS_NUM) (rounded up)
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parameter CS_WIDTH = 1, // # of total memory chip selects
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parameter USE_DM_PORT = 1, // enable Data Mask (=1 enable)
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parameter DM_WIDTH = 9, // # of data mask bits
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parameter DQ_WIDTH = 72, // # of data width
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parameter DQ_BITS = 7, // set to log2(DQS_WIDTH*DQ_PER_DQS)
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parameter DQ_PER_DQS = 8, // # of DQ data bits per strobe
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parameter DQS_WIDTH = 9, // # of DQS strobes
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parameter DQS_BITS = 4, // set to log2(DQS_WIDTH)
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parameter HIGH_PERFORMANCE_MODE = "TRUE", // IODELAY Performance Mode
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parameter IODELAY_GRP = "IODELAY_MIG", // IODELAY Group Name
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parameter ODT_WIDTH = 1, // # of memory on-die term enables
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parameter ROW_WIDTH = 14, // # of memory row & # of addr bits
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parameter APPDATA_WIDTH = 144, // # of usr read/write data bus bits
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parameter ADDITIVE_LAT = 0, // additive write latency
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parameter BURST_LEN = 4, // burst length (in double words)
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parameter BURST_TYPE = 0, // burst type (=0 seq; =1 interlved)
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parameter CAS_LAT = 5, // CAS latency
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parameter ECC_ENABLE = 0, // enable ECC (=1 enable)
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parameter ODT_TYPE = 1, // ODT (=0(none),=1(75),=2(150),=3(50))
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parameter MULTI_BANK_EN = 1, // enable bank management
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parameter TWO_T_TIME_EN = 0, // 2t timing for unbuffered dimms
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parameter REDUCE_DRV = 0, // reduced strength mem I/O (=1 yes)
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parameter REG_ENABLE = 1, // registered addr/ctrl (=1 yes)
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parameter TREFI_NS = 7800, // auto refresh interval (ns)
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parameter TRAS = 40000, // active->precharge delay
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parameter TRCD = 15000, // active->read/write delay
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parameter TRFC = 105000, // ref->ref, ref->active delay
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parameter TRP = 15000, // precharge->command delay
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parameter TRTP = 7500, // read->precharge delay
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parameter TWR = 15000, // used to determine wr->prech
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parameter TWTR = 10000, // write->read delay
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parameter CLK_PERIOD = 3000, // Core/Mem clk period (in ps)
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parameter SIM_ONLY = 0, // = 1 to skip power up delay
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parameter DEBUG_EN = 0, // Enable debug signals/controls
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parameter FPGA_SPEED_GRADE = 2 // FPGA Speed Grade
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)
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(
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input clk0,
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input usr_clk, // jb
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input clk90,
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input clkdiv0,
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input rst0,
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input rst90,
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input rstdiv0,
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input [2:0] app_af_cmd,
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input [30:0] app_af_addr,
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input app_af_wren,
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input app_wdf_wren,
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input [APPDATA_WIDTH-1:0] app_wdf_data,
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input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
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output app_af_afull,
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output app_wdf_afull,
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output rd_data_valid,
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output [APPDATA_WIDTH-1:0] rd_data_fifo_out,
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output [1:0] rd_ecc_error,
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output phy_init_done,
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output [CLK_WIDTH-1:0] ddr2_ck,
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output [CLK_WIDTH-1:0] ddr2_ck_n,
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output [ROW_WIDTH-1:0] ddr2_a,
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output [BANK_WIDTH-1:0] ddr2_ba,
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output ddr2_ras_n,
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output ddr2_cas_n,
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output ddr2_we_n,
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output [CS_WIDTH-1:0] ddr2_cs_n,
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output [CKE_WIDTH-1:0] ddr2_cke,
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output [ODT_WIDTH-1:0] ddr2_odt,
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output [DM_WIDTH-1:0] ddr2_dm,
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inout [DQS_WIDTH-1:0] ddr2_dqs,
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inout [DQS_WIDTH-1:0] ddr2_dqs_n,
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inout [DQ_WIDTH-1:0] ddr2_dq,
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// Debug signals (optional use)
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input dbg_idel_up_all,
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input dbg_idel_down_all,
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input dbg_idel_up_dq,
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input dbg_idel_down_dq,
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input dbg_idel_up_dqs,
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input dbg_idel_down_dqs,
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input dbg_idel_up_gate,
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input dbg_idel_down_gate,
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input [DQ_BITS-1:0] dbg_sel_idel_dq,
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input dbg_sel_all_idel_dq,
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input [DQS_BITS:0] dbg_sel_idel_dqs,
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input dbg_sel_all_idel_dqs,
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input [DQS_BITS:0] dbg_sel_idel_gate,
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input dbg_sel_all_idel_gate,
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output [3:0] dbg_calib_done,
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output [3:0] dbg_calib_err,
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output [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt,
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output [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt,
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output [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt,
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output [DQS_WIDTH-1:0] dbg_calib_rd_data_sel,
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output [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly,
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output [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly
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);
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// memory initialization/control logic
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ddr2_mem_if_top #
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(
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.BANK_WIDTH (BANK_WIDTH),
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.CKE_WIDTH (CKE_WIDTH),
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.CLK_WIDTH (CLK_WIDTH),
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.COL_WIDTH (COL_WIDTH),
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.CS_BITS (CS_BITS),
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.CS_NUM (CS_NUM),
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.CS_WIDTH (CS_WIDTH),
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.USE_DM_PORT (USE_DM_PORT),
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.DM_WIDTH (DM_WIDTH),
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.DQ_WIDTH (DQ_WIDTH),
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.DQ_BITS (DQ_BITS),
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.DQ_PER_DQS (DQ_PER_DQS),
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.DQS_BITS (DQS_BITS),
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.DQS_WIDTH (DQS_WIDTH),
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.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
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.IODELAY_GRP (IODELAY_GRP),
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.ODT_WIDTH (ODT_WIDTH),
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.ROW_WIDTH (ROW_WIDTH),
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.APPDATA_WIDTH (APPDATA_WIDTH),
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.ADDITIVE_LAT (ADDITIVE_LAT),
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.BURST_LEN (BURST_LEN),
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.BURST_TYPE (BURST_TYPE),
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.CAS_LAT (CAS_LAT),
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.ECC_ENABLE (ECC_ENABLE),
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.MULTI_BANK_EN (MULTI_BANK_EN),
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.TWO_T_TIME_EN (TWO_T_TIME_EN),
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.ODT_TYPE (ODT_TYPE),
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.DDR_TYPE (1),
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.REDUCE_DRV (REDUCE_DRV),
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.REG_ENABLE (REG_ENABLE),
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.TREFI_NS (TREFI_NS),
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.TRAS (TRAS),
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.TRCD (TRCD),
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.TRFC (TRFC),
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.TRP (TRP),
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.TRTP (TRTP),
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.TWR (TWR),
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.TWTR (TWTR),
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.CLK_PERIOD (CLK_PERIOD),
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.SIM_ONLY (SIM_ONLY),
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.DEBUG_EN (DEBUG_EN),
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.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE)
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)
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u_mem_if_top
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(
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.clk0 (clk0),
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.usr_clk (usr_clk), // jb
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.clk90 (clk90),
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.clkdiv0 (clkdiv0),
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.rst0 (rst0),
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.rst90 (rst90),
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.rstdiv0 (rstdiv0),
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.app_af_cmd (app_af_cmd),
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.app_af_addr (app_af_addr),
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.app_af_wren (app_af_wren),
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.app_wdf_wren (app_wdf_wren),
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.app_wdf_data (app_wdf_data),
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.app_wdf_mask_data (app_wdf_mask_data),
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.app_af_afull (app_af_afull),
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.app_wdf_afull (app_wdf_afull),
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.rd_data_valid (rd_data_valid),
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.rd_data_fifo_out (rd_data_fifo_out),
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.rd_ecc_error (rd_ecc_error),
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.phy_init_done (phy_init_done),
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.ddr_ck (ddr2_ck),
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.ddr_ck_n (ddr2_ck_n),
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.ddr_addr (ddr2_a),
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.ddr_ba (ddr2_ba),
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.ddr_ras_n (ddr2_ras_n),
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.ddr_cas_n (ddr2_cas_n),
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.ddr_we_n (ddr2_we_n),
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.ddr_cs_n (ddr2_cs_n),
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.ddr_cke (ddr2_cke),
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.ddr_odt (ddr2_odt),
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.ddr_dm (ddr2_dm),
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.ddr_dqs (ddr2_dqs),
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.ddr_dqs_n (ddr2_dqs_n),
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.ddr_dq (ddr2_dq),
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.dbg_idel_up_all (dbg_idel_up_all),
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.dbg_idel_down_all (dbg_idel_down_all),
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.dbg_idel_up_dq (dbg_idel_up_dq),
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.dbg_idel_down_dq (dbg_idel_down_dq),
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| 258 |
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.dbg_idel_up_dqs (dbg_idel_up_dqs),
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| 259 |
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.dbg_idel_down_dqs (dbg_idel_down_dqs),
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| 260 |
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.dbg_idel_up_gate (dbg_idel_up_gate),
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.dbg_idel_down_gate (dbg_idel_down_gate),
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| 262 |
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.dbg_sel_idel_dq (dbg_sel_idel_dq),
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| 263 |
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.dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),
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| 264 |
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.dbg_sel_idel_dqs (dbg_sel_idel_dqs),
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| 265 |
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.dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),
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| 266 |
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.dbg_sel_idel_gate (dbg_sel_idel_gate),
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| 267 |
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.dbg_sel_all_idel_gate (dbg_sel_all_idel_gate),
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| 268 |
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.dbg_calib_done (dbg_calib_done),
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.dbg_calib_err (dbg_calib_err),
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.dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),
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.dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),
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.dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
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.dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),
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.dbg_calib_rden_dly (dbg_calib_rden_dly),
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.dbg_calib_gate_dly (dbg_calib_gate_dly)
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);
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endmodule
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