URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [sim/] [bin/] [Makefile] - Blame information for rev 280

Go to most recent revision | Details | Compare with Previous | View Log


# Include file for tools, etc (mainly interested in the Xilinx path here)
include ../../../../tools.inc
 
ORPSOC_ROOT=../../../../..
BOARD=ml501
 
CUR_DIR=$(shell pwd)
# The root path of the whole project
PROJECT_ROOT =$(CUR_DIR)/$(ORPSOC_ROOT)
 
SIM_DIR=$(CUR_DIR)/../../sim
 
BOARD_BENCH_DIR=$(CUR_DIR)/../../bench
BOARD_RTL_DIR=$(CUR_DIR)/../../rtl
BOARD_SW_DIR=$(CUR_DIR)/../../sw
BOARD_SYN_DIR=$(CUR_DIR)/../../syn
 
 
# Important!
RTL_TESTBENCH_TOP=ml501_testbench
BENCH_TOP_VERILOG_DIR=$(BOARD_BENCH_DIR)
 
# Extra defines passed to testbench compilation
# Used here for DDR2 model defines
EXTRA_BENCH_DEFINES=+define+sg37E +define+x16
 
#MEMORY_MODELS=$(BENCH_VERILOG_DIR)/cy7c1354.v $(BENCH_VERILOG_DIR)/ddr2_model.v
 
SIMULATOR=vsim
 
RTL_VERILOG_INCLUDE_DIR =$(BOARD_RTL_DIR)
 
 
include $(ORPSOC_ROOT)/sim/bin/Makefile
 
 
ifeq ($(VCD), 1)
VOPT_ARGS=+acc=rnp
endif
 
 
# Here we re-define the modelsim compilation variable, changing include dirs
# so we use the includes/defines from the board's rtl path instead of the
# normal orpsocv2 bench path.
 
 
# Modelsim testench compilation - we change this from the standard makefile
# to change:
# 1) The include directory (should be the board RTL path, not the main RTL path)
# 2) Change the define for the name of the top testbench (board dependent)
# 3) Add the board's testbench paths
# 4) Add the various extra memory models we use (maybe should just use a script for this instead? TODO!)
VSIM_COMPILE_TB = vlog $(BENCH_VERILOG_DIR)/or1200_monitor.v $(BENCH_TOP_VERILOG_DIR)/$(RTL_TESTBENCH_TOP).v
VSIM_COMPILE_TB += +incdir+$(BENCH_VERILOG_DIR) +incdir+$(BENCH_TOP_VERILOG_DIR) +incdir+$(BOARD_RTL_DIR) +incdir+$(XILINX_VERILOG_SRC)
VSIM_COMPILE_TB += +define+TEST_DEFINE_FILE
VSIM_COMPILE_TB += +define+OR1200_TOP=$(RTL_TESTBENCH_TOP).dut.i_or1k.i_or1200_top
VSIM_COMPILE_TB += +define+TESTBENCH_DEFINES=\"$(RTL_TESTBENCH_TOP)_defines.v\"
VSIM_COMPILE_TB += -y $(BENCH_VERILOG_DIR) -y $(BOARD_BENCH_DIR) +libext+.v
VSIM_COMPILE_TB += $(EXTRA_BENCH_DEFINES)
 
VOPT_STEP=vopt -quiet $(VOPT_ARGS) glbl $(RTL_TESTBENCH_TOP) -L $(MGC_ORPSOC_LIB) -o testbench
SIM_COMMANDRUN= $(VSIM_COMPILE_TB); $(VOPT_STEP); $(VSIM) -c -quiet +nowarnTFMPC -L $(MGC_ORPSOC_LIB)  -do "run -all; exit" testbench
 
# Re-define the command-file generation rule - we add a few extra things to
# our scripts to tell the simulator where the Xilinx tools, other set of
# includes, etc.
$(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE): $(SIM_BIN_DIR)/$(SIM_COMMANDFILE)
        $(Q)sed < $(SIM_BIN_DIR)/$(SIM_COMMANDFILE) > $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) \
                -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
                -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
                -e s!\$$BOARD_BENCH_DIR!$(BOARD_BENCH_DIR)!          \
                -e s!\$$BOARD_RTL_DIR!$(BOARD_RTL_DIR)!              \
                -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
                -e s!\$$XILINX_VERILOG_SRC!$(XILINX_VERILOG_SRC)!    \
                -e \\!^//.*\$$!d -e \\!^\$$!d ; \
        echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
        if [ ! -z $$VCD ]; \
                then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
                if [ $(SIMULATOR) = $(NCVERILOG) ]; \
                        then echo "+access+r" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
                fi; \
        fi; \
        if [ ! -z $$UART_PRINTF ]; \
                then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
        fi; \
        if [ $(SIMULATOR) = $(NCVERILOG) ]; \
                then echo "+nocopyright" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
                echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
        fi
 
 
 
# A new set of tests for software which will run only on this board
# eth board test doesn't quit properly for some reason
BOARD_TESTS=boot memtest gpio
 
rtl-board-tests: $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) prepare-sw prepare-rtl prepare-dirs
        @echo
        @echo "Beginning loop that will complete the following tests for $(BOARD) board: $(BOARD_TESTS)"
        @echo
        $(Q)for TEST in $(BOARD_TESTS); do \
                echo "################################################################################"; \
                echo; \
                echo "\t#### Current test: $$TEST ####"; echo; \
                echo "\t#### Compiling software ####"; echo; \
                CURRENT_TEST_SW_DIR=$(BOARD_SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
                $(MAKE) -C $$CURRENT_TEST_SW_DIR clean $$TEST $(TEST_SW_MAKE_OPTS); \
                rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
                echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
                echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
                if [ ! -z $$VCD ]; \
                        then echo "\`define VCD" >> $(SIM_RUN_DIR)/test_define.v; \
                fi; \
                if [ ! -z $$UART_PRINTF ]; \
                        then echo "\`define UART_PRINTF" >> $(SIM_RUN_DIR)/test_define.v; \
                fi; \
                if [ -z $$NO_SIM_LOGGING ]; then \
                        echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
                fi; \
                echo ; \
                echo "\t#### Compiling RTL ####"; \
                $(SIM_COMMANDCOMPILE); \
                echo; \
                echo "\t#### Beginning simulation ####"; \
                time -p $(SIM_COMMANDRUN) ; \
                if [ $$? -gt 0 ]; then exit $$?; fi; \
                TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
                echo; echo "\t####"; \
                if [ $$TEST_RESULT -gt 0 ]; then \
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
                else    echo "\t#### Test $$TEST FAILED ####";\
                fi; \
                echo "\t####"; echo; \
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
        done; \
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
 
 
SYN_SIM_COMMANDCOMPILE=if [ ! -e work ]; then vlib work; vlib $(MGC_ORPSOC_LIB); vlog -work $(MGC_ORPSOC_LIB) +libext+.v -y $(XILINX_VERILOG_SRC) +incdir+$(XILINX_VERILOG_SRC) -y $(XILINX_VERILOG_SRC)/unisims +incdir+$(XILINX_VERILOG_SRC)/unisims -y $(XILINX_VERILOG_SRC)/XilinxCoreLib +incdir+$(XILINX_VERILOG_SRC)/XilinxCoreLib $(BOARD_SYN_DIR)/$(BOARD).v $(BOARD_RTL_DIR)/ml501_ddr2_wb_if_cache.v ; fi
syn-board-test:  prepare-dirs $(BOARD_SYN_DIR)/$(BOARD).v
        $(Q)echo "\`define TEST_NAME_STRING \"ml501-post-synthesis\"" > $(SIM_RUN_DIR)/test_define.v; \
        echo "\`define POST_SYNTHESIS_SIM" >> $(SIM_RUN_DIR)/test_define.v; \
 
        echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
        if [ ! -z $$VCD ]; \
                then echo "\`define VCD" >> $(SIM_RUN_DIR)/test_define.v; \
                if [ ! -z $$VCD_DEPTH ]; \
                        then echo "\`define VCD_DEPTH "$(VCD_DEPTH) >> $(SIM_RUN_DIR)/test_define.v; \
                fi; \
        fi; \
        if [ ! -z $$UART_PRINTF ]; \
                then echo "\`define UART_PRINTF" >> $(SIM_RUN_DIR)/test_define.v; \
        fi; \
        echo "\t#### Compiling RTL ####"; \
        $(SYN_SIM_COMMANDCOMPILE); \
        echo; \
        echo "\t#### Beginning simulation ####"; \
        time -p $(SIM_COMMANDRUN) ; \
        echo

Line No.	Rev	Author	Line
1	67	julius	`# Include file for tools, etc (mainly interested in the Xilinx path here)`
2			`include ../../../../tools.inc`
3
4			`ORPSOC_ROOT=../../../../..`
5			`BOARD=ml501`
6
7			`CUR_DIR=$(shell pwd)`
8			`# The root path of the whole project`
9			`PROJECT_ROOT =$(CUR_DIR)/$(ORPSOC_ROOT)`
10
11			`SIM_DIR=$(CUR_DIR)/../../sim`
12
13			`BOARD_BENCH_DIR=$(CUR_DIR)/../../bench`
14			`BOARD_RTL_DIR=$(CUR_DIR)/../../rtl`
15			`BOARD_SW_DIR=$(CUR_DIR)/../../sw`
16			`BOARD_SYN_DIR=$(CUR_DIR)/../../syn`
17
18
19			`# Important!`
20			`RTL_TESTBENCH_TOP=ml501_testbench`
21			`BENCH_TOP_VERILOG_DIR=$(BOARD_BENCH_DIR)`
22
23			`# Extra defines passed to testbench compilation`
24			`# Used here for DDR2 model defines`
25			`EXTRA_BENCH_DEFINES=+define+sg37E +define+x16`
26
27			`#MEMORY_MODELS=$(BENCH_VERILOG_DIR)/cy7c1354.v $(BENCH_VERILOG_DIR)/ddr2_model.v`
28
29			`SIMULATOR=vsim`
30
31			`RTL_VERILOG_INCLUDE_DIR =$(BOARD_RTL_DIR)`
32
33
34			`include $(ORPSOC_ROOT)/sim/bin/Makefile`
35
36
37			`ifeq ($(VCD), 1)`
38			`VOPT_ARGS=+acc=rnp`
39			`endif`
40
41
42			`# Here we re-define the modelsim compilation variable, changing include dirs`
43			`# so we use the includes/defines from the board's rtl path instead of the`
44			`# normal orpsocv2 bench path.`
45
46
47			`# Modelsim testench compilation - we change this from the standard makefile`
48			`# to change:`
49			`# 1) The include directory (should be the board RTL path, not the main RTL path)`
50			`# 2) Change the define for the name of the top testbench (board dependent)`
51			`# 3) Add the board's testbench paths`
52			`# 4) Add the various extra memory models we use (maybe should just use a script for this instead? TODO!)`
53			`VSIM_COMPILE_TB = vlog $(BENCH_VERILOG_DIR)/or1200_monitor.v $(BENCH_TOP_VERILOG_DIR)/$(RTL_TESTBENCH_TOP).v`
54			`VSIM_COMPILE_TB += +incdir+$(BENCH_VERILOG_DIR) +incdir+$(BENCH_TOP_VERILOG_DIR) +incdir+$(BOARD_RTL_DIR) +incdir+$(XILINX_VERILOG_SRC)`
55			`VSIM_COMPILE_TB += +define+TEST_DEFINE_FILE`
56			`VSIM_COMPILE_TB += +define+OR1200_TOP=$(RTL_TESTBENCH_TOP).dut.i_or1k.i_or1200_top`
57			`VSIM_COMPILE_TB += +define+TESTBENCH_DEFINES=\"$(RTL_TESTBENCH_TOP)_defines.v\"`
58			`VSIM_COMPILE_TB += -y $(BENCH_VERILOG_DIR) -y $(BOARD_BENCH_DIR) +libext+.v`
59			`VSIM_COMPILE_TB += $(EXTRA_BENCH_DEFINES)`
60
61			`VOPT_STEP=vopt -quiet $(VOPT_ARGS) glbl $(RTL_TESTBENCH_TOP) -L $(MGC_ORPSOC_LIB) -o testbench`
62			`SIM_COMMANDRUN= $(VSIM_COMPILE_TB); $(VOPT_STEP); $(VSIM) -c -quiet +nowarnTFMPC -L $(MGC_ORPSOC_LIB) -do "run -all; exit" testbench`
63
64			`# Re-define the command-file generation rule - we add a few extra things to`
65			`# our scripts to tell the simulator where the Xilinx tools, other set of`
66			`# includes, etc.`
67			`$(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE): $(SIM_BIN_DIR)/$(SIM_COMMANDFILE)`
68			`$(Q)sed < $(SIM_BIN_DIR)/$(SIM_COMMANDFILE) > $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) \`
69			`-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \`
70			`-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \`
71			`-e s!\$$BOARD_BENCH_DIR!$(BOARD_BENCH_DIR)! \`
72			`-e s!\$$BOARD_RTL_DIR!$(BOARD_RTL_DIR)! \`
73			`-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \`
74			`-e s!\$$XILINX_VERILOG_SRC!$(XILINX_VERILOG_SRC)! \`
75			`-e \\!^//.*\$$!d -e \\!^\$$!d ; \`
76			`echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \`
77			`if [ ! -z $$VCD ]; \`
78			`then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \`
79			`if [ $(SIMULATOR) = $(NCVERILOG) ]; \`
80			`then echo "+access+r" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \`
81			`fi; \`
82			`fi; \`
83			`if [ ! -z $$UART_PRINTF ]; \`
84			`then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \`
85			`fi; \`
86			`if [ $(SIMULATOR) = $(NCVERILOG) ]; \`
87			`then echo "+nocopyright" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \`
88			`echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \`
89			`fi`
90
91
92
93			`# A new set of tests for software which will run only on this board`
94	71	julius	`# eth board test doesn't quit properly for some reason`
95			`BOARD_TESTS=boot memtest gpio`
96	67	julius
97			`rtl-board-tests: $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) prepare-sw prepare-rtl prepare-dirs`
98			`@echo`
99			`@echo "Beginning loop that will complete the following tests for $(BOARD) board: $(BOARD_TESTS)"`
100			`@echo`
101			`$(Q)for TEST in $(BOARD_TESTS); do \`
102			`echo "################################################################################"; \`
103			`echo; \`
104			`echo "\t#### Current test: $$TEST ####"; echo; \`
105			`echo "\t#### Compiling software ####"; echo; \`
106			CURRENT_TEST_SW_DIR=$(BOARD_SW_DIR)/`echo $$TEST \| cut -d "-" -f 1`; \
107			`$(MAKE) -C $$CURRENT_TEST_SW_DIR clean $$TEST $(TEST_SW_MAKE_OPTS); \`
108			`rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \`
109			`rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \`
110			`ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \`
111			echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
112			echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
113			`if [ ! -z $$VCD ]; \`
114			then echo "\`define VCD" >> $(SIM_RUN_DIR)/test_define.v; \
115			`fi; \`
116			`if [ ! -z $$UART_PRINTF ]; \`
117			then echo "\`define UART_PRINTF" >> $(SIM_RUN_DIR)/test_define.v; \
118			`fi; \`
119			`if [ -z $$NO_SIM_LOGGING ]; then \`
120			echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
121			`fi; \`
122			`echo ; \`
123			`echo "\t#### Compiling RTL ####"; \`
124			`$(SIM_COMMANDCOMPILE); \`
125			`echo; \`
126			`echo "\t#### Beginning simulation ####"; \`
127			`time -p $(SIM_COMMANDRUN) ; \`
128			`if [ $$? -gt 0 ]; then exit $$?; fi; \`
129			TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log \| grep report \| grep $(SIM_SUCCESS_MESSAGE) -c`; \
130			`echo; echo "\t####"; \`
131			`if [ $$TEST_RESULT -gt 0 ]; then \`
132			echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
133			`else echo "\t#### Test $$TEST FAILED ####";\`
134			`fi; \`
135			`echo "\t####"; echo; \`
136			TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
137			`done; \`
138			`echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo`
139
140
141			`SYN_SIM_COMMANDCOMPILE=if [ ! -e work ]; then vlib work; vlib $(MGC_ORPSOC_LIB); vlog -work $(MGC_ORPSOC_LIB) +libext+.v -y $(XILINX_VERILOG_SRC) +incdir+$(XILINX_VERILOG_SRC) -y $(XILINX_VERILOG_SRC)/unisims +incdir+$(XILINX_VERILOG_SRC)/unisims -y $(XILINX_VERILOG_SRC)/XilinxCoreLib +incdir+$(XILINX_VERILOG_SRC)/XilinxCoreLib $(BOARD_SYN_DIR)/$(BOARD).v $(BOARD_RTL_DIR)/ml501_ddr2_wb_if_cache.v ; fi`
142			`syn-board-test: prepare-dirs $(BOARD_SYN_DIR)/$(BOARD).v`
143			$(Q)echo "\`define TEST_NAME_STRING \"ml501-post-synthesis\"" > $(SIM_RUN_DIR)/test_define.v; \
144			echo "\`define POST_SYNTHESIS_SIM" >> $(SIM_RUN_DIR)/test_define.v; \
145
146			echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
147			`if [ ! -z $$VCD ]; \`
148			then echo "\`define VCD" >> $(SIM_RUN_DIR)/test_define.v; \
149			`if [ ! -z $$VCD_DEPTH ]; \`
150			then echo "\`define VCD_DEPTH "$(VCD_DEPTH) >> $(SIM_RUN_DIR)/test_define.v; \
151			`fi; \`
152			`fi; \`
153			`if [ ! -z $$UART_PRINTF ]; \`
154			then echo "\`define UART_PRINTF" >> $(SIM_RUN_DIR)/test_define.v; \
155			`fi; \`
156			`echo "\t#### Compiling RTL ####"; \`
157			`$(SYN_SIM_COMMANDCOMPILE); \`
158			`echo; \`
159			`echo "\t#### Beginning simulation ####"; \`
160			`time -p $(SIM_COMMANDRUN) ; \`
161			`echo`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [sim/] [bin/] [Makefile] - Blame information for rev 280