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julius |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Interrupt-driven Ethernet MAC test code ////
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//// ////
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//// Description ////
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//// Do ethernet receive path testing ////
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//// Relies on testbench to provide simulus - expects at least ////
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//// 256 packets to be sent. ////
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//// ////
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//// Author(s): ////
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//// - Julius Baxter, julius@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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#include "cpu-utils.h"
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#include "board.h"
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#include "int.h"
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#include "ethmac.h"
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#include "eth-phy-mii.h"
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volatile unsigned tx_done;
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volatile unsigned rx_done;
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/* Functions in this file */
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void ethmac_setup(void);
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void oeth_dump_bds();
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/* Interrupt functions */
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void oeth_interrupt(void);
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static void oeth_rx(void);
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static void oeth_tx(void);
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/* Function to calculate checksum of ping responses we send */
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unsigned short calculate_checksum(char* dats, unsigned int len) ;
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/* Let the ethernet packets use a space beginning here for buffering */
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#define ETH_BUFF_BASE 0x200000;
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#define RXBUFF_PREALLOC 1
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#define TXBUFF_PREALLOC 1
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/* The transmitter timeout
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*/
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#define TX_TIMEOUT (2*HZ)
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/* Buffer number (must be 2^n)
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* Note: if changing these, must also change settings in eth_stim.v testbench
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* file!
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*/
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#define OETH_RXBD_NUM 16
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#define OETH_TXBD_NUM 16
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#define OETH_RXBD_NUM_MASK (OETH_RXBD_NUM-1)
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#define OETH_TXBD_NUM_MASK (OETH_TXBD_NUM-1)
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/* Buffer size
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*/
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#define OETH_RX_BUFF_SIZE 0x600
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#define OETH_TX_BUFF_SIZE 0x600
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/* Buffer size (if not XXBUF_PREALLOC
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*/
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#define MAX_FRAME_SIZE 1518
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/* The buffer descriptors track the ring buffers.
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*/
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struct oeth_private {
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//struct sk_buff* rx_skbuff[OETH_RXBD_NUM];
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//struct sk_buff* tx_skbuff[OETH_TXBD_NUM];
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unsigned short tx_next; /* Next buffer to be sent */
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unsigned short tx_last; /* Next buffer to be checked if packet sent */
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unsigned short tx_full; /* Buffer ring fuul indicator */
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unsigned short rx_cur; /* Next buffer to be checked if packet received */
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oeth_regs *regs; /* Address of controller registers. */
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oeth_bd *rx_bd_base; /* Address of Rx BDs. */
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oeth_bd *tx_bd_base; /* Address of Tx BDs. */
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// struct net_device_stats stats;
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};
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char CHECKSUM_BUFFER[OETH_RX_BUFF_SIZE]; // Big enough to hold a packet
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#define PHYNUM 7
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void ethmac_setup(void)
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{
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// from arch/or32/drivers/open_eth.c
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volatile oeth_regs *regs;
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regs = (oeth_regs *)(OETH_REG_BASE);
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/* Reset MII mode module */
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regs->miimoder = OETH_MIIMODER_RST; /* MII Reset ON */
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regs->miimoder &= ~OETH_MIIMODER_RST; /* MII Reset OFF */
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regs->miimoder = 0x64; /* Clock divider for MII Management interface */
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/* Reset the controller.
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*/
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regs->moder = OETH_MODER_RST; /* Reset ON */
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regs->moder &= ~OETH_MODER_RST; /* Reset OFF */
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/* Setting TXBD base to OETH_TXBD_NUM.
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*/
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regs->tx_bd_num = OETH_TXBD_NUM;
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/* Set min/max packet length
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*/
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regs->packet_len = 0x00400600;
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/* Set IPGT register to recomended value
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*/
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regs->ipgt = 0x12;
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/* Set IPGR1 register to recomended value
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*/
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regs->ipgr1 = 0x0000000c;
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/* Set IPGR2 register to recomended value
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*/
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regs->ipgr2 = 0x00000012;
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/* Set COLLCONF register to recomended value
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*/
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regs->collconf = 0x000f003f;
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/* Set control module mode
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*/
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#if 0
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regs->ctrlmoder = OETH_CTRLMODER_TXFLOW | OETH_CTRLMODER_RXFLOW;
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#else
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regs->ctrlmoder = 0;
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#endif
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/* Clear MIIM registers */
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regs->miitx_data = 0;
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regs->miiaddress = 0;
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regs->miicommand = 0;
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regs->mac_addr1 = ETH_MACADDR0 << 8 | ETH_MACADDR1;
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regs->mac_addr0 = ETH_MACADDR2 << 24 | ETH_MACADDR3 << 16 | ETH_MACADDR4 << 8 | ETH_MACADDR5;
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/* Clear all pending interrupts
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*/
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regs->int_src = 0xffffffff;
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/* Promisc, IFG, CRCEn
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*/
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regs->moder |= OETH_MODER_PRO | OETH_MODER_PAD | OETH_MODER_IFG | OETH_MODER_CRCEN | OETH_MODER_FULLD;
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/* Enable interrupt sources.
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*/
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regs->int_mask = OETH_INT_MASK_TXB |
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OETH_INT_MASK_TXE |
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OETH_INT_MASK_RXF |
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OETH_INT_MASK_RXE |
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OETH_INT_MASK_BUSY |
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OETH_INT_MASK_TXC |
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OETH_INT_MASK_RXC;
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// Buffer setup stuff
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volatile oeth_bd *tx_bd, *rx_bd;
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int i,j,k;
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/* Initialize TXBD pointer
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*/
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tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
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/* Initialize RXBD pointer
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*/
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rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
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/* Preallocated ethernet buffer setup */
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unsigned long mem_addr = ETH_BUFF_BASE; /* Defined at top */
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// Setup TX Buffers
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for(i = 0; i < OETH_TXBD_NUM; i++) {
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//tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC | OETH_RX_BD_IRQ;
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tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC;
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tx_bd[i].addr = mem_addr;
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mem_addr += OETH_TX_BUFF_SIZE;
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}
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tx_bd[OETH_TXBD_NUM - 1].len_status |= OETH_TX_BD_WRAP;
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// Setup RX buffers
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for(i = 0; i < OETH_RXBD_NUM; i++) {
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rx_bd[i].len_status = OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ; // Init. with IRQ
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rx_bd[i].addr = mem_addr;
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mem_addr += OETH_RX_BUFF_SIZE;
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}
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rx_bd[OETH_RXBD_NUM - 1].len_status |= OETH_RX_BD_WRAP; // Last buffer wraps
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/* Enable just the receiver
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*/
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regs->moder &= ~(OETH_MODER_RXEN | OETH_MODER_TXEN);
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regs->moder |= OETH_MODER_RXEN /* | OETH_MODER_TXEN*/;
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return;
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}
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void
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ethmac_halt(void)
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{
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volatile oeth_regs *regs;
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regs = (oeth_regs *)(OETH_REG_BASE);
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// Disable receive and transmit
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regs->moder &= ~(OETH_MODER_RXEN | OETH_MODER_TXEN);
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}
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/* The interrupt handler.
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*/
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void
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oeth_interrupt(void)
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{
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volatile oeth_regs *regs;
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regs = (oeth_regs *)(OETH_REG_BASE);
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uint int_events;
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int serviced;
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serviced = 0;
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/* Get the interrupt events that caused us to be here.
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*/
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int_events = regs->int_src;
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regs->int_src = int_events;
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/* Handle receive event in its own function.
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*/
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if (int_events & (OETH_INT_RXF | OETH_INT_RXE)) {
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serviced |= 0x1;
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oeth_rx();
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}
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267 |
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/* Handle transmit event in its own function.
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269 |
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*/
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270 |
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if (int_events & (OETH_INT_TXB | OETH_INT_TXE)) {
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serviced |= 0x2;
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272 |
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oeth_tx();
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273 |
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serviced |= 0x2;
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275 |
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}
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276 |
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/* Check for receive busy, i.e. packets coming but no place to
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278 |
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* put them.
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279 |
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*/
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280 |
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if (int_events & OETH_INT_BUSY) {
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281 |
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serviced |= 0x4;
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282 |
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if (!(int_events & (OETH_INT_RXF | OETH_INT_RXE)))
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283 |
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oeth_rx();
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284 |
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}
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285 |
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286 |
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return;
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287 |
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}
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288 |
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289 |
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290 |
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static void
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292 |
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oeth_rx(void)
|
293 |
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{
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294 |
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volatile oeth_regs *regs;
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295 |
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regs = (oeth_regs *)(OETH_REG_BASE);
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296 |
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297 |
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volatile oeth_bd *rx_bdp;
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298 |
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int pkt_len, i;
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299 |
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int bad = 0;
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300 |
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301 |
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rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
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302 |
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303 |
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/* Find RX buffers marked as having received data */
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304 |
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for(i = 0; i < OETH_RXBD_NUM; i++)
|
305 |
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{
|
306 |
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bad=0;
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307 |
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/* Looking for buffer descriptors marked not empty */
|
308 |
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if(!(rx_bdp[i].len_status & OETH_RX_BD_EMPTY)){
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309 |
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/* Check status for errors.
|
310 |
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*/
|
311 |
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report(i);
|
312 |
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report(rx_bdp[i].len_status);
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313 |
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if (rx_bdp[i].len_status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT)) {
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314 |
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bad = 1;
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315 |
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report(0xbaad0001);
|
316 |
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}
|
317 |
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if (rx_bdp[i].len_status & OETH_RX_BD_DRIBBLE) {
|
318 |
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bad = 1;
|
319 |
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report(0xbaad0002);
|
320 |
|
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}
|
321 |
|
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if (rx_bdp[i].len_status & OETH_RX_BD_CRCERR) {
|
322 |
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bad = 1;
|
323 |
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report(0xbaad0003);
|
324 |
|
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}
|
325 |
|
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if (rx_bdp[i].len_status & OETH_RX_BD_OVERRUN) {
|
326 |
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bad = 1;
|
327 |
|
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report(0xbaad0004);
|
328 |
|
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}
|
329 |
|
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if (rx_bdp[i].len_status & OETH_RX_BD_MISS) {
|
330 |
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report(0xbaad0005);
|
331 |
|
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}
|
332 |
|
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if (rx_bdp[i].len_status & OETH_RX_BD_LATECOL) {
|
333 |
|
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bad = 1;
|
334 |
|
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report(0xbaad0006);
|
335 |
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}
|
336 |
|
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if (bad) {
|
337 |
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rx_bdp[i].len_status &= ~OETH_RX_BD_STATS;
|
338 |
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rx_bdp[i].len_status |= OETH_RX_BD_EMPTY;
|
339 |
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//exit(0xbaaaaaad);
|
340 |
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|
341 |
|
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continue;
|
342 |
|
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}
|
343 |
|
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else {
|
344 |
|
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/*
|
345 |
|
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* Process the incoming frame.
|
346 |
|
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*/
|
347 |
|
|
pkt_len = rx_bdp[i].len_status >> 16;
|
348 |
|
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|
349 |
|
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// Do a bit of work - ie. copy it, process it
|
350 |
|
|
memcpy(CHECKSUM_BUFFER, rx_bdp[i].addr, pkt_len);
|
351 |
|
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report(0xc4eccccc);
|
352 |
|
|
report(calculate_checksum(CHECKSUM_BUFFER, pkt_len));
|
353 |
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|
354 |
|
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/* finish up */
|
355 |
|
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rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */
|
356 |
|
|
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; /* Mark RX BD as empty */
|
357 |
|
|
rx_done++;
|
358 |
|
|
report(rx_done);
|
359 |
|
|
}
|
360 |
|
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}
|
361 |
|
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}
|
362 |
|
|
}
|
363 |
|
|
|
364 |
|
|
// Calculate checksum on received data.
|
365 |
|
|
// From http://lkml.indiana.edu/hypermail/linux/kernel/9612.3/0060.html
|
366 |
|
|
unsigned short calculate_checksum(char* dats, unsigned int len)
|
367 |
|
|
{
|
368 |
|
|
unsigned int itr;
|
369 |
|
|
unsigned long accum = 0;
|
370 |
|
|
unsigned long longsum;
|
371 |
|
|
|
372 |
|
|
// Sum all pairs of data
|
373 |
|
|
for(itr=0;itr<(len & ~0x1);itr+=2)
|
374 |
|
|
accum += (unsigned long)(((dats[itr]<<8)&0xff00)|(dats[itr+1]&0x00ff));
|
375 |
|
|
|
376 |
|
|
if (len & 0x1) // Do leftover
|
377 |
|
|
accum += (unsigned long) ((dats[itr-1]<<8)&0xff00);
|
378 |
|
|
|
379 |
|
|
longsum = (unsigned long) (accum & 0xffff);
|
380 |
|
|
longsum += (unsigned long) (accum >> 16); // Sum the carries
|
381 |
|
|
longsum += (longsum >> 16);
|
382 |
|
|
return (unsigned short)((longsum ^ 0xffff) & 0xffff);
|
383 |
|
|
|
384 |
|
|
}
|
385 |
|
|
|
386 |
|
|
|
387 |
|
|
static void
|
388 |
|
|
oeth_tx(void)
|
389 |
|
|
{
|
390 |
|
|
volatile oeth_bd *tx_bd;
|
391 |
|
|
int i;
|
392 |
|
|
|
393 |
|
|
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/
|
394 |
|
|
|
395 |
|
|
/* Go through the TX buffs, search for one that was just sent */
|
396 |
|
|
for(i = 0; i < OETH_TXBD_NUM; i++)
|
397 |
|
|
{
|
398 |
|
|
/* Looking for buffer NOT ready for transmit. and IRQ enabled */
|
399 |
|
|
if( (!(tx_bd[i].len_status & (OETH_TX_BD_READY))) && (tx_bd[i].len_status & (OETH_TX_BD_IRQ)) )
|
400 |
|
|
{
|
401 |
|
|
/* Single threaded so no chance we have detected a buffer that has had its IRQ bit set but not its BD_READ flag. Maybe this won't work in linux */
|
402 |
|
|
tx_bd[i].len_status &= ~OETH_TX_BD_IRQ;
|
403 |
|
|
|
404 |
|
|
/* Probably good to check for TX errors here */
|
405 |
|
|
|
406 |
|
|
/* set our test variable */
|
407 |
|
|
tx_done = 1;
|
408 |
|
|
|
409 |
|
|
}
|
410 |
|
|
}
|
411 |
|
|
return;
|
412 |
|
|
}
|
413 |
|
|
|
414 |
|
|
// Loop to check if a number is prime by doing mod divide of the number
|
415 |
|
|
// to test by every number less than it
|
416 |
|
|
int
|
417 |
|
|
is_prime_number(unsigned long n)
|
418 |
|
|
{
|
419 |
|
|
unsigned long c;
|
420 |
|
|
if (n < 2) return 0;
|
421 |
|
|
for(c=2;c<n;c++)
|
422 |
|
|
if ((n % c) == 0)
|
423 |
|
|
return 0;
|
424 |
|
|
return 1;
|
425 |
|
|
}
|
426 |
|
|
|
427 |
|
|
int
|
428 |
|
|
main ()
|
429 |
|
|
{
|
430 |
|
|
|
431 |
|
|
/* Initialise handler vector */
|
432 |
|
|
int_init();
|
433 |
|
|
|
434 |
|
|
/* Install ethernet interrupt handler, it is enabled here too */
|
435 |
|
|
int_add(ETH0_IRQ, oeth_interrupt, 0);
|
436 |
|
|
|
437 |
|
|
/* Enable interrupts in supervisor register */
|
438 |
|
|
cpu_enable_user_interrupts();
|
439 |
|
|
|
440 |
|
|
/* Enable CPU timer */
|
441 |
|
|
cpu_enable_timer();
|
442 |
|
|
|
443 |
|
|
rx_done = 0;
|
444 |
|
|
|
445 |
|
|
ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX in MODER */
|
446 |
|
|
|
447 |
|
|
#define NUM_PRIMES_TO_CHECK 1000
|
448 |
|
|
#define RX_TEST_LENGTH_PACKETS 12
|
449 |
|
|
|
450 |
|
|
char prime_check_results[NUM_PRIMES_TO_CHECK];
|
451 |
|
|
unsigned long num_to_check;
|
452 |
|
|
|
453 |
|
|
for(num_to_check=2;num_to_check<NUM_PRIMES_TO_CHECK;num_to_check++)
|
454 |
|
|
{
|
455 |
|
|
prime_check_results[num_to_check-2]
|
456 |
|
|
= (char) is_prime_number(num_to_check);
|
457 |
|
|
report(num_to_check | (0x1e<<24));
|
458 |
|
|
report(prime_check_results[num_to_check-2] | (0x2e<<24));
|
459 |
|
|
// Check number of packets received, testbench will hopefully send at
|
460 |
|
|
// least this many packets
|
461 |
|
|
if (rx_done >= (RX_TEST_LENGTH_PACKETS - 1))
|
462 |
|
|
exit(0x8000000d);
|
463 |
|
|
}
|
464 |
|
|
|
465 |
|
|
ethmac_halt();
|
466 |
|
|
|
467 |
|
|
exit(0x8000000d);
|
468 |
|
|
|
469 |
|
|
return 0;
|
470 |
|
|
}
|