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568 |
julius |
# Makefile fragment with some variables global to this board board
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# Expects BOARD_ROOT to be set
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FPGA_VENDOR=xilinx
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BOARD_NAME=s3adsp1800
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BOARD=$(FPGA_VENDOR)/$(BOARD_NAME)
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DESIGN_NAME=orpsoc
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# Doc:
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# http://www.xilinx.com/support/documentation/boards_and_kits/ug454_sp3a_dsp_start_ug.pdf
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# Path down to root of project
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PROJECT_ROOT=$(BOARD_ROOT)/../../..
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SYNTHESIS_TOOL=xst
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export BOARD
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include $(PROJECT_ROOT)/scripts/make/Makefile-misc.inc
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include $(PROJECT_ROOT)/scripts/make/Makefile-board-paths.inc
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include $(PROJECT_ROOT)/scripts/make/Makefile-board-tops.inc
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include $(PROJECT_ROOT)/scripts/make/Makefile-board-definesparse.inc
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638 |
stekern |
# Check that the Xilinx scripts have been sourced
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ifndef XILINX
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$(error The XILINX environment variable was not set, \
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please run: 'source /path/to/xilinx_ise/settings{32|64}.sh')
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568 |
julius |
endif
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# Backend directories
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# This one is the board build's backend dir.
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BOARD_BACKEND_DIR=$(BOARD_ROOT)/backend
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BOARD_BACKEND_VERILOG_DIR=$(BOARD_BACKEND_DIR)/rtl/verilog
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BOARD_BACKEND_BIN_DIR=$(BOARD_BACKEND_DIR)/bin
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# Technology backend (vendor-specific)
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TECHNOLOGY_BACKEND_DIR=$(BOARD_ROOT)/../backend
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# This path is for the technology library
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638 |
stekern |
TECHNOLOGY_LIBRARY_VERILOG_DIR=$(XILINX)/verilog
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568 |
julius |
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# Bootrom setup
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# BootROM code, which generates a verilog array select values
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BOOTROM_FILE=bootrom.v
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BOOTROM_SW_DIR=$(BOARD_SW_DIR)/bootrom
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BOOTROM_SRC=$(shell ls $(BOOTROM_SW_DIR)/* | grep -v $(BOOTROM_FILE))
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BOOTROM_VERILOG=$(BOOTROM_SW_DIR)/$(BOOTROM_FILE)
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bootrom: $(BOOTROM_VERILOG)
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$(BOOTROM_VERILOG): $(BOOTROM_SRC)
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$(Q)echo; echo "\t### Generating bootup ROM ###"; echo
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$(Q)$(MAKE) -C $(BOOTROM_SW_DIR) $(BOOTROM_FILE)
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clean-bootrom:
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$(Q)echo; echo "\t### Cleaning bootup ROM ###"; echo
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$(Q)$(MAKE) -C $(BOOTROM_SW_DIR) clean
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include $(PROJECT_ROOT)/scripts/make/Makefile-board-rtlmodules.inc
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# "Backend" source file stuff (PLL, RAM macro models.)
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BOARD_BACKEND_VERILOG_SRC=$(shell ls $(BOARD_BACKEND_VERILOG_DIR)/*.v )
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# Backend tool path
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# BACKEND_TECHNOLOGY_VERILOG_SRC should be set if we need to compile specific
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# libraries, as in the Actel and Altera case, and left empty for Xilinx who
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# allow us to simply pass the path with the -y option because they have each
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# bit of the tech library in individual files, and in which case this variable
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# should be left unset.
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# Keep this variable empty
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BACKEND_TECHNOLOGY_VERILOG_SRC=
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