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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [backend/] [par/] [bin/] [s3adsp1800.ucf] - Blame information for rev 570

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Line No. Rev Author Line
1 568 julius 
############################################################################
2 
##    _____
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##   /     \
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##  /____   \____
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## / \===\   \==/
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##/___\===\___\/  AVNET Design Resource Center
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##     \======/         www.em.avnet.com/drc
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##      \====/          www.em.avnet.com/spartan3a-dsp
9 
##----------------------------------------------------------------
10 
##
11 
## Disclaimer:
12 
##    Avnet, Inc. makes no warranty for the use of this code or design.
13 
##    This code is provided  "As Is". Avnet, Inc assumes no responsibility for
14 
##    any errors, which may appear in this code, nor does it make a commitment
15 
##    to update the information contained herein. Avnet, Inc specifically
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##    disclaims any implied warranties of fitness for a particular purpose.
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##                     Copyright(c) 2007 Avnet, Inc.
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##                             All rights reserved.
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##
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############################################################################
21 
 
22 
## Spartan-3A Specific constraints
23 
CONFIG VCCAUX=3.3;
24 
 
25 
#### System level constraints
26 
 
27 
# Net sys_clk_i LOC = "AE13" | IOSTANDARD = LVCMOS33 ;  # socket clock
28 
Net sys_clk_i LOC = "F13" | IOSTANDARD = LVCMOS33 ;  # 125 MHz clock
29 
# Net sys_clk_i LOC = "K14"  | IOSTANDARD = LVCMOS33 ;  # SMA clock
30 
 
31 
Net rst_n_pad_i LOC="Y16" | IOSTANDARD = LVTTL;
32 
Net rst_n_pad_i TIG;
33 
#NET "mb_opb_OPB_Rst" TIG;
34 
 
35 
#### Timing constraints
36 
 
37 
Net sys_clk_i TNM_NET = sys_clk_i;
38 
TIMESPEC TS_sys_clk_i = PERIOD sys_clk_i 8000 ps; # 125MHz
39 
 
40 
# Can't see any FB nets in DDR2 design from MIG - Julius
41 
#Net fpga_0_DDR_CLK_FB TNM_NET = fpga_0_DDR_CLK_FB;
42 
#TIMESPEC TS_fpga_0_DDR_CLK_FB = PERIOD fpga_0_DDR_CLK_FB 8000 ps; # 125MHz
43 
 
44 
# Not using this clock - Julius
45 
#Net CLK_25_175MHZ TNM_NET = CLK_25_175MHZ;
46 
#TIMESPEC TS_CLK_25_175MHZ = PERIOD CLK_25_175MHZ 39700 ps; # 25.175MHz
47 
#INST "CLK_25_175MHZ_BUFGP/BUFG" LOC = "BUFGMUX_X3Y2";
48 
 
49 
#### Module RS232 constraints
50 
 
51 
Net uart0_srx_pad_i LOC="N21" | IOSTANDARD = LVTTL;
52 
Net uart0_stx_pad_o LOC="P22" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW;
53 
 
54 
#### Module LEDs_8Bit constraints
55 
 
56 
#Net fpga_0_LEDs_8Bit_GPIO_d_out* TIG;
57 
Net gpio0_io[*] TIG;
58 
Net gpio0_io<0> LOC="D25" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
59 
Net gpio0_io<1> LOC="D24" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
60 
Net gpio0_io<2> LOC="G21" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
61 
Net gpio0_io<3> LOC="H20" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
62 
Net gpio0_io<4> LOC="K22" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
63 
Net gpio0_io<5> LOC="N19" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
64 
Net gpio0_io<6> LOC="P25" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
65 
Net gpio0_io<7> LOC="P18" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
66 
 
67 
#### Module DIP_Switches_8Bit constraints
68 
 
69 
#Net fpga_0_DIP_Switches_8Bit_GPIO_in* TIG;
70 
 
71 
#Net gpio0_io<8> LOC="A23" | IOSTANDARD = LVTTL;
72 
#Net gpio0_io<9> LOC="A5"  | IOSTANDARD = LVTTL;
73 
#Net gpio0_io<10> LOC="B24" | IOSTANDARD = LVTTL;
74 
#Net gpio0_io<11> LOC="D19" | IOSTANDARD = LVTTL;
75 
#Net gpio0_io<12> LOC="D15" | IOSTANDARD = LVTTL;
76 
#Net gpio0_io<13> LOC="E9"  | IOSTANDARD = LVTTL;
77 
#Net gpio0_io<14> LOC="G16" | IOSTANDARD = LVTTL;
78 
#Net gpio0_io<15> LOC="A7"  | IOSTANDARD = LVTTL;
79 
 
80 
#### Module Buttons_4Bit constraints
81 
 
82 
#Net gpio0_io<16> LOC = "J17" | IOSTANDARD = LVTTL;
83 
#Net gpio0_io<17> LOC = "J15" | IOSTANDARD = LVTTL;
84 
#Net gpio0_io<18> LOC = "J13" | IOSTANDARD = LVTTL;
85 
#Net gpio0_io<19> LOC = "J10" | IOSTANDARD = LVTTL;
86 
 
87 
# GPIO pads which can have I/O bufs - on J8 SysAce header
88 
Net gpio0_io<8>  LOC = "U18" | IOSTANDARD = LVTTL;
89 
Net gpio0_io<9>  LOC = "Y22" | IOSTANDARD = LVTTL;
90 
Net gpio0_io<10> LOC = "Y23" | IOSTANDARD = LVTTL;
91 
Net gpio0_io<11> LOC = "U21" | IOSTANDARD = LVTTL;
92 
Net gpio0_io<12> LOC = "T20" | IOSTANDARD = LVTTL;
93 
Net gpio0_io<13> LOC = "Y24" | IOSTANDARD = LVTTL;
94 
Net gpio0_io<14> LOC = "Y25" | IOSTANDARD = LVTTL;
95 
Net gpio0_io<15> LOC = "T18" | IOSTANDARD = LVTTL;
96 
Net gpio0_io<16> LOC = "T17" | IOSTANDARD = LVTTL;
97 
Net gpio0_io<17> LOC = "W23" | IOSTANDARD = LVTTL;
98 
Net gpio0_io<18> LOC = "V25" | IOSTANDARD = LVTTL;
99 
Net gpio0_io<19> LOC = "V22" | IOSTANDARD = LVTTL;
100 
Net gpio0_io<20> LOC = "V24" | IOSTANDARD = LVTTL;
101 
Net gpio0_io<21> LOC = "V23" | IOSTANDARD = LVTTL;
102 
Net gpio0_io<22> LOC = "AC26" | IOSTANDARD = LVTTL;
103 
Net gpio0_io<23> LOC = "AB26" | IOSTANDARD = LVTTL;
104 
 
105 
 
106 
#### Module DDR2_SDRAM_32Mx32 constraints
107 
 
108 
##################################################################################################
109 
## Clock constraints
110 
##################################################################################################
111 
#NET "*/infrastructure_top0/sys_clk_ibuf" TNM_NET = "SYS_CLK";
112 
#TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK"  7.519000  ns HIGH 50 %;
113 
##################################################################################################
114 
 
115 
##################################################################################################
116 
## These paths are constrained to get rid of unconstrained paths.
117 
##################################################################################################
118 
NET "*/infrastructure_top0/clk_dcm0/clk0dcm" TNM_NET = "clk0";
119 
#NET "xilinx_s3adsp_ddr2/xilinx_s3adsp_ddr2_if/s3adsp_ddr2/top_00/data_path0/dqs_delayed_col*" TNM_NET = "dqs_clk";
120 
NET "*/top_00/data_path0/dqs_delayed_col*" TNM_NET = "dqs_clk";
121 
TIMESPEC "TS_CLK" = FROM "clk0" TO "dqs_clk"  18 ns DATAPATHONLY;
122 
 
123 
NET "*/infrastructure_top0/clk_dcm0/clk90dcm" TNM_NET = "clk90";
124 
TIMESPEC "TS_CLK90" = FROM "dqs_clk" TO "clk90" 18 ns DATAPATHONLY;
125 
TIMESPEC "TS_DQSCLK" = FROM "clk90" TO "dqs_clk" 18 ns DATAPATHONLY;
126 
 
127 
#NET "*/top_00/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk" TNM_NET = "fifo_we_clk";
128 
NET "*/top_00/data_path0/dqs_delayed_col0[*]" TNM_NET = "fifo_we_clk";
129 
 
130 
TIMESPEC "TS_WE_CLK" = FROM "dqs_clk" TO "fifo_we_clk"  5 ns DATAPATHONLY;
131 
 
132 
#NET "*/top_00/data_path0/data_read_controller0/gen_wr_addr*fifo*_wr_addr_inst/clk" TNM_NET = "fifo_waddr_clk";
133 
 
134 
NET "*/top_00/data_path0/dqs_delayed_col0[*]" TNM_NET = "fifo_waddr_clk";
135 
TIMESPEC "TS_WADDR_CLK" = FROM "dqs_clk" TO "fifo_waddr_clk"  5 ns DATAPATHONLY;
136 
 
137 
NET "*/top_00/data_path0/dqs_delayed_col1[*]" TNM_NET = "fifo_waddr_clk1";
138 
TIMESPEC "TS_WADDR_CLK" = FROM "dqs_clk" TO "fifo_waddr_clk1"  5 ns DATAPATHONLY;
139 
 
140 
#############################################################################################################
141 
## Calibration Circuit Constraints
142 
#############################################################################################################
143 
## Placement constraints for LUTS in tap delay ckt
144 
#############################################################################################################
145 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l0" RLOC=X0Y6;
146 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l0" U_SET = delay_calibration_chain;
147 
 
148 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l1" RLOC=X0Y6;
149 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l1" U_SET = delay_calibration_chain;
150 
 
151 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l2" RLOC=X0Y7;
152 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l2" U_SET = delay_calibration_chain;
153 
 
154 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l3" RLOC=X0Y7;
155 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l3" U_SET = delay_calibration_chain;
156 
 
157 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l4" RLOC=X1Y6;
158 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l4" U_SET = delay_calibration_chain;
159 
 
160 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l5" RLOC=X1Y6;
161 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l5" U_SET = delay_calibration_chain;
162 
 
163 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l6" RLOC=X1Y7;
164 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l6" U_SET = delay_calibration_chain;
165 
 
166 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l7" RLOC=X1Y7;
167 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l7" U_SET = delay_calibration_chain;
168 
 
169 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l8" RLOC=X0Y4;
170 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l8" U_SET = delay_calibration_chain;
171 
 
172 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l9" RLOC=X0Y4;
173 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l9" U_SET = delay_calibration_chain;
174 
 
175 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l10" RLOC=X0Y5;
176 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l10" U_SET = delay_calibration_chain;
177 
 
178 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l11" RLOC=X0Y5;
179 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l11" U_SET = delay_calibration_chain;
180 
 
181 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l12" RLOC=X1Y4;
182 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l12" U_SET = delay_calibration_chain;
183 
 
184 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l13" RLOC=X1Y4;
185 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l13" U_SET = delay_calibration_chain;
186 
 
187 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l14" RLOC=X1Y5;
188 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l14" U_SET = delay_calibration_chain;
189 
 
190 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l15" RLOC=X1Y5;
191 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l15" U_SET = delay_calibration_chain;
192 
 
193 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l16" RLOC=X0Y2;
194 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l16" U_SET = delay_calibration_chain;
195 
 
196 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l17" RLOC=X0Y2;
197 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l17" U_SET = delay_calibration_chain;
198 
 
199 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l18" RLOC=X0Y3;
200 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l18" U_SET = delay_calibration_chain;
201 
 
202 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l19" RLOC=X0Y3;
203 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l19" U_SET = delay_calibration_chain;
204 
 
205 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l20" RLOC=X1Y2;
206 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l20" U_SET = delay_calibration_chain;
207 
 
208 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l21" RLOC=X1Y2;
209 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l21" U_SET = delay_calibration_chain;
210 
 
211 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l22" RLOC=X1Y3;
212 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l22" U_SET = delay_calibration_chain;
213 
 
214 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l23" RLOC=X1Y3;
215 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l23" U_SET = delay_calibration_chain;
216 
 
217 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l24" RLOC=X0Y0;
218 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l24" U_SET = delay_calibration_chain;
219 
 
220 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l25" RLOC=X0Y0;
221 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l25" U_SET = delay_calibration_chain;
222 
 
223 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l26" RLOC=X0Y1;
224 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l26" U_SET = delay_calibration_chain;
225 
 
226 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l27" RLOC=X0Y1;
227 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l27" U_SET = delay_calibration_chain;
228 
 
229 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l28" RLOC=X1Y0;
230 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l28" U_SET = delay_calibration_chain;
231 
 
232 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l29" RLOC=X1Y0;
233 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l29" U_SET = delay_calibration_chain;
234 
 
235 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l30" RLOC=X1Y1;
236 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l30" U_SET = delay_calibration_chain;
237 
 
238 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l31" RLOC=X1Y1;
239 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l31" U_SET = delay_calibration_chain;
240 
 
241 
#####################################################################################################
242 
# Placement constraints for first stage flops in tap delay ckt
243 
#####################################################################################################
244 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[0].r" RLOC=X0Y6;
245 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[0].r" U_SET = delay_calibration_chain;
246 
 
247 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[1].r" RLOC=X0Y6;
248 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[1].r" U_SET = delay_calibration_chain;
249 
 
250 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[2].r" RLOC=X0Y7;
251 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[2].r" U_SET = delay_calibration_chain;
252 
 
253 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[3].r" RLOC=X0Y7;
254 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[3].r" U_SET = delay_calibration_chain;
255 
 
256 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[4].r" RLOC=X1Y6;
257 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[4].r" U_SET = delay_calibration_chain;
258 
 
259 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[5].r" RLOC=X1Y6;
260 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[5].r" U_SET = delay_calibration_chain;
261 
 
262 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[6].r" RLOC=X1Y7;
263 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[6].r" U_SET = delay_calibration_chain;
264 
 
265 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[7].r" RLOC=X1Y7;
266 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[7].r" U_SET = delay_calibration_chain;
267 
 
268 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[8].r" RLOC=X0Y4;
269 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[8].r" U_SET = delay_calibration_chain;
270 
 
271 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[9].r" RLOC=X0Y4;
272 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[9].r" U_SET = delay_calibration_chain;
273 
 
274 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[10].r" RLOC=X0Y5;
275 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[10].r" U_SET = delay_calibration_chain;
276 
 
277 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[11].r" RLOC=X0Y5;
278 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[11].r" U_SET = delay_calibration_chain;
279 
 
280 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[12].r" RLOC=X1Y4;
281 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[12].r" U_SET = delay_calibration_chain;
282 
 
283 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[13].r" RLOC=X1Y4;
284 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[13].r" U_SET = delay_calibration_chain;
285 
 
286 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[14].r" RLOC=X1Y5;
287 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[14].r" U_SET = delay_calibration_chain;
288 
 
289 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[15].r" RLOC=X1Y5;
290 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[15].r" U_SET = delay_calibration_chain;
291 
 
292 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[16].r" RLOC=X0Y2;
293 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[16].r" U_SET = delay_calibration_chain;
294 
 
295 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[17].r" RLOC=X0Y2;
296 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[17].r" U_SET = delay_calibration_chain;
297 
 
298 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[18].r" RLOC=X0Y3;
299 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[18].r" U_SET = delay_calibration_chain;
300 
 
301 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[19].r" RLOC=X0Y3;
302 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[19].r" U_SET = delay_calibration_chain;
303 
 
304 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[20].r" RLOC=X1Y2;
305 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[20].r" U_SET = delay_calibration_chain;
306 
 
307 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[21].r" RLOC=X1Y2;
308 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[21].r" U_SET = delay_calibration_chain;
309 
 
310 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[22].r" RLOC=X1Y3;
311 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[22].r" U_SET = delay_calibration_chain;
312 
 
313 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[23].r" RLOC=X1Y3;
314 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[23].r" U_SET = delay_calibration_chain;
315 
 
316 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[24].r" RLOC=X0Y0;
317 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[24].r" U_SET = delay_calibration_chain;
318 
 
319 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[25].r" RLOC=X0Y0;
320 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[25].r" U_SET = delay_calibration_chain;
321 
 
322 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[26].r" RLOC=X0Y1;
323 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[26].r" U_SET = delay_calibration_chain;
324 
 
325 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[27].r" RLOC=X0Y1;
326 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[27].r" U_SET = delay_calibration_chain;
327 
 
328 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[28].r" RLOC=X1Y0;
329 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[28].r" U_SET = delay_calibration_chain;
330 
 
331 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[29].r" RLOC=X1Y0;
332 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[29].r" U_SET = delay_calibration_chain;
333 
 
334 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[30].r" RLOC=X1Y1;
335 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[30].r" U_SET = delay_calibration_chain;
336 
 
337 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[31].r" RLOC=X1Y1;
338 
INST "*/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[31].r" U_SET = delay_calibration_chain;
339 
 
340 
#########################################################################################################
341 
## BEL constraints for LUTS in tap delay ckt
342 
#########################################################################################################
343 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l0"  BEL= G;
344 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l1"  BEL= F;
345 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l2"  BEL= G;
346 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l3"  BEL= F;
347 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l4"  BEL= G;
348 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l5"  BEL= F;
349 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l6"  BEL= G;
350 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l7"  BEL= F;
351 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l8"  BEL= G;
352 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l9"  BEL= F;
353 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l10" BEL= G;
354 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l11" BEL= F;
355 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l12" BEL= G;
356 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l13" BEL= F;
357 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l14" BEL= G;
358 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l15" BEL= F;
359 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l16" BEL= G;
360 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l17" BEL= F;
361 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l18" BEL= G;
362 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l19" BEL= F;
363 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l20" BEL= G;
364 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l21" BEL= F;
365 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l22" BEL= G;
366 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l23" BEL= F;
367 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l24" BEL= G;
368 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l25" BEL= F;
369 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l26" BEL= G;
370 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l27" BEL= F;
371 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l28" BEL= G;
372 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l29" BEL= F;
373 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l30" BEL= G;
374 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l31" BEL= F;
375 
 
376 
 
377 
 
378 
##################################################################################################
379 
## RLOC Origin constraint for LUT delay calibration chain.
380 
##################################################################################################
381 
INST "*/infrastructure_top0/cal_top0/tap_dly0/l0" RLOC_ORIGIN = X42Y154;
382 
 
383 
##################################################################################################
384 
## Area Group Constraint For tap_dly and cal_ctl module.
385 
##################################################################################################
386 
INST "*/infrastructure_top0/cal_top0/cal_ctl0/*" AREA_GROUP = cal_ctl;
387 
INST "*/infrastructure_top0/cal_top0/tap_dly0/*" AREA_GROUP = cal_ctl;
388 
AREA_GROUP "cal_ctl" RANGE = SLICE_X42Y154:SLICE_X53Y167;
389 
AREA_GROUP "cal_ctl" GROUP = CLOSED;
390 
 
391 
##################################################################################################
392 
 
393 
#***********************************************************************************************************#
394 
#                        CONTROLLER 0
395 
#***********************************************************************************************************#
396 
 
397 
##################################################################################################
398 
# I/O STANDARDS
399 
##################################################################################################
400 
NET  "ddr2_dq[*]"                        IOSTANDARD = SSTL18_II;
401 
NET  "ddr2_a[*]"                         IOSTANDARD = SSTL18_II;
402 
NET  "ddr2_ba[*]"                        IOSTANDARD = SSTL18_II;
403 
NET  "ddr2_cke"                          IOSTANDARD = SSTL18_II;
404 
NET  "ddr2_cs_n"                         IOSTANDARD = SSTL18_II;
405 
NET  "ddr2_ras_n"                        IOSTANDARD = SSTL18_II;
406 
NET  "ddr2_cas_n"                        IOSTANDARD = SSTL18_II;
407 
NET  "ddr2_we_n"                         IOSTANDARD = SSTL18_II;
408 
NET  "ddr2_odt"                          IOSTANDARD = SSTL18_II;
409 
NET  "ddr2_dm[*]"                        IOSTANDARD = SSTL18_II;
410 
NET  "ddr2_rst_dqs_div_in"                    IOSTANDARD = SSTL18_II;
411 
NET  "ddr2_rst_dqs_div_out"                   IOSTANDARD = SSTL18_II;
412 
NET  "ddr2_dqs[*]"                       IOSTANDARD = DIFF_SSTL18_II;
413 
NET  "ddr2_dqs_n[*]"                     IOSTANDARD = DIFF_SSTL18_II;
414 
NET  "ddr2_ck[*]"                        IOSTANDARD = DIFF_SSTL18_II;
415 
NET  "ddr2_ck_n[*]"                      IOSTANDARD = DIFF_SSTL18_II;
416 
 
417 
 
418 
##################################################################################################
419 
# Pin Location Constraints for Clock,Masks, Address, and Controls
420 
##################################################################################################
421 
# New UCF (from MIG, updated with correct pins from schematic)
422 
 
423 
NET  "ddr2_ck[0]"    LOC = "N1" ;     #bank 3
424 
NET  "ddr2_ck_n[0]"    LOC = "N2" ;     #bank 3
425 
NET  "ddr2_ck[1]"    LOC = "N5" ;     #bank 3
426 
NET  "ddr2_ck_n[1]"    LOC = "N4" ;     #bank 3
427 
 
428 
NET  "ddr2_dm[0]"    LOC = "V2" ;     #bank 3
429 
NET  "ddr2_dm[1]"    LOC = "V1" ;     #bank 3
430 
NET  "ddr2_dm[2]"    LOC = "R2" ;     #bank 3
431 
NET  "ddr2_dm[3]"    LOC = "M6" ;     #bank 3
432 
 
433 
NET  "ddr2_a[12]"    LOC = "M4" ;     #bank 3
434 
NET  "ddr2_a[11]"    LOC = "M3" ;     #bank 3
435 
NET  "ddr2_a[10]"    LOC = "M8" ;     #bank 3
436 
NET  "ddr2_a[9]"     LOC = "M7" ;     #bank 3
437 
NET  "ddr2_a[8]"     LOC = "L4" ;     #bank 3
438 
NET  "ddr2_a[7]"     LOC = "L3" ;     #bank 3
439 
NET  "ddr2_a[6]"     LOC = "K3" ;     #bank 3
440 
NET  "ddr2_a[5]"     LOC = "K2" ;     #bank 3
441 
NET  "ddr2_a[4]"     LOC = "K5" ;     #bank 3
442 
NET  "ddr2_a[3]"     LOC = "K4" ;     #bank 3
443 
NET  "ddr2_a[2]"     LOC = "M10" ;     #bank 3
444 
NET  "ddr2_a[1]"     LOC = "M9" ;     #bank 3
445 
NET  "ddr2_a[0]"     LOC = "J5" ;     #bank 3
446 
 
447 
NET  "ddr2_ba[1]"    LOC = "J4" ;     #bank 3
448 
NET  "ddr2_ba[0]"    LOC = "K6" ;     #bank 3
449 
 
450 
NET  "ddr2_cke"      LOC = "L7" ;     #bank 3
451 
NET  "ddr2_cs_n"     LOC = "H2" ;     #bank 3
452 
NET  "ddr2_ras_n"    LOC = "H1" ;     #bank 3
453 
NET  "ddr2_cas_n"    LOC = "L10" ;     #bank 3
454 
NET  "ddr2_we_n"     LOC = "L9" ;     #bank 3
455 
NET  "ddr2_odt"      LOC = "G3" ;     #bank 3
456 
 
457 
##################################################################################################
458 
## There is an issue with Xilinx ISE_DS 10.1 tool, default drive strength of LVCMOS18 for Spartan-3A
459 
## should set to 8MA for top/bottom banks, the tool is setting it to 12MA.
460 
## We are setting the drive strength to 8MA in UCF file for following signal/signals
461 
## as work aroud until the ISE bug is fixed
462 
 
463 
##################################################################################################
464 
 
465 
##################################################################################################
466 
## MAXDELAY constraints
467 
##################################################################################################
468 
 
469 
##################################################################################################
470 
## Constraint to have the tap delay inverter connection wire length to be the same and minimum to get
471 
## accurate calibration of tap delays. The following constraints are independent of frequency.
472 
##################################################################################################
473 
NET "*/infrastructure_top0/cal_top0/tap_dly0/tap[7]"  MAXDELAY = 400 ps;
474 
NET "*/infrastructure_top0/cal_top0/tap_dly0/tap[15]"  MAXDELAY = 400 ps;
475 
NET "*/infrastructure_top0/cal_top0/tap_dly0/tap[23]"  MAXDELAY = 400 ps;
476 
 
477 
##################################################################################################
478 
## MAXDELAY constraint on inter LUT delay elements. This constraint is required to minimize the
479 
## wire delays between the LUTs.
480 
##################################################################################################
481 
NET "*/data_path0/data_read_controller0/gen_delay*dqs_delay_col*/delay*"  MAXDELAY = 190 ps;
482 
NET "*/data_path0/data_read_controller0/rst_dqs_div_delayed/delay*"  MAXDELAY = 200 ps;
483 
 
484 
##################################################################################################
485 
## Constraint from the dqs PAD to input of LUT delay element.
486 
##################################################################################################
487 
NET "*/dqs_int_delay_in*" MAXDELAY = 661 ps;
488 
 
489 
##################################################################################################
490 
## Constraint from rst_dqs_div_in PAD to input of LUT delay element.
491 
##################################################################################################
492 
NET "*/dqs_div_rst" MAXDELAY = 468 ps;
493 
 
494 
##################################################################################################
495 
## Following are the MAXDELAY constraints on delayed rst_dqs_div net and fifo write enable signals.
496 
## These constraints are required since these paths are not covered by timing analysis. The requirement is total
497 
## delay on delayed rst_dqs_div and fifo_wr_en nets should not exceed the clock period.
498 
##################################################################################################
499 
NET "*/data_path0/data_read_controller0/rst_dqs_div"  MAXDELAY = 3007 ps;
500 
#NET "*/data_path0/data_read0/fifo*_wr_en*"                    MAXDELAY = 3007 ps;
501 
NET "*/data_path0/fifo*_wr_en[*]"                     MAXDELAY = 3007 ps;
502 
 
503 
##################################################################################################
504 
## The MAXDELAY value on fifo write address should be less than clock period. This constraint is
505 
## required since this path is not covered by timing analysis.
506 
##################################################################################################
507 
#NET "*/data_path0/data_read0/fifo*_wr_addr[*]"           MAXDELAY = 6391 ps;
508 
NET "*/data_path0/fifo*_wr_addr[*]"           MAXDELAY = 6391 ps;
509 
 
510 
##################################################################################################
511 
 
512 
##################################################################################################
513 
##  constraints for bit ddr2_dq, 1, location in tile: 0
514 
##################################################################################################
515 
NET "ddr2_dq[1]" LOC = "V8";     #bank 3
516 
INST "*/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit1"   LOC = SLICE_X2Y26;
517 
INST "*/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit1" LOC = SLICE_X2Y27;
518 
 
519 
##################################################################################################
520 
##  constraints for bit ddr2_dq, 0, location in tile: 0
521 
##################################################################################################
522 
NET "ddr2_dq[0]" LOC = "U9";     #bank 3
523 
INST "*/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit0"   LOC = SLICE_X0Y26;
524 
INST "*/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit0" LOC = SLICE_X0Y27;
525 
 
526 
##################################################################################################
527 
##  constraints for bit ddr2_dq, 3, location in tile: 0
528 
##################################################################################################
529 
NET "ddr2_dq[3]" LOC = "AC1";     #bank 3
530 
INST "*/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit3"   LOC = SLICE_X2Y28;
531 
INST "*/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit3" LOC = SLICE_X2Y29;
532 
 
533 
##################################################################################################
534 
##  constraints for bit ddr2_dq, 2, location in tile: 0
535 
##################################################################################################
536 
NET "ddr2_dq[2]" LOC = "AB1";     #bank 3
537 
INST "*/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit2"   LOC = SLICE_X0Y28;
538 
INST "*/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit2" LOC = SLICE_X0Y29;
539 
 
540 
##################################################################################################
541 
##  constraints for bit ddr2_dqs_n, 0, location in tile: 0
542 
##################################################################################################
543 
NET "ddr2_dqs_n[0]" LOC = "V6";     #bank 3
544 
 
545 
##################################################################################################
546 
##  constraints for bit ddr2_dqs, 0, location in tile: 0
547 
##################################################################################################
548 
NET "ddr2_dqs[0]" LOC = "V7";     #bank 3
549 
 
550 
##################################################################################################
551 
## LUT location constraints for dqs_delayed_col0
552 
##################################################################################################
553 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one" LOC = SLICE_X2Y31;
554 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one" BEL = F;
555 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two" LOC = SLICE_X2Y31;
556 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two" BEL = G;
557 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three" LOC = SLICE_X2Y30;
558 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three" BEL = G;
559 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four" LOC = SLICE_X2Y30;
560 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four" BEL = F;
561 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five" LOC = SLICE_X3Y31;
562 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five" BEL = G;
563 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six" LOC = SLICE_X3Y30;
564 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six" BEL = G;
565 
 
566 
##################################################################################################
567 
## LUT location constraints for dqs_delayed_col1
568 
##################################################################################################
569 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one" LOC = SLICE_X0Y31;
570 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one" BEL = F;
571 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two" LOC = SLICE_X0Y31;
572 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two" BEL = G;
573 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three" LOC = SLICE_X0Y30;
574 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three" BEL = G;
575 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four" LOC = SLICE_X0Y30;
576 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four" BEL = F;
577 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five" LOC = SLICE_X1Y31;
578 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five" BEL = G;
579 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six" LOC = SLICE_X1Y30;
580 
INST "*/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six" BEL = G;
581 
 
582 
##################################################################################################
583 
## Slice location constraints for Fifo write address and write enable
584 
##################################################################################################
585 
INST "*/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit0" LOC = SLICE_X1Y26;
586 
INST "*/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit1" LOC = SLICE_X1Y26;
587 
INST "*/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit2" LOC = SLICE_X1Y27;
588 
INST "*/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit3" LOC = SLICE_X1Y27;
589 
INST "*/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit0" LOC = SLICE_X3Y26;
590 
INST "*/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit1" LOC = SLICE_X3Y26;
591 
INST "*/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit2" LOC = SLICE_X3Y27;
592 
INST "*/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit3" LOC = SLICE_X3Y27;
593 
#INST "*/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst" LOC = SLICE_X1Y29;
594 
INST "*/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst/dout*" LOC = SLICE_X1Y29;
595 
#INST "*/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst" LOC = SLICE_X3Y29;
596 
INST "*data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst/dout*" LOC = SLICE_X3Y29;
597 
 
598 
##################################################################################################
599 
##  constraints for bit ddr2_dq, 5, location in tile: 0
600 
##################################################################################################
601 
NET "ddr2_dq[5]" LOC = "Y6";     #bank 3
602 
INST "*/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit5"   LOC = SLICE_X2Y34;
603 
INST "*/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit5" LOC = SLICE_X2Y35;
604 
 
605 
##################################################################################################
606 
##  constraints for bit ddr2_dq, 4, location in tile: 0
607 
##################################################################################################
608 
NET "ddr2_dq[4]" LOC = "Y5";     #bank 3
609 
INST "*/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit4"   LOC = SLICE_X0Y34;
610 
INST "*/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit4" LOC = SLICE_X0Y35;
611 
 
612 
##################################################################################################
613 
##  constraints for bit ddr2_dq, 7, location in tile: 0
614 
##################################################################################################
615 
NET "ddr2_dq[7]" LOC = "U8";     #bank 3
616 
INST "*/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit7"   LOC = SLICE_X2Y36;
617 
INST "*/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit7" LOC = SLICE_X2Y37;
618 
 
619 
##################################################################################################
620 
##  constraints for bit ddr2_dq, 6, location in tile: 0
621 
##################################################################################################
622 
NET "ddr2_dq[6]" LOC = "U7";     #bank 3
623 
INST "*/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit6"   LOC = SLICE_X0Y36;
624 
INST "*/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit6" LOC = SLICE_X0Y37;
625 
 
626 
##################################################################################################
627 
##  constraints for bit ddr2_dq, 9, location in tile: 0
628 
##################################################################################################
629 
NET "ddr2_dq[9]" LOC = "AA3";     #bank 3
630 
INST "*/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit1"   LOC = SLICE_X2Y38;
631 
INST "*/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit1" LOC = SLICE_X2Y39;
632 
 
633 
##################################################################################################
634 
##  constraints for bit ddr2_dq, 8, location in tile: 0
635 
##################################################################################################
636 
NET "ddr2_dq[8]" LOC = "AA2";     #bank 3
637 
INST "*/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit0"   LOC = SLICE_X0Y38;
638 
INST "*/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit0" LOC = SLICE_X0Y39;
639 
 
640 
##################################################################################################
641 
##  constraints for bit ddr2_dq, 11, location in tile: 0
642 
##################################################################################################
643 
NET "ddr2_dq[11]" LOC = "Y2";     #bank 3
644 
INST "*/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit3"   LOC = SLICE_X2Y42;
645 
INST "*/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit3" LOC = SLICE_X2Y43;
646 
 
647 
##################################################################################################
648 
##  constraints for bit ddr2_dq, 10, location in tile: 0
649 
##################################################################################################
650 
NET "ddr2_dq[10]" LOC = "Y1";     #bank 3
651 
INST "*/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit2"   LOC = SLICE_X0Y42;
652 
INST "*/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit2" LOC = SLICE_X0Y43;
653 
 
654 
##################################################################################################
655 
##  constraints for bit ddr2_dqs_n, 1, location in tile: 0
656 
##################################################################################################
657 
NET "ddr2_dqs_n[1]" LOC = "W4";     #bank 3
658 
 
659 
##################################################################################################
660 
##  constraints for bit ddr2_dqs, 1, location in tile: 0
661 
##################################################################################################
662 
NET "ddr2_dqs[1]" LOC = "W3";     #bank 3
663 
 
664 
##################################################################################################
665 
## LUT location constraints for dqs_delayed_col0
666 
##################################################################################################
667 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one" LOC = SLICE_X2Y45;
668 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one" BEL = F;
669 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two" LOC = SLICE_X2Y45;
670 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two" BEL = G;
671 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three" LOC = SLICE_X2Y44;
672 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three" BEL = G;
673 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four" LOC = SLICE_X2Y44;
674 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four" BEL = F;
675 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five" LOC = SLICE_X3Y45;
676 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five" BEL = G;
677 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six" LOC = SLICE_X3Y44;
678 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six" BEL = G;
679 
 
680 
##################################################################################################
681 
## LUT location constraints for dqs_delayed_col1
682 
##################################################################################################
683 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one" LOC = SLICE_X0Y45;
684 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one" BEL = F;
685 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two" LOC = SLICE_X0Y45;
686 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two" BEL = G;
687 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three" LOC = SLICE_X0Y44;
688 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three" BEL = G;
689 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four" LOC = SLICE_X0Y44;
690 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four" BEL = F;
691 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five" LOC = SLICE_X1Y45;
692 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five" BEL = G;
693 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six" LOC = SLICE_X1Y44;
694 
INST "*/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six" BEL = G;
695 
 
696 
##################################################################################################
697 
## Slice location constraints for Fifo write address and write enable
698 
##################################################################################################
699 
INST "*/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit0" LOC = SLICE_X1Y40;
700 
INST "*/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit1" LOC = SLICE_X1Y40;
701 
INST "*/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit2" LOC = SLICE_X1Y41;
702 
INST "*/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit3" LOC = SLICE_X1Y41;
703 
INST "*/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit0" LOC = SLICE_X3Y40;
704 
INST "*/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit1" LOC = SLICE_X3Y40;
705 
INST "*/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit2" LOC = SLICE_X3Y41;
706 
INST "*/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit3" LOC = SLICE_X3Y41;
707 
#INST "*/data_path0/data_read_controller0/gen_wr_en[1].fifo_0_wr_en_inst" LOC = SLICE_X1Y43;
708 
INST "*/data_path0/data_read_controller0/gen_wr_en[1].fifo_0_wr_en_inst/dout*" LOC = SLICE_X1Y43;
709 
#INST "*/data_path0/data_read_controller0/gen_wr_en[1].fifo_1_wr_en_inst" LOC = SLICE_X3Y43;
710 
INST "*/data_path0/data_read_controller0/gen_wr_en[1].fifo_1_wr_en_inst/dout*" LOC = SLICE_X3Y43;
711 
 
712 
##################################################################################################
713 
##  constraints for bit ddr2_dq, 13, location in tile: 0
714 
##################################################################################################
715 
NET "ddr2_dq[13]" LOC = "U6";     #bank 3
716 
INST "*/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit5"   LOC = SLICE_X2Y46;
717 
INST "*/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit5" LOC = SLICE_X2Y47;
718 
 
719 
##################################################################################################
720 
##  constraints for bit ddr2_dq, 12, location in tile: 0
721 
##################################################################################################
722 
NET "ddr2_dq[12]" LOC = "T7";     #bank 3
723 
INST "*/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit4"   LOC = SLICE_X0Y46;
724 
INST "*/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit4" LOC = SLICE_X0Y47;
725 
 
726 
##################################################################################################
727 
##  constraints for bit ddr2_dq, 15, location in tile: 0
728 
##################################################################################################
729 
NET "ddr2_dq[15]" LOC = "V5";     #bank 3
730 
INST "*/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit7"   LOC = SLICE_X2Y50;
731 
INST "*/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit7" LOC = SLICE_X2Y51;
732 
 
733 
##################################################################################################
734 
##  constraints for bit ddr2_dq, 14, location in tile: 0
735 
##################################################################################################
736 
NET "ddr2_dq[14]" LOC = "U5";     #bank 3
737 
INST "*/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit6"   LOC = SLICE_X0Y50;
738 
INST "*/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit6" LOC = SLICE_X0Y51;
739 
 
740 
##################################################################################################
741 
##  constraints for bit ddr2_dq, 16, location in tile: 0
742 
##################################################################################################
743 
# Not correct! Schematic on board says R8  Julius
744 
#NET "ddr2_dq[16]" LOC = "V1";     #bank 3
745 
#INST "*/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit0"   LOC = SLICE_X0Y54;
746 
#INST "*/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit0" LOC = SLICE_X0Y55;
747 
 
748 
NET "ddr2_dq[16]" LOC = "R8";     #bank 3
749 
INST "*/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit0"   LOC = SLICE_X0Y58;
750 
INST "*/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit0" LOC = SLICE_X0Y59;
751 
 
752 
 
753 
##################################################################################################
754 
##  constraints for bit ddr2_dq, 17, location in tile: 0
755 
##################################################################################################
756 
NET "ddr2_dq[17]" LOC = "R7";     #bank 3
757 
INST "*/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit1"   LOC = SLICE_X2Y58;
758 
INST "*/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit1" LOC = SLICE_X2Y59;
759 
 
760 
##################################################################################################
761 
##  constraints for bit ddr2_dq, 18, location in tile: 0
762 
##################################################################################################
763 
# Not correct! Schematic says U1 for this bit. - Julius
764 
#
765 
#NET "ddr2_dq[18]" LOC = "R8";     #bank 3
766 
#INST "*/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit2"   LOC = SLICE_X0Y58;
767 
#INST "*/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit2" LOC = SLICE_X0Y59;
768 
 
769 
NET "ddr2_dq[18]" LOC = "U1";     #bank 3
770 
 
771 
##################################################################################################
772 
##  constraints for bit ddr2_dq, 19, location in tile: 0
773 
##################################################################################################
774 
NET "ddr2_dq[19]" LOC = "U2";     #bank 3
775 
INST "*/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit3"   LOC = SLICE_X2Y60;
776 
INST "*/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit3" LOC = SLICE_X2Y61;
777 
 
778 
##################################################################################################
779 
##  constraints for bit ddr2_dqs_n, 2, location in tile: 0
780 
##################################################################################################
781 
NET "ddr2_dqs_n[2]" LOC = "U4";     #bank 3
782 
 
783 
##################################################################################################
784 
##  constraints for bit ddr2_dqs, 2, location in tile: 0
785 
##################################################################################################
786 
NET "ddr2_dqs[2]" LOC = "T5";     #bank 3
787 
 
788 
##################################################################################################
789 
## LUT location constraints for dqs_delayed_col0
790 
##################################################################################################
791 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/one" LOC = SLICE_X2Y67;
792 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/one" BEL = F;
793 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/two" LOC = SLICE_X2Y67;
794 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/two" BEL = G;
795 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/three" LOC = SLICE_X2Y66;
796 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/three" BEL = G;
797 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/four" LOC = SLICE_X2Y66;
798 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/four" BEL = F;
799 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/five" LOC = SLICE_X3Y67;
800 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/five" BEL = G;
801 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/six" LOC = SLICE_X3Y66;
802 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col0/six" BEL = G;
803 
 
804 
##################################################################################################
805 
## LUT location constraints for dqs_delayed_col1
806 
##################################################################################################
807 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/one" LOC = SLICE_X0Y67;
808 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/one" BEL = F;
809 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/two" LOC = SLICE_X0Y67;
810 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/two" BEL = G;
811 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/three" LOC = SLICE_X0Y66;
812 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/three" BEL = G;
813 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/four" LOC = SLICE_X0Y66;
814 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/four" BEL = F;
815 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/five" LOC = SLICE_X1Y67;
816 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/five" BEL = G;
817 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/six" LOC = SLICE_X1Y66;
818 
INST "*/data_path0/data_read_controller0/gen_delay[2].dqs_delay_col1/six" BEL = G;
819 
 
820 
##################################################################################################
821 
## Slice location constraints for Fifo write address and write enable
822 
##################################################################################################
823 
INST "*/data_path0/data_read_controller0/gen_wr_addr[2].fifo_0_wr_addr_inst/bit0" LOC = SLICE_X1Y62;
824 
INST "*/data_path0/data_read_controller0/gen_wr_addr[2].fifo_0_wr_addr_inst/bit1" LOC = SLICE_X1Y62;
825 
INST "*/data_path0/data_read_controller0/gen_wr_addr[2].fifo_0_wr_addr_inst/bit2" LOC = SLICE_X1Y63;
826 
INST "*/data_path0/data_read_controller0/gen_wr_addr[2].fifo_0_wr_addr_inst/bit3" LOC = SLICE_X1Y63;
827 
INST "*/data_path0/data_read_controller0/gen_wr_addr[2].fifo_1_wr_addr_inst/bit0" LOC = SLICE_X3Y62;
828 
INST "*/data_path0/data_read_controller0/gen_wr_addr[2].fifo_1_wr_addr_inst/bit1" LOC = SLICE_X3Y62;
829 
INST "*/data_path0/data_read_controller0/gen_wr_addr[2].fifo_1_wr_addr_inst/bit2" LOC = SLICE_X3Y63;
830 
INST "*/data_path0/data_read_controller0/gen_wr_addr[2].fifo_1_wr_addr_inst/bit3" LOC = SLICE_X3Y63;
831 
#INST "*/data_path0/data_read_controller0/gen_wr_en[2].fifo_0_wr_en_inst" LOC = SLICE_X1Y65;
832 
INST "*/data_path0/data_read_controller0/gen_wr_en[2].fifo_0_wr_en_inst/dout*" LOC = SLICE_X1Y65;
833 
#INST "*/data_path0/data_read_controller0/gen_wr_en[2].fifo_1_wr_en_inst" LOC = SLICE_X3Y65;
834 
INST "*/data_path0/data_read_controller0/gen_wr_en[2].fifo_1_wr_en_inst/dout*" LOC = SLICE_X3Y65;
835 
 
836 
##################################################################################################
837 
##  constraints for bit ddr2_dq, 21, location in tile: 0
838 
##################################################################################################
839 
NET "ddr2_dq[21]" LOC = "P9";     #bank 3
840 
INST "*/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit5"   LOC = SLICE_X2Y68;
841 
INST "*/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit5" LOC = SLICE_X2Y69;
842 
 
843 
##################################################################################################
844 
##  constraints for bit ddr2_dq, 20, location in tile: 0
845 
##################################################################################################
846 
NET "ddr2_dq[20]" LOC = "P8";     #bank 3
847 
INST "*/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit4"   LOC = SLICE_X0Y68;
848 
INST "*/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit4" LOC = SLICE_X0Y69;
849 
 
850 
##################################################################################################
851 
##  constraints for bit ddr2_dq, 23, location in tile: 0
852 
##################################################################################################
853 
NET "ddr2_dq[23]" LOC = "R6";     #bank 3
854 
INST "*/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit7"   LOC = SLICE_X2Y70;
855 
INST "*/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit7" LOC = SLICE_X2Y71;
856 
 
857 
##################################################################################################
858 
##  constraints for bit ddr2_dq, 22, location in tile: 0
859 
##################################################################################################
860 
NET "ddr2_dq[22]" LOC = "R5";     #bank 3
861 
INST "*/data_path0/data_read0/gen_strobe[2].strobe/fifo_bit6"   LOC = SLICE_X0Y70;
862 
INST "*/data_path0/data_read0/gen_strobe[2].strobe_n/fifo_bit6" LOC = SLICE_X0Y71;
863 
 
864 
##################################################################################################
865 
##  constraints for bit ddr2_dq, 25, location in tile: 0
866 
##################################################################################################
867 
NET "ddr2_dq[25]" LOC = "P6";     #bank 3
868 
INST "*/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit1"   LOC = SLICE_X2Y74;
869 
INST "*/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit1" LOC = SLICE_X2Y75;
870 
 
871 
##################################################################################################
872 
##  constraints for bit ddr2_dq, 24, location in tile: 0
873 
##################################################################################################
874 
NET "ddr2_dq[24]" LOC = "P7";     #bank 3
875 
INST "*/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit0"   LOC = SLICE_X0Y74;
876 
INST "*/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit0" LOC = SLICE_X0Y75;
877 
 
878 
##################################################################################################
879 
##  constraints for bit ddr2_dq, 27, location in tile: 0
880 
##################################################################################################
881 
NET "ddr2_dq[27]" LOC = "T4";     #bank 3
882 
INST "*/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit3"   LOC = SLICE_X2Y76;
883 
INST "*/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit3" LOC = SLICE_X2Y77;
884 
 
885 
##################################################################################################
886 
##  constraints for bit ddr2_dq, 26, location in tile: 0
887 
##################################################################################################
888 
NET "ddr2_dq[26]" LOC = "T3";     #bank 3
889 
INST "*/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit2"   LOC = SLICE_X0Y76;
890 
INST "*/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit2" LOC = SLICE_X0Y77;
891 
 
892 
##################################################################################################
893 
##  constraints for bit ddr2_dqs_n, 3, location in tile: 0
894 
##################################################################################################
895 
NET "ddr2_dqs_n[3]" LOC = "R4";     #bank 3
896 
 
897 
##################################################################################################
898 
##  constraints for bit ddr2_dqs, 3, location in tile: 0
899 
##################################################################################################
900 
NET "ddr2_dqs[3]" LOC = "R3";     #bank 3
901 
 
902 
##################################################################################################
903 
## LUT location constraints for dqs_delayed_col0
904 
##################################################################################################
905 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/one" LOC = SLICE_X2Y79;
906 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/one" BEL = F;
907 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/two" LOC = SLICE_X2Y79;
908 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/two" BEL = G;
909 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/three" LOC = SLICE_X2Y78;
910 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/three" BEL = G;
911 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/four" LOC = SLICE_X2Y78;
912 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/four" BEL = F;
913 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/five" LOC = SLICE_X3Y79;
914 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/five" BEL = G;
915 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/six" LOC = SLICE_X3Y78;
916 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col0/six" BEL = G;
917 
 
918 
##################################################################################################
919 
## LUT location constraints for dqs_delayed_col1
920 
##################################################################################################
921 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/one" LOC = SLICE_X0Y79;
922 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/one" BEL = F;
923 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/two" LOC = SLICE_X0Y79;
924 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/two" BEL = G;
925 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/three" LOC = SLICE_X0Y78;
926 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/three" BEL = G;
927 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/four" LOC = SLICE_X0Y78;
928 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/four" BEL = F;
929 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/five" LOC = SLICE_X1Y79;
930 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/five" BEL = G;
931 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/six" LOC = SLICE_X1Y78;
932 
INST "*/data_path0/data_read_controller0/gen_delay[3].dqs_delay_col1/six" BEL = G;
933 
 
934 
##################################################################################################
935 
## Slice location constraints for Fifo write address and write enable
936 
##################################################################################################
937 
INST "*/data_path0/data_read_controller0/gen_wr_addr[3].fifo_0_wr_addr_inst/bit0" LOC = SLICE_X1Y74;
938 
INST "*/data_path0/data_read_controller0/gen_wr_addr[3].fifo_0_wr_addr_inst/bit1" LOC = SLICE_X1Y74;
939 
INST "*/data_path0/data_read_controller0/gen_wr_addr[3].fifo_0_wr_addr_inst/bit2" LOC = SLICE_X1Y75;
940 
INST "*/data_path0/data_read_controller0/gen_wr_addr[3].fifo_0_wr_addr_inst/bit3" LOC = SLICE_X1Y75;
941 
INST "*/data_path0/data_read_controller0/gen_wr_addr[3].fifo_1_wr_addr_inst/bit0" LOC = SLICE_X3Y74;
942 
INST "*/data_path0/data_read_controller0/gen_wr_addr[3].fifo_1_wr_addr_inst/bit1" LOC = SLICE_X3Y74;
943 
INST "*/data_path0/data_read_controller0/gen_wr_addr[3].fifo_1_wr_addr_inst/bit2" LOC = SLICE_X3Y75;
944 
INST "*/data_path0/data_read_controller0/gen_wr_addr[3].fifo_1_wr_addr_inst/bit3" LOC = SLICE_X3Y75;
945 
#INST "*/data_path0/data_read_controller0/gen_wr_en[3].fifo_0_wr_en_inst" LOC = SLICE_X1Y77;
946 
INST "*/data_path0/data_read_controller0/gen_wr_en[3].fifo_0_wr_en_inst/dout*" LOC = SLICE_X1Y77;
947 
#INST "*/data_path0/data_read_controller0/gen_wr_en[3].fifo_1_wr_en_inst" LOC = SLICE_X3Y77;
948 
INST "*/data_path0/data_read_controller0/gen_wr_en[3].fifo_1_wr_en_inst/dout*" LOC = SLICE_X3Y77;
949 
 
950 
##################################################################################################
951 
##  constraints for bit ddr2_dq, 29, location in tile: 0
952 
##################################################################################################
953 
# Not correct! Schematic says P10 - Julius
954 
#NET "ddr2_dq[29]" LOC = "R2";     #bank 3
955 
#INST "*/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit5"   LOC = SLICE_X2Y82;
956 
#INST "*/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit5" LOC = SLICE_X2Y83;
957 
 
958 
NET "ddr2_dq[29]" LOC = "P10";     #bank 3
959 
 
960 
##################################################################################################
961 
##  constraints for bit ddr2_dq, 28, location in tile: 0
962 
##################################################################################################
963 
NET "ddr2_dq[28]" LOC = "N9";     #bank 3
964 
INST "*/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit4"   LOC = SLICE_X0Y84;
965 
INST "*/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit4" LOC = SLICE_X0Y85;
966 
 
967 
##################################################################################################
968 
##  constraints for bit ddr2_dq, 31, location in tile: 0
969 
##################################################################################################
970 
NET "ddr2_dq[31]" LOC = "P3";     #bank 3
971 
INST "*/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit7"   LOC = SLICE_X2Y86;
972 
INST "*/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit7" LOC = SLICE_X2Y87;
973 
 
974 
##################################################################################################
975 
##  constraints for bit ddr2_dq, 30, location in tile: 0
976 
##################################################################################################
977 
NET "ddr2_dq[30]" LOC = "P4";     #bank 3
978 
INST "*/data_path0/data_read0/gen_strobe[3].strobe/fifo_bit6"   LOC = SLICE_X0Y86;
979 
INST "*/data_path0/data_read0/gen_strobe[3].strobe_n/fifo_bit6" LOC = SLICE_X0Y87;
980 
 
981 
##################################################################################################
982 
##  constraints for bit rst_dqs_div_in, 1, location in tile: 1
983 
##################################################################################################
984 
NET "ddr2_rst_dqs_div_in" LOC = "T9";     #bank 3
985 
 
986 
##################################################################################################
987 
## Slice location constraints for delayed rst_dqs_div signal
988 
##################################################################################################
989 
INST "*/data_path0/data_read_controller0/rst_dqs_div_delayed/one" LOC = SLICE_X0Y53;
990 
INST "*/data_path0/data_read_controller0/rst_dqs_div_delayed/one" BEL = F;
991 
INST "*/data_path0/data_read_controller0/rst_dqs_div_delayed/two" LOC = SLICE_X0Y52;
992 
INST "*/data_path0/data_read_controller0/rst_dqs_div_delayed/two" BEL = G;
993 
INST "*/data_path0/data_read_controller0/rst_dqs_div_delayed/three" LOC = SLICE_X0Y53;
994 
INST "*/data_path0/data_read_controller0/rst_dqs_div_delayed/three" BEL = G;
995 
INST "*/data_path0/data_read_controller0/rst_dqs_div_delayed/four" LOC = SLICE_X1Y52;
996 
INST "*/data_path0/data_read_controller0/rst_dqs_div_delayed/four" BEL = F;
997 
INST "*/data_path0/data_read_controller0/rst_dqs_div_delayed/five" LOC = SLICE_X1Y52;
998 
INST "*/data_path0/data_read_controller0/rst_dqs_div_delayed/five" BEL = G;
999 
INST "*/data_path0/data_read_controller0/rst_dqs_div_delayed/six" LOC = SLICE_X1Y53;
1000 
INST "*/data_path0/data_read_controller0/rst_dqs_div_delayed/six" BEL = G;
1001 
 
1002 
##################################################################################################
1003 
##  constraints for bit rst_dqs_div_out, 1, location in tile: 0
1004 
##################################################################################################
1005 
NET "ddr2_rst_dqs_div_out" LOC = "T10";     #bank 3
1006 
 
1007 
##################################################################################################
1008 
## Location constraint for rst_dqs_div_r flop in the controller. This is to be placed close the PAD
1009 
## that drives the rst_dqs_div _out signal to meet the timing.
1010 
##################################################################################################
1011 
INST "*/controller0/rst_dqs_div_r" LOC = SLICE_X4Y52;
1012 
##################################################################################################
1013 
 
1014 
## DDR controller cache interface domain crossing timing ignores
1015 
 
1016 
NET "wb_clk" TNM_NET = "WB_CLK";
1017 
NET "xilinx_s3adsp_ddr2/xilinx_s3adsp_ddr2_if/ddr2_if_clk" TNM_NET = "DDR2_IF_CLK";
1018 
 
1019 
# Path constraints - if bus clock is 50Mhz they have 20ns
1020 
TIMESPEC TS_ddr2_controller_false_paths = FROM "WB_CLK" to "DDR2_IF_CLK" TIG;
1021 
TIMESPEC TS_ddr2_controller_false_paths2 = FROM "DDR2_IF_CLK" to "WB_CLK" TIG;
1022 
 
1023 
 
1024 
#### Module FLASH_16Mx8 constraints
1025 
# Controller not present, so commenting out - Julius
1026 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<31>  LOC="AC23" | IOSTANDARD = LVCMOS33; # Flash A0
1027 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<30>  LOC="AC24" | IOSTANDARD = LVCMOS33;
1028 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<29>  LOC="R21"  | IOSTANDARD = LVCMOS33;
1029 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<28>  LOC="R22"  | IOSTANDARD = LVCMOS33;
1030 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<27>  LOC="T23"  | IOSTANDARD = LVCMOS33;
1031 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<26>  LOC="T24"  | IOSTANDARD = LVCMOS33;
1032 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<25>  LOC="R18"  | IOSTANDARD = LVCMOS33;
1033 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<24>  LOC="R17"  | IOSTANDARD = LVCMOS33;
1034 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<23>  LOC="R25"  | IOSTANDARD = LVCMOS33;
1035 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<22>  LOC="R26"  | IOSTANDARD = LVCMOS33;
1036 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<21>  LOC="M26"  | IOSTANDARD = LVCMOS33;
1037 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<20>  LOC="M25"  | IOSTANDARD = LVCMOS33;
1038 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<19>  LOC="L24"  | IOSTANDARD = LVCMOS33;
1039 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<18>  LOC="M23"  | IOSTANDARD = LVCMOS33;
1040 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<17>  LOC="N18"  | IOSTANDARD = LVCMOS33;
1041 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<16>  LOC="N17"  | IOSTANDARD = LVCMOS33;
1042 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<15>  LOC="N20"  | IOSTANDARD = LVCMOS33;
1043 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<14>  LOC="M20"  | IOSTANDARD = LVCMOS33;
1044 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<13>  LOC="J26"  | IOSTANDARD = LVCMOS33;
1045 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<12>  LOC="J25"  | IOSTANDARD = LVCMOS33;
1046 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<11>  LOC="J21"  | IOSTANDARD = LVCMOS33;
1047 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<10>  LOC="H21"  | IOSTANDARD = LVCMOS33;
1048 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<9>   LOC="C26"  | IOSTANDARD = LVCMOS33;
1049 
#Net fpga_0_FLASH_16Mx8_Mem_A_pin<8>   LOC="C25"  | IOSTANDARD = LVCMOS33; # Flash A23
1050 
#Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<0>  LOC="AE10" | IOSTANDARD = LVCMOS25; # Flash D7
1051 
#Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<1>  LOC="AF10" | IOSTANDARD = LVCMOS25;
1052 
#Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<2>  LOC="AF12" | IOSTANDARD = LVCMOS25;
1053 
#Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<3>  LOC="AE12" | IOSTANDARD = LVCMOS25;
1054 
#Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<4>  LOC="Y15"  | IOSTANDARD = LVCMOS25;
1055 
#Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<5>  LOC="AF18" | IOSTANDARD = LVCMOS25;
1056 
#Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<6>  LOC="AE18" | IOSTANDARD = LVCMOS25;
1057 
#Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<7>  LOC="AF24" | IOSTANDARD = LVCMOS25; # Flash D0
1058 
#Net fpga_0_FLASH_16Mx8_Mem_WEN_pin    LOC="Y20"  | IOSTANDARD = LVCMOS33;
1059 
#Net fpga_0_FLASH_16Mx8_Mem_OEN_pin<0> LOC="AE26" | IOSTANDARD = LVCMOS33;
1060 
#Net fpga_0_FLASH_16Mx8_Mem_CEN_pin<0> LOC="AD25" | IOSTANDARD = LVCMOS33;
1061 
#Net fpga_0_FLASH_16Mx8_rpn_dummy_pin  LOC="N24"  | IOSTANDARD = LVCMOS33;
1062 
 
1063 
#### Module Ethernet_MAC constraints
1064 
 
1065 
Net eth0_tx_er LOC="E4" | IOSTANDARD = LVCMOS18; # "Dummy" pin
1066 
Net eth0_tx_clk LOC="P2" | IOSTANDARD = LVCMOS18;
1067 
Net eth0_tx_en LOC="D3" | IOSTANDARD = LVCMOS18;
1068 
Net eth0_tx_data<3> LOC="B1" | IOSTANDARD = LVCMOS18;
1069 
Net eth0_tx_data<2> LOC="B2" | IOSTANDARD = LVCMOS18;
1070 
Net eth0_tx_data<1> LOC="J9" | IOSTANDARD = LVCMOS18;
1071 
Net eth0_tx_data<0> LOC="J8" | IOSTANDARD = LVCMOS18;
1072 
 
1073 
Net eth0_crs LOC="G1" | IOSTANDARD = LVCMOS18;
1074 
Net eth0_crs IOBDELAY=NONE;
1075 
Net eth0_col LOC="Y3" | IOSTANDARD = LVCMOS18;
1076 
Net eth0_col IOBDELAY=NONE;
1077 
 
1078 
 
1079 
Net eth0_rx_clk LOC="P1" | IOSTANDARD = LVCMOS18;
1080 
 
1081 
Net eth0_dv LOC="D1" | IOSTANDARD = LVCMOS18;
1082 
Net eth0_dv IOBDELAY=NONE;
1083 
Net eth0_rx_data<0> LOC="C2" | IOSTANDARD = LVCMOS18;
1084 
Net eth0_rx_data<0> IOBDELAY=NONE;
1085 
Net eth0_rx_data<1> LOC="G2" | IOSTANDARD = LVCMOS18;
1086 
Net eth0_rx_data<1> IOBDELAY=NONE;
1087 
Net eth0_rx_data<2> LOC="G5" | IOSTANDARD = LVCMOS18;
1088 
Net eth0_rx_data<2> IOBDELAY=NONE;
1089 
Net eth0_rx_data<3> LOC="D2" | IOSTANDARD = LVCMOS18;
1090 
Net eth0_rx_data<3> IOBDELAY=NONE;
1091 
Net eth0_rx_er LOC="J3" | IOSTANDARD = LVCMOS18;
1092 
Net eth0_rx_er IOBDELAY=NONE;
1093 
 
1094 
Net eth0_rst_n_o LOC="G4" | IOSTANDARD = LVCMOS18;
1095 
 
1096 
Net eth0_mdc_pad_o LOC="F4" | IOSTANDARD = LVCMOS18;
1097 
Net eth0_md_pad_io LOC="F5" | IOSTANDARD = LVCMOS18;
1098 
 
1099 
#Net eth0_rx_clk PERIOD=40000 ps;
1100 
Net eth0_rx_clk TNM_NET = eth0_rx_clk;
1101 
TIMESPEC TS_eth0_rx_clk = PERIOD eth0_rx_clk 40000 ps;
1102 
#Net eth0_tx_clk PERIOD=40000 ps;
1103 
Net eth0_tx_clk TNM_NET = eth0_tx_clk;
1104 
TIMESPEC TS_eth0_tx_clk = PERIOD eth0_tx_clk 40000 ps;
1105 
 
1106 
###################################################################################3
1107 
# EXP Expansion Connector JX1
1108 
 
1109 
# JX1 - Outputs: 36 Single-ended, 48 Differential (24 pairs)
1110 
#NET se_o_grp1<0>   LOC ="C22" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_0"
1111 
#NET se_o_grp1<1>   LOC ="A22" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_2"
1112 
#NET se_o_grp1<2>   LOC ="C21" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_4"
1113 
#NET se_o_grp1<3>   LOC ="B21" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_6"
1114 
#NET se_o_grp1<4>   LOC ="C20" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_8"
1115 
#NET se_o_grp1<5>   LOC ="B20" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_10"
1116 
#NET se_o_grp1<6>   LOC ="A20" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_12"
1117 
#NET se_o_grp1<7>   LOC ="D20" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_14"
1118 
#NET se_o_grp1<8>   LOC ="B19" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_16"
1119 
#NET se_o_grp1<9>   LOC ="A19" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_18"
1120 
#NET se_o_grp1<10>  LOC ="C18" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_20"
1121 
#NET se_o_grp1<11>  LOC ="B18" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_22"
1122 
#NET se_o_grp1<12>  LOC ="A18" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_24"
1123 
#NET se_o_grp1<13>  LOC ="C17" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_26"
1124 
#NET se_o_grp1<14>  LOC ="B14" | IOSTANDARD = LVCMOS25; # "EXP1_DIFF_CLK_IN_P"
1125 
#NET se_o_grp1<15>  LOC ="A14" | IOSTANDARD = LVCMOS25; # "EXP1_DIFF_CLK_IN_N"
1126 
#NET se_o_grp1<16>  LOC ="D17" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_30"
1127 
#NET se_o_grp1<17>  LOC ="B17" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_31"
1128 
#NET se_o_grp1<18>  LOC ="G20" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_1"
1129 
#NET se_o_grp1<19>  LOC ="G19" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_3"
1130 
#NET se_o_grp1<20>  LOC ="E21" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_5"
1131 
#NET se_o_grp1<21>  LOC ="D23" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_7"
1132 
#NET se_o_grp1<22>  LOC ="B23" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_9"
1133 
#NET se_o_grp1<23>  LOC ="C23" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_11"
1134 
#NET se_o_grp1<24>  LOC ="D22" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_13"
1135 
#NET se_o_grp1<25>  LOC ="D21" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_15"
1136 
#NET se_o_grp1<26>  LOC ="F20" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_17"
1137 
#NET se_o_grp1<27>  LOC ="H17" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_19"
1138 
#NET se_o_grp1<28>  LOC ="F19" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_21"
1139 
#NET se_o_grp1<29>  LOC ="G17" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_23"
1140 
#NET se_o_grp1<30>  LOC ="K16" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_25"
1141 
#NET se_o_grp1<31>  LOC ="F17" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_27"
1142 
 
1143 
#NET se_o_grp2<0>   LOC ="D18" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_28"
1144 
#NET se_o_grp2<1>   LOC ="J14" | IOSTANDARD = LVCMOS25; # "EXP1_SE_CLK_IN"
1145 
#NET se_o_grp2<2>   LOC ="E17" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_29"
1146 
#NET se_o_grp2<3>   LOC ="G10" | IOSTANDARD = LVCMOS25; # "EXP1_SE_CLK_OUT"
1147 
#NET se_o_grp2<4>   LOC ="C16" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_32"
1148 
#NET se_o_grp2<5>   LOC ="J16" | IOSTANDARD = LVCMOS25; # "EXP1_SE_IO_33"
1149 
# DIFF pair 10 is on "CC" I/O so have to make single-ended to be outputs
1150 
#NET se_o_grp2<6>   LOC ="C13" | IOSTANDARD = LVCMOS25; # "EXP1_DIFF_N10"
1151 
#NET se_o_grp2<7>   LOC ="B13" | IOSTANDARD = LVCMOS25; # "EXP1_DIFF_P10"
1152 
 
1153 
#NET dp_o_grp3<0>   LOC ="D6"  | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N0"
1154 
#NET dp_o_grp3<1>   LOC ="C6"  | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N2"
1155 
#NET dp_o_grp3<2>   LOC ="C7"  | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N4"
1156 
#NET dp_o_grp3<3>   LOC ="B8"  | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N6"
1157 
#NET dp_o_grp3<4>   LOC ="B9"  | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N8"
1158 
#NET dp_o_grp3<5>   LOC ="D10" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N12"
1159 
#NET dp_o_grp3<6>   LOC ="D11" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N14"
1160 
#NET dp_o_grp3<7>   LOC ="B4"  | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_CLK_OUT_N"
1161 
#NET dp_o_grp3<8>   LOC ="B12" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N16"
1162 
#NET dp_o_grp3<9>   LOC ="C12" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N18"
1163 
#NET dp_o_grp3<10>  LOC ="C15" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N20"
1164 
#NET dp_o_grp3<11>  LOC ="K11" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N1"
1165 
#NET dp_o_grp3<12>  LOC ="D8"  | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N3"
1166 
#NET dp_o_grp3<13>  LOC ="D9"  | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N5"
1167 
#NET dp_o_grp3<14>  LOC ="B10" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N7"
1168 
#NET dp_o_grp3<15>  LOC ="K12" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N9"
1169 
 
1170 
#NET dp_o_grp3<16>  LOC ="C5"  | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P0"
1171 
#NET dp_o_grp3<17>  LOC ="B6"  | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P2"
1172 
#NET dp_o_grp3<18>  LOC ="B7"  | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P4"
1173 
#NET dp_o_grp3<19>  LOC ="A8"  | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P6"
1174 
#NET dp_o_grp3<20>  LOC ="A9"  | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P8"
1175 
#NET dp_o_grp3<21>  LOC ="C10" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P12"
1176 
#NET dp_o_grp3<22>  LOC ="C11" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P14"
1177 
#NET dp_o_grp3<23>  LOC ="A4"  | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_CLK_OUT_P"
1178 
#NET dp_o_grp3<24>  LOC ="A12" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P16"
1179 
#NET dp_o_grp3<25>  LOC ="D13" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P18"
1180 
#NET dp_o_grp3<26>  LOC ="D16" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P20"
1181 
#NET dp_o_grp3<27>  LOC ="J11" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P1"
1182 
#NET dp_o_grp3<28>  LOC ="C8"  | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P3"
1183 
#NET dp_o_grp3<29>  LOC ="E10" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P5"
1184 
#NET dp_o_grp3<30>  LOC ="A10" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P7"
1185 
#NET dp_o_grp3<31>  LOC ="J12" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P9"
1186 
 
1187 
#NET dp_o_grp4<0>   LOC ="F12" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N11"
1188 
#NET dp_o_grp4<1>   LOC ="H12" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N13"
1189 
#NET dp_o_grp4<2>   LOC ="H15" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N15"
1190 
#NET dp_o_grp4<3>   LOC ="F14" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N17"
1191 
#NET dp_o_grp4<4>   LOC ="E15" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N19"
1192 
#NET dp_o_grp4<5>   LOC ="A15" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_N21"
1193 
 
1194 
#NET dp_o_grp4<6>   LOC ="E12" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P11"
1195 
#NET dp_o_grp4<7>   LOC ="G12" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P13"
1196 
#NET dp_o_grp4<8>   LOC ="G15" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P15"
1197 
#NET dp_o_grp4<9>   LOC ="E14" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P17"
1198 
#NET dp_o_grp4<10>  LOC ="F15" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P19"
1199 
#NET dp_o_grp4<11>  LOC ="B15" | IOSTANDARD = LVDS_25;  # "EXP1_DIFF_P21"
1200 
 
1201 
# EXP Expansion Connector JX2
1202 
 
1203 
# JX2 - Inputs: 36 Single-ended, 48 Differential (24 pairs)
1204 
#NET se_i_grp1<0>   LOC ="V16"  | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_0"
1205 
#NET se_i_grp1<1>   LOC ="Y17"  | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_2"
1206 
#NET se_i_grp1<2>   LOC ="AA18" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_4"
1207 
#NET se_i_grp1<3>   LOC ="AC20" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_6"
1208 
#NET se_i_grp1<4>   LOC ="AA17" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_8"
1209 
#NET se_i_grp1<5>   LOC ="AC19" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_10"
1210 
#NET se_i_grp1<6>   LOC ="AB18" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_12"
1211 
#NET se_i_grp1<7>   LOC ="V15"  | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_14"
1212 
#NET se_i_grp1<8>   LOC ="W15"  | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_16"
1213 
#NET se_i_grp1<9>   LOC ="AB16" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_18"
1214 
#NET se_i_grp1<10>  LOC ="M21"  | IOSTANDARD = LVCMOS33; # "EXP2_SE_IO_20"
1215 
#NET se_i_grp1<11>  LOC ="AC16" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_22"
1216 
#NET se_i_grp1<12>  LOC ="U22"  | IOSTANDARD = LVCMOS33; # "EXP2_SE_IO_24"
1217 
#NET se_i_grp1<13>  LOC ="AC15" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_26"
1218 
#NET se_i_grp1<14>  LOC ="AA13" | IOSTANDARD = LVCMOS25; # "EXP2_DIFF_CLK_IN_P"
1219 
#NET se_i_grp1<15>  LOC ="Y13"  | IOSTANDARD = LVCMOS25; # "EXP2_DIFF_CLK_IN_N"
1220 
#NET se_i_grp1<16>  LOC ="V14"  | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_30"
1221 
#NET se_i_grp1<17>  LOC ="U15"  | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_31"
1222 
#NET se_i_grp1<18>  LOC ="AE25" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_1"
1223 
#NET se_i_grp1<19>  LOC ="AF25" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_3"
1224 
#NET se_i_grp1<20>  LOC ="AE23" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_5"
1225 
#NET se_i_grp1<21>  LOC ="AF23" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_7"
1226 
#NET se_i_grp1<22>  LOC ="AD22" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_9"
1227 
#NET se_i_grp1<23>  LOC ="AE21" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_11"
1228 
#NET se_i_grp1<24>  LOC ="AD21" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_13"
1229 
#NET se_i_grp1<25>  LOC ="AC21" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_15"
1230 
#NET se_i_grp1<26>  LOC ="U23"  | IOSTANDARD = LVCMOS33; # "EXP2_SE_IO_17"
1231 
#NET se_i_grp1<27>  LOC ="U24"  | IOSTANDARD = LVCMOS33; # "EXP2_SE_IO_19"
1232 
#NET se_i_grp1<28>  LOC ="AD20" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_21"
1233 
#NET se_i_grp1<29>  LOC ="AF19" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_23"
1234 
#NET se_i_grp1<30>  LOC ="AE19" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_25"
1235 
#NET se_i_grp1<31>  LOC ="AD19" | IOSTANDARD = LVCMOS25; # "EXP2_SE_IO_27"
1236 
 
1237 
#NET se_i_grp2<0>   LOC ="R20"  | IOSTANDARD = LVCMOS33; # "EXP2_SE_IO_28"
1238 
#NET se_i_grp2<1>   LOC ="AF13" | IOSTANDARD = LVCMOS25; # "EXP2_SE_CLK_IN"
1239 
#NET se_i_grp2<2>   LOC ="R19"  | IOSTANDARD = LVCMOS33; # "EXP2_SE_IO_29"
1240 
#NET se_i_grp2<3>   LOC ="Y14"  | IOSTANDARD = LVCMOS25; # "EXP2_SE_CLK_OUT"
1241 
#NET se_i_grp2<4>   LOC ="K23"  | IOSTANDARD = LVCMOS33; # "EXP2_SE_IO_32"
1242 
#NET se_i_grp2<5>   LOC ="M22"  | IOSTANDARD = LVCMOS33; # "EXP2_SE_IO_33"
1243 
# DIFF pair 10 is on "CC" I/O so have to make single-ended to be outputs
1244 
#NET se_i_grp2<6>   LOC ="AE14" | IOSTANDARD = LVCMOS25; # "EXP2_DIFF_N10"
1245 
#NET se_i_grp2<7>   LOC ="AF14" | IOSTANDARD = LVCMOS25; # "EXP2_DIFF_P10"
1246 
 
1247 
#NET dp_i_grp3<0>   LOC ="AE6"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N0"
1248 
#NET dp_i_grp3<1>   LOC ="U11"  | IOSTANDARD = LVDS_25; # "EXP1_DIFF_N2"
1249 
#NET dp_i_grp3<2>   LOC ="Y9"   | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N4"
1250 
#NET dp_i_grp3<3>   LOC ="AA10" | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N6"
1251 
#NET dp_i_grp3<4>   LOC ="AC9"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N8"
1252 
#NET dp_i_grp3<5>   LOC ="AC11" | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N12"
1253 
#NET dp_i_grp3<6>   LOC ="W12"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N14"
1254 
#NET dp_i_grp3<7>   LOC ="V17"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_CLK_OUT_N"
1255 
#NET dp_i_grp3<8>   LOC ="AA12" | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N16"
1256 
#NET dp_i_grp3<9>   LOC ="W13"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N18"
1257 
#NET dp_i_grp3<10>  LOC ="W10"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N20"
1258 
#NET dp_i_grp3<11>  LOC ="AF3"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N1"
1259 
#NET dp_i_grp3<12>  LOC ="AF4"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N3"
1260 
#NET dp_i_grp3<13>  LOC ="AB7"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N5"
1261 
#NET dp_i_grp3<14>  LOC ="AD6"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N7"
1262 
#NET dp_i_grp3<15>  LOC ="AE7"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N9"
1263 
 
1264 
#NET dp_i_grp3<16>  LOC ="AF5"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P0"
1265 
#NET dp_i_grp3<17>  LOC ="V11"  | IOSTANDARD = LVDS_25; # "EXP1_DIFF_P2"
1266 
#NET dp_i_grp3<18>  LOC ="W9"   | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P4"
1267 
#NET dp_i_grp3<19>  LOC ="Y10"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P6"
1268 
#NET dp_i_grp3<20>  LOC ="AB9"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P8"
1269 
#NET dp_i_grp3<21>  LOC ="AD11" | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P12"
1270 
#NET dp_i_grp3<22>  LOC ="V12"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P14"
1271 
#NET dp_i_grp3<23>  LOC ="W17"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_CLK_OUT_P"
1272 
#NET dp_i_grp3<24>  LOC ="Y12"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P16"
1273 
#NET dp_i_grp3<25>  LOC ="V13"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P18"
1274 
#NET dp_i_grp3<26>  LOC ="V10"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P20"
1275 
#NET dp_i_grp3<27>  LOC ="AE3"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P1"
1276 
#NET dp_i_grp3<28>  LOC ="AE4"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P3"
1277 
#NET dp_i_grp3<29>  LOC ="AC8"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P5"
1278 
#NET dp_i_grp3<30>  LOC ="AC6"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P7"
1279 
#NET dp_i_grp3<31>  LOC ="AD7"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P9"
1280 
 
1281 
#NET dp_i_grp4<0>   LOC ="AF8"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N11"
1282 
#NET dp_i_grp4<1>   LOC ="AF9"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N13"
1283 
#NET dp_i_grp4<2>   LOC ="AE20" | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N15"
1284 
#NET dp_i_grp4<3>   LOC ="AD17" | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N17"
1285 
#NET dp_i_grp4<4>   LOC ="AC12" | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N19"
1286 
#NET dp_i_grp4<5>   LOC ="AC14" | IOSTANDARD = LVDS_25; # "EXP2_DIFF_N21"
1287 
 
1288 
#NET dp_i_grp4<6>   LOC ="AE8"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P11"
1289 
#NET dp_i_grp4<7>   LOC ="AE9"  | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P13"
1290 
#NET dp_i_grp4<8>   LOC ="AF20" | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P15"
1291 
#NET dp_i_grp4<9>   LOC ="AE17" | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P17"
1292 
#NET dp_i_grp4<10>  LOC ="AB12" | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P19"
1293 
#NET dp_i_grp4<11>  LOC ="AD14" | IOSTANDARD = LVDS_25; # "EXP2_DIFF_P21"
1294 
 
1295 
#INST "jx1_to_jx2/jx1_to_jx2/nextbus_block/dp_i_grp3_ibufds*" DIFF_TERM = TRUE;
1296 
#INST "jx1_to_jx2/jx1_to_jx2/nextbus_block/dp_i_grp4_ibufds*" DIFF_TERM = TRUE;
1297 
 
1298 
#### DAC out
1299 
#NET "CLK_25_175MHZ" LOC ="P26" | IOSTANDARD = LVCMOS33;
1300 
#NET "DAC_HSYNC"     LOC ="K26" | IOSTANDARD = LVCMOS33;
1301 
#NET "DAC_VSYNC"     LOC ="K25" | IOSTANDARD = LVCMOS33;
1302 
#NET "DAC_RGB<0>"    LOC ="L22" | IOSTANDARD = LVCMOS33;
1303 
#NET "DAC_RGB<1>"    LOC ="K21" | IOSTANDARD = LVCMOS33;
1304 
#NET "DAC_RGB<2>"    LOC ="G23" | IOSTANDARD = LVCMOS33;
1305 
#NET "DAC_RGB<3>"    LOC ="G24" | IOSTANDARD = LVCMOS33;
1306 
#NET "DAC_RGB<4>"    LOC ="M19" | IOSTANDARD = LVCMOS33;
1307 
#NET "DAC_RGB<5>"    LOC ="M18" | IOSTANDARD = LVCMOS33;
1308 
#NET "DAC_RGB<6>"    LOC ="J23" | IOSTANDARD = LVCMOS33;
1309 
#NET "DAC_RGB<7>"    LOC ="J22" | IOSTANDARD = LVCMOS33;
1310 
#NET "DAC_RGB<8>"    LOC ="L20" | IOSTANDARD = LVCMOS33;
1311 
#NET "DAC_RGB<9>"    LOC ="K20" | IOSTANDARD = LVCMOS33;
1312 
#NET "DAC_RGB<10>"   LOC ="F25" | IOSTANDARD = LVCMOS33;
1313 
#NET "DAC_RGB<11>"   LOC ="F24" | IOSTANDARD = LVCMOS33;
1314 
 
1315 
#### Module SysACE_CompactFlash constraints
1316 
 
1317 
#Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC = AA14   | IOSTANDARD = LVCMOS33;
1318 
#Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin TNM_NET = sysace_clk;
1319 
#TIMESPEC TS_sysace_clk = PERIOD sysace_clk 41667 ps;
1320 
 
1321 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0>  LOC = AC26   | IOSTANDARD = LVCMOS33;
1322 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1>  LOC = AB26   | IOSTANDARD = LVCMOS33;
1323 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2>  LOC = AB23   | IOSTANDARD = LVCMOS33;
1324 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3>  LOC = AB24   | IOSTANDARD = LVCMOS33;
1325 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4>  LOC = V18    | IOSTANDARD = LVCMOS33;
1326 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5>  LOC = V19    | IOSTANDARD = LVCMOS33;
1327 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6>  LOC = AA22   | IOSTANDARD = LVCMOS33;
1328 
 
1329 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0>  LOC = AA23   | IOSTANDARD = LVCMOS33;
1330 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1>  LOC = V21    | IOSTANDARD = LVCMOS33;
1331 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2>  LOC = U20    | IOSTANDARD = LVCMOS33;
1332 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3>  LOC = AA24   | IOSTANDARD = LVCMOS33;
1333 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4>  LOC = AA25   | IOSTANDARD = LVCMOS33;
1334 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5>  LOC = U19    | IOSTANDARD = LVCMOS33;
1335 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6>  LOC = U18    | IOSTANDARD = LVCMOS33;
1336 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7>  LOC = Y22    | IOSTANDARD = LVCMOS33;
1337 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8>  LOC = Y23    | IOSTANDARD = LVCMOS33;
1338 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9>  LOC = U21    | IOSTANDARD = LVCMOS33;
1339 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC = T20    | IOSTANDARD = LVCMOS33;
1340 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC = Y24    | IOSTANDARD = LVCMOS33;
1341 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC = Y25    | IOSTANDARD = LVCMOS33;
1342 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC = T18    | IOSTANDARD = LVCMOS33;
1343 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC = T17    | IOSTANDARD = LVCMOS33;
1344 
#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC = W23    | IOSTANDARD = LVCMOS33;
1345 
#Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin     LOC = V25    | IOSTANDARD = LVCMOS33;
1346 
#Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin     LOC = V22    | IOSTANDARD = LVCMOS33;
1347 
#Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin     LOC = V24    | IOSTANDARD = LVCMOS33;
1348 
#Net fpga_0_SysACE_CompactFlash_SysACE_RST_pin     LOC = V23    | IOSTANDARD = LVCMOS33;
1349 
 
1350 
# Steal some pins off J8 (System Ace header) for debug connections to ORSoC debug cable
1351 
 
1352 
 
1353 
NET uart0_srx_expheader_pad_i  LOC = AA25; # J8 Pin 25, "D04"
1354 
NET uart0_srx_expheader_pad_i TIG;
1355 
NET uart0_srx_expheader_pad_i PULLUP;
1356 
NET uart0_srx_expheader_pad_i IOSTANDARD = LVTTL;
1357 
 
1358 
NET uart0_stx_expheader_pad_o  LOC = U19; # J8 Pin 28, "D05"
1359 
NET uart0_stx_expheader_pad_o TIG;
1360 
NET uart0_stx_expheader_pad_o PULLUP;
1361 
NET uart0_stx_expheader_pad_o IOSTANDARD = LVTTL;
1362 
 
1363 
NET tdo_pad_o  LOC = AA23; # J8 Pin 21, "D0"
1364 
NET tdi_pad_i  LOC = V21 ; # J8 Pin 24, "D1"
1365 
NET tms_pad_i  LOC = U20 ; # J8 Pin 23, "D2"
1366 
NET tck_pad_i  LOC = AA24; # J8 Pin 26, "D3"
1367 
 
1368 
NET tdo_pad_o  TIG; NET tdo_pad_o  PULLUP; NET tdo_pad_o  IOSTANDARD = LVTTL;
1369 
NET tdi_pad_i  TIG; NET tdi_pad_i  PULLUP; NET tdi_pad_i  IOSTANDARD = LVTTL;
1370 
NET tms_pad_i  TIG; NET tms_pad_i  PULLUP; NET tms_pad_i  IOSTANDARD = LVTTL;
1371 
NET tck_pad_i  TIG; NET tck_pad_i  PULLUP; NET tck_pad_i  IOSTANDARD = LVTTL;
1372 
# Overide the following mapping error:
1373 
# ERROR:Place:645 - A clock IOB clock component is not placed at an optimal clock
1374 
# IOB site.
1375 
NET "tck_pad_i" CLOCK_DEDICATED_ROUTE = FALSE;
1376 
NET  tck_pad_i TNM_NET = tck_pad_i;
1377 
TIMESPEC TS_tck_pad_i = PERIOD tck_pad_i 40 ns;
1378 
 
1379 
 
1380 
# SPI
1381 
 
1382 
NET spi0_mosi_o  LOC = AB15  | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = FAST | TIG;
1383 
NET spi0_ss_o<0> LOC = AA7 | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = FAST | TIG;
1384 
NET spi0_miso_i  LOC = AF24 | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = FAST | TIG;
1385 
NET spi0_sck_o   LOC = AE24 | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = FAST | TIG;

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