OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [bench/] [verilog/] [include/] [ddr2_model_preload.v] - Blame information for rev 568

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 568 julius
// File intended to be included in the generate statement for each DDR2 part.
2
// The following loads a vmem file, "sram.vmem" by default, into the SDRAM.
3
 
4
// Wait until the DDR memory is initialised, and then magically
5
// load it
6
@(posedge dut.xilinx_s3adsp_ddr2.xilinx_s3adsp_ddr2_if.phy_init_done);
7
//$display("%t: Loading DDR2",$time);
8
 
9
$readmemh("sram.vmem", program_array);
10
/* Now dish it out to the DDR2 model's memory */
11
for(ram_ptr = 0 ; ram_ptr < 4096 ; ram_ptr = ram_ptr + 1)
12
  begin
13
 
14
     // Construct the burst line, with every second word from where we
15
     // started, and picking the correct half of the word with i%2
16
     program_word_ptr = ram_ptr *8;
17
 
18
     tmp_program_word = program_array[program_word_ptr+1];
19
     ddr2_ram_mem_line[15:0] = tmp_program_word[15 + (i*16):(i*16)];
20
 
21
     tmp_program_word = program_array[program_word_ptr];
22
     ddr2_ram_mem_line[31:16] = tmp_program_word[15 + (i*16):(i*16)];
23
 
24
     tmp_program_word = program_array[program_word_ptr+3];
25
     ddr2_ram_mem_line[47:32] = tmp_program_word[15 + (i*16):(i*16)];
26
 
27
     tmp_program_word = program_array[program_word_ptr+2];
28
     ddr2_ram_mem_line[63:48] = tmp_program_word[15 + (i*16):(i*16)];
29
 
30
     tmp_program_word = program_array[program_word_ptr+5];
31
     ddr2_ram_mem_line[79:64] = tmp_program_word[15 + (i*16):(i*16)];
32
 
33
     tmp_program_word = program_array[program_word_ptr+4];
34
     ddr2_ram_mem_line[95:80] = tmp_program_word[15 + (i*16):(i*16)];
35
 
36
     tmp_program_word = program_array[program_word_ptr+7];
37
     ddr2_ram_mem_line[111:96] = tmp_program_word[15 + (i*16):(i*16)];
38
 
39
     tmp_program_word = program_array[program_word_ptr+6];
40
     ddr2_ram_mem_line[127:112] = tmp_program_word[15 + (i*16):(i*16)];
41
 
42
     // Put this assembled line into the RAM using its memory writing TASK
43
     u_mem0.memory_write(2'b00,ram_ptr[19:7],
44
                         {ram_ptr[6:0],3'b000},ddr2_ram_mem_line);
45
 
46
     //$display("Writing 0x%h, ramline=%d",ddr2_ram_mem_line, ram_ptr);
47
 
48
  end // for (ram_ptr = 0 ; ram_ptr < ...
49
$display("(%t) * DDR2 RAM %1d preloaded",$time, i);
50
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.