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julius |
// File intended to be included in the generate statement for each DDR2 part.
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// The following loads a vmem file, "sram.vmem" by default, into the SDRAM.
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// Wait until the DDR memory is initialised, and then magically
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// load it
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@(posedge dut.xilinx_s3adsp_ddr2.xilinx_s3adsp_ddr2_if.phy_init_done);
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//$display("%t: Loading DDR2",$time);
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$readmemh("sram.vmem", program_array);
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/* Now dish it out to the DDR2 model's memory */
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for(ram_ptr = 0 ; ram_ptr < 4096 ; ram_ptr = ram_ptr + 1)
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begin
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// Construct the burst line, with every second word from where we
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// started, and picking the correct half of the word with i%2
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program_word_ptr = ram_ptr *8;
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tmp_program_word = program_array[program_word_ptr+1];
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ddr2_ram_mem_line[15:0] = tmp_program_word[15 + (i*16):(i*16)];
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tmp_program_word = program_array[program_word_ptr];
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ddr2_ram_mem_line[31:16] = tmp_program_word[15 + (i*16):(i*16)];
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tmp_program_word = program_array[program_word_ptr+3];
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ddr2_ram_mem_line[47:32] = tmp_program_word[15 + (i*16):(i*16)];
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tmp_program_word = program_array[program_word_ptr+2];
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ddr2_ram_mem_line[63:48] = tmp_program_word[15 + (i*16):(i*16)];
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tmp_program_word = program_array[program_word_ptr+5];
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ddr2_ram_mem_line[79:64] = tmp_program_word[15 + (i*16):(i*16)];
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tmp_program_word = program_array[program_word_ptr+4];
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ddr2_ram_mem_line[95:80] = tmp_program_word[15 + (i*16):(i*16)];
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tmp_program_word = program_array[program_word_ptr+7];
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ddr2_ram_mem_line[111:96] = tmp_program_word[15 + (i*16):(i*16)];
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tmp_program_word = program_array[program_word_ptr+6];
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ddr2_ram_mem_line[127:112] = tmp_program_word[15 + (i*16):(i*16)];
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// Put this assembled line into the RAM using its memory writing TASK
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u_mem0.memory_write(2'b00,ram_ptr[19:7],
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{ram_ptr[6:0],3'b000},ddr2_ram_mem_line);
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//$display("Writing 0x%h, ramline=%d",ddr2_ram_mem_line, ram_ptr);
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end // for (ram_ptr = 0 ; ram_ptr < ...
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$display("(%t) * DDR2 RAM %1d preloaded",$time, i);
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