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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [bench/] [verilog/] [orpsoc_testbench.v] - Blame information for rev 568

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//////////////////////////////////////////////////////////////////////
///                                                               //// 
/// ORPSoC Spartan 3A DSP 1800 board testbench                    ////
///                                                               ////
/// Instantiate ORPSoC, monitors, provide stimulus                ////
///                                                               ////
/// Julius Baxter, julius@opencores.org                           ////
///                                                               ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009,2010,2011 Authors and OPENCORES.ORG       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "orpsoc-defines.v"
`include "orpsoc-testbench-defines.v"
`include "test-defines.v"
`include "timescale.v"
// Xilinx simulation:
`include "glbl.v"
 
module orpsoc_testbench;
 
   // Clock and reset signal registers
   reg clk = 0;
   reg rst_n = 1; // Active LOW
 
   always
     #((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
 
   // Reset, ACTIVE LOW
   initial
     begin
        #1;
        repeat (32) @(negedge clk)
          rst_n <= 1;
        repeat (32) @(negedge clk)
          rst_n <= 0;
        repeat (32) @(negedge clk)
          rst_n <= 1;
     end
 
   // Include design parameters file
`include "orpsoc-params.v"
 
   // Pullup bus for I2C
   tri1 i2c_scl, i2c_sda;
 
`ifdef JTAG_DEBUG
   wire tdo_pad_o;
   wire tck_pad_i;
   wire tms_pad_i;
   wire tdi_pad_i;
`endif
`ifdef UART0
   wire uart0_stx_pad_o;
   wire uart0_srx_pad_i;
`endif
`ifdef GPIO0
   wire [gpio0_io_width-1:0] gpio0_io;
`endif
`ifdef SPI0
   wire                      spi0_mosi_o;
   wire                      spi0_miso_i;
   wire                      spi0_sck_o;
   wire                      spi0_hold_n_o;
   wire                      spi0_w_n_o;
   wire [spi0_ss_width-1:0]  spi0_ss_o;
`endif
`ifdef ETH0
   wire                      mtx_clk_o;
   wire [3:0]                 ethphy_mii_tx_d;
   wire                      ethphy_mii_tx_en;
   wire                      ethphy_mii_tx_err;
   wire                      mrx_clk_o;
   wire [3:0]                 mrxd_o;
   wire                      mrxdv_o;
   wire                      mrxerr_o;
   wire                      mcoll_o;
   wire                      mcrs_o;
   wire                      ethphy_rst_n;
   wire                      eth0_mdc_pad_o;
   wire                      eth0_md_pad_io;
`endif
`ifdef XILINX_DDR2
 `include "s3adsp_ddr2_parameters_0.v"
   localparam DEVICE_WIDTH = 16; // Memory device data width
   localparam REG_ENABLE   = `REGISTERED; // registered addr/ctrl
 
   localparam real           CLK_PERIOD_NS      = 7519.0 / 1000.0;
     // Delay for DQS signal during operation
   localparam real           TPROP_DQS          = 0.00;
   localparam real           TPROP_DQS_RD       = 0.05;
   localparam real           TPROP_PCB_CTRL     = 0.00;
   localparam real           TPROP_PCB_DATA     = 0.00;
   localparam real           TPROP_PCB_DATA_RD  = 0.00;
 
   wire [`DATA_WIDTH-1:0]    ddr2_dq_sdram;
   wire [`DATA_STROBE_WIDTH-1:0] ddr2_dqs_sdram;
 
   // ddr2_dqs_n signal will be driven only in case of differential dqs is enabled.
   wire [`DATA_STROBE_WIDTH-1:0]  ddr2_dqs_n_sdram;
   wire [`DATA_MASK_WIDTH-1:0]    ddr2_dm_sdram;
   reg  [`DATA_MASK_WIDTH-1:0]    ddr2_dm_sdram_tmp;
   reg  [`CLK_WIDTH-1:0]          ddr2_clk_sdram;
   reg  [`CLK_WIDTH-1:0]          ddr2_clk_n_sdram;
   reg  [`ROW_ADDRESS-1:0]        ddr2_address_sdram;
   reg  [`BANK_ADDRESS-1:0]       ddr2_ba_sdram;
   reg                            ddr2_ras_n_sdram;
   reg                            ddr2_cas_n_sdram;
   reg                            ddr2_we_n_sdram;
   reg                            ddr2_cs_n_sdram;
   reg                            ddr2_cke_sdram;
   reg                            ddr2_odt_sdram;
 
 
   wire [`DATA_WIDTH-1:0]         ddr2_dq_fpga;
   wire [`DATA_STROBE_WIDTH-1:0]  ddr2_dqs_fpga;
 
   // ddr2_dqs_n signal will be driven only in case of differential dqs is enabled.
   wire [`DATA_STROBE_WIDTH-1:0]  ddr2_dqs_n_fpga;
   wire [`DATA_MASK_WIDTH-1:0]    ddr2_dm_fpga;
   wire [`CLK_WIDTH-1:0]          ddr2_clk_fpga;
   wire [`CLK_WIDTH-1:0]          ddr2_clk_n_fpga;
   wire [`ROW_ADDRESS-1:0]        ddr2_address_fpga;
   wire [`BANK_ADDRESS-1:0]       ddr2_ba_fpga;
   wire                           ddr2_ras_n_fpga;
   wire                           ddr2_cas_n_fpga;
   wire                           ddr2_we_n_fpga;
   wire                           ddr2_cs_n_fpga;
   wire                           ddr2_cke_fpga;
   wire                           ddr2_odt_fpga;
 
   wire                           ddr2_rst_dqs_div_loop;
 
`endif
 
   orpsoc_top dut
     (
`ifdef JTAG_DEBUG
      .tms_pad_i                        (tms_pad_i),
      .tck_pad_i                        (tck_pad_i),
      .tdi_pad_i                        (tdi_pad_i),
      .tdo_pad_o                        (tdo_pad_o),
`endif
`ifdef XILINX_DDR2
      .ddr2_ras_n                       (ddr2_ras_n_fpga),
      .ddr2_cas_n                       (ddr2_cas_n_fpga),
      .ddr2_we_n                        (ddr2_we_n_fpga),
      .ddr2_cs_n                        (ddr2_cs_n_fpga),
      .ddr2_cke                         (ddr2_cke_fpga),
      .ddr2_odt                         (ddr2_odt_fpga),
      .ddr2_dm                          (ddr2_dm_fpga),
      .ddr2_dq                          (ddr2_dq_fpga),
      .ddr2_dqs                         (ddr2_dqs_fpga),
      .ddr2_dqs_n                       (ddr2_dqs_n_fpga),
      .ddr2_ck                          (ddr2_clk_fpga),
      .ddr2_ck_n                        (ddr2_clk_n_fpga),
      .ddr2_ba                          (ddr2_ba_fpga),
      .ddr2_a                           (ddr2_address_fpga),
      .ddr2_rst_dqs_div_in              (ddr2_rst_dqs_div_loop),
      .ddr2_rst_dqs_div_out             (ddr2_rst_dqs_div_loop),
`endif
 
`ifdef UART0
      .uart0_stx_pad_o                  (uart0_stx_pad_o),
      .uart0_srx_pad_i                  (uart0_srx_pad_i),
      .uart0_stx_expheader_pad_o        (uart0_stx_pad_o),
      .uart0_srx_expheader_pad_i        (uart0_srx_pad_i),
`endif
`ifdef SPI0
       .spi0_sck_o                      (spi0_sck_o),
       .spi0_miso_i                     (spi0_miso_i),
      .spi0_mosi_o                      (spi0_mosi_o),
      .spi0_ss_o                        (spi0_ss_o),
`endif
`ifdef I2C0
      .i2c0_sda_io                      (i2c_sda),
      .i2c0_scl_io                      (i2c_scl),
`endif
`ifdef GPIO0
      .gpio0_io                         (gpio0_io),
`endif
`ifdef ETH0
      .eth0_tx_clk                      (mtx_clk_o),
      .eth0_tx_data                     (ethphy_mii_tx_d),
      .eth0_tx_en                       (ethphy_mii_tx_en),
      .eth0_tx_er                       (ethphy_mii_tx_err),
      .eth0_rx_clk                      (mrx_clk_o),
      .eth0_rx_data                     (mrxd_o),
      .eth0_dv                          (mrxdv_o),
      .eth0_rx_er                       (mrxerr_o),
      .eth0_col                         (mcoll_o),
      .eth0_crs                         (mcrs_o),
      .eth0_rst_n_o                     (ethphy_rst_n),
      .eth0_mdc_pad_o                   (eth0_mdc_pad_o),
      .eth0_md_pad_io                   (eth0_md_pad_io),
`endif //  `ifdef ETH0
 
      .sys_clk_i                        (clk),
 
      .rst_n_pad_i                      (rst_n)
      );
 
   //
   // Instantiate OR1200 monitor
   //
   or1200_monitor monitor();
 
`ifndef SIM_QUIET
 `define CPU_ic_top or1200_ic_top
 `define CPU_dc_top or1200_dc_top
   wire                      ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;
   always @(posedge ic_en)
     $display("Or1200 IC enabled at %t", $time);
 
   wire                      dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;
   always @(posedge dc_en)
     $display("Or1200 DC enabled at %t", $time);
`endif
 
 
`ifdef JTAG_DEBUG
 `ifdef VPI_DEBUG
   // Debugging interface
   vpi_debug_module vpi_dbg
     (
      .tms(tms_pad_i),
      .tck(tck_pad_i),
      .tdi(tdi_pad_i),
      .tdo(tdo_pad_o)
      );
 `else
   // If no VPI debugging, tie off JTAG inputs
   assign tdi_pad_i = 1;
   assign tck_pad_i = 0;
   assign tms_pad_i = 1;
 `endif // !`ifdef VPI_DEBUG_ENABLE
`endif //  `ifdef JTAG_DEBUG
 
`ifdef SPI0
   // SPI flash memory - M25P16 compatible SPI protocol
   AT26DFxxx
     #(.MEMSIZE(2048*1024)) // 2MB flash on ML501
     spi0_flash
     (// Outputs
      .SO                                       (spi0_miso_i),
      // Inputs
      .CSB                                      (spi0_ss_o),
      .SCK                                      (spi0_sck_o),
      .SI                                       (spi0_mosi_o),
      .WPB                                      (1'b1)
      );
 
 
`endif //  `ifdef SPI0
 
`ifdef ETH0
 
   /* TX/RXes packets and checks them, enabled when ethernet MAC is */
// Disabled for now - Julius `include "eth_stim.v"
 
   eth_phy eth_phy0
     (
      // Outputs
      .mtx_clk_o                        (mtx_clk_o),
      .mrx_clk_o                        (mrx_clk_o),
      .mrxd_o                           (mrxd_o[3:0]),
      .mrxdv_o                          (mrxdv_o),
      .mrxerr_o                         (mrxerr_o),
      .mcoll_o                          (mcoll_o),
      .mcrs_o                           (mcrs_o),
      .link_o                           (),
      .speed_o                          (),
      .duplex_o                         (),
      .smii_clk_i                       (1'b0),
      .smii_sync_i                      (1'b0),
      .smii_rx_o                        (),
      // Inouts
      .md_io                            (eth0_md_pad_io),
      // Inputs
 `ifndef ETH0_PHY_RST
      // If no reset out from the design, hook up to the board's active low rst
      .m_rst_n_i                        (rst_n),
 `else
      .m_rst_n_i                        (ethphy_rst_n),
 `endif
      .mtxd_i                           (ethphy_mii_tx_d[3:0]),
      .mtxen_i                          (ethphy_mii_tx_en),
      .mtxerr_i                         (ethphy_mii_tx_err),
      .mdc_i                            (eth0_mdc_pad_o));
 
`endif //  `ifdef ETH0
 
`ifdef XILINX_DDR2
 
   always @( * ) begin
      ddr2_clk_sdram         <=  #(TPROP_PCB_CTRL) ddr2_clk_fpga;
      ddr2_clk_n_sdram       <=  #(TPROP_PCB_CTRL) ddr2_clk_n_fpga;
      ddr2_address_sdram     <=  #(TPROP_PCB_CTRL) ddr2_address_fpga;
      ddr2_ba_sdram          <=  #(TPROP_PCB_CTRL) ddr2_ba_fpga;
      ddr2_ras_n_sdram       <=  #(TPROP_PCB_CTRL) ddr2_ras_n_fpga;
      ddr2_cas_n_sdram       <=  #(TPROP_PCB_CTRL) ddr2_cas_n_fpga;
      ddr2_we_n_sdram        <=  #(TPROP_PCB_CTRL) ddr2_we_n_fpga;
      ddr2_cs_n_sdram        <=  #(TPROP_PCB_CTRL) ddr2_cs_n_fpga;
      ddr2_cke_sdram         <=  #(TPROP_PCB_CTRL) ddr2_cke_fpga;
      ddr2_odt_sdram         <=  #(TPROP_PCB_CTRL) ddr2_odt_fpga;
      ddr2_dm_sdram_tmp      <=  #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation
   end // always @ ( * )
 
   assign ddr2_dm_sdram = ddr2_dm_sdram_tmp;
 
 
   // Model delays on bi-directional BUS
   genvar dqwd;
   generate
      for (dqwd = 0;dqwd < `DATA_WIDTH;dqwd = dqwd+1) begin : dq_delay
         wiredelay #
                  (
                   .Delay_g     (TPROP_PCB_DATA),
                   .Delay_rd    (TPROP_PCB_DATA_RD)
                   )
         u_delay_dq
                  (
                   .A       (ddr2_dq_fpga[dqwd]),
                   .B       (ddr2_dq_sdram[dqwd]),
                   .reset       (rst_n)
                   );
      end
   endgenerate
   genvar dqswd;
   generate
      for (dqswd = 0;dqswd < `DATA_STROBE_WIDTH;dqswd = dqswd+1)
        begin : dqs_delay
         wiredelay #
                   (
                    .Delay_g     (TPROP_DQS),
                    .Delay_rd    (TPROP_DQS_RD)
                    )
         u_delay_dqs
                   (
                    .A       (ddr2_dqs_fpga[dqswd]),
                    .B       (ddr2_dqs_sdram[dqswd]),
                    .reset       (rst_n)
                    );
 
         wiredelay #
           (
            .Delay_g     (TPROP_DQS),
            .Delay_rd    (TPROP_DQS_RD)
            )
         u_delay_dqs_n
           (
            .A       (ddr2_dqs_n_fpga[dqswd]),
            .B       (ddr2_dqs_n_sdram[dqswd]),
            .reset       (rst_n)
            );
      end
   endgenerate
 
 
   assign ddr2_dm_sdram = ddr2_dm_sdram_tmp;
   //parameter NUM_PROGRAM_WORDS=1048576;
   parameter NUM_PROGRAM_WORDS=262144;
   integer ram_ptr, program_word_ptr, k;
   reg [31:0] tmp_program_word;
   reg [31:0] program_array [0:NUM_PROGRAM_WORDS-1]; // 256k words = 1MB
   reg [8*16-1:0] ddr2_ram_mem_line; //8*16-bits= 8 shorts (half-words)
   genvar         i,j;
 
   generate
      for(i = 0; i < `DATA_STROBE_WIDTH/2; i = i+1) begin : gen_bytes
 
         initial
           begin
 `ifdef PRELOAD_RAM
           `include "ddr2_model_preload.v"
 `endif
           end
 
         ddr2_model u_mem0
              (
               .ck       (ddr2_clk_sdram[i]),
               .ck_n     (ddr2_clk_n_sdram[i]),
               .cke     (ddr2_cke_sdram),
               .cs_n    (ddr2_cs_n_sdram),
               .ras_n   (ddr2_ras_n_sdram),
               .cas_n   (ddr2_cas_n_sdram),
               .we_n    (ddr2_we_n_sdram),
               .dm_rdqs (ddr2_dm_sdram[(2*(i+1))-1 : i*2]),
               .ba      (ddr2_ba_sdram),
               .addr    (ddr2_address_sdram),
               .dq      (ddr2_dq_sdram[(16*(i+1))-1 : i*16]),
               .dqs     (ddr2_dqs_sdram[(2*(i+1))-1 : i*2]),
               .dqs_n   (ddr2_dqs_n_sdram[(2*(i+1))-1 : i*2]),
               .rdqs_n  (),
               .odt     (ddr2_odt_sdram)
               );
         end // block: gen_bytes
   endgenerate
 
   task ddr2_read32;
      input [31:0] addr;
      output [31:0] word;
      begin
         // TODO fill this in
         word = 0;
      end
   endtask // ddr2_read32
 
`endif //  `ifdef XILINX_DDR2
 
`ifdef VCD
   reg vcd_go = 0;
   always @(vcd_go)
     begin
 
 `ifdef VCD_DELAY
        #(`VCD_DELAY);
 `endif
 
        // Delay by x insns
 `ifdef VCD_DELAY_INSNS
        #10; // Delay until after the value becomes valid
        while (monitor.insns < `VCD_DELAY_INSNS)
          @(posedge clk);
 `endif
 
 `ifdef SIMULATOR_MODELSIM
        // Modelsim can GZip VCDs on the fly if given in the suffix
  `define VCD_SUFFIX   ".vcd.gz"
 `else
  `define VCD_SUFFIX   ".vcd"
 `endif
 
 `ifndef SIM_QUIET
        $display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
 `endif
        $dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
 `ifndef VCD_DEPTH
  `define VCD_DEPTH 0
 `endif
        $dumpvars(`VCD_DEPTH);
 
     end
`endif //  `ifdef VCD
 
   initial
     begin
`ifndef SIM_QUIET
        $display("\n* Starting simulation of design RTL.\n* Test: %s\n",
                 `TEST_NAME_STRING );
`endif
 
`ifdef VCD
        vcd_go = 1;
`endif
 
     end // initial begin
 
`ifdef END_TIME
   initial begin
      #(`END_TIME);
 `ifndef SIM_QUIET
      $display("* Finish simulation due to END_TIME being set at %t", $time);
 `endif
      $finish;
   end
`endif
 
`ifdef END_INSNS
   initial begin
      #10
        while (monitor.insns < `END_INSNS)
          @(posedge clk);
 `ifndef SIM_QUIET
      $display("* Finish simulation due to END_INSNS count (%d) reached at %t",
               `END_INSNS, $time);
 `endif
      $finish;
   end
`endif
 
`ifdef UART0
   //   
   // UART0 decoder
   //   
   uart_decoder
     #(
        .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
        )
   uart0_decoder
     (
      .clk(clk),
      .uart_tx(uart0_stx_pad_o)
      );
 
   // Loopback UART lines
   assign uart0_srx_pad_i = uart0_stx_pad_o;
 
`endif //  `ifdef UART0
 
endmodule // orpsoc_testbench
 
// Local Variables:
// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")
// verilog-library-files:()
// verilog-library-extensions:(".v" ".h")
// End:
 

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [bench/] [verilog/] [orpsoc_testbench.v] - Blame information for rev 568

Line No.	Rev	Author	Line
1	568	julius	`//////////////////////////////////////////////////////////////////////`
2			`/// ////`
3			`/// ORPSoC Spartan 3A DSP 1800 board testbench ////`
4			`/// ////`
5			`/// Instantiate ORPSoC, monitors, provide stimulus ////`
6			`/// ////`
7			`/// Julius Baxter, julius@opencores.org ////`
8			`/// ////`
9			`//////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2009,2010,2011 Authors and OPENCORES.ORG ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer. ////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation; ////`
21			`//// either version 2.1 of the License, or (at your option) any ////`
22			`//// later version. ////`
23			`//// ////`
24			`//// This source is distributed in the hope that it will be ////`
25			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
26			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
27			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
28			`//// details. ////`
29			`//// ////`
30			`//// You should have received a copy of the GNU Lesser General ////`
31			`//// Public License along with this source; if not, download it ////`
32			`//// from http://www.opencores.org/lgpl.shtml ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35
36			`include "orpsoc-defines.v"
37			`include "orpsoc-testbench-defines.v"
38			`include "test-defines.v"
39			`include "timescale.v"
40			`// Xilinx simulation:`
41			`include "glbl.v"
42
43			`module orpsoc_testbench;`
44
45			`// Clock and reset signal registers`
46			`reg clk = 0;`
47			`reg rst_n = 1; // Active LOW`
48
49			`always`
50			#((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
51
52			`// Reset, ACTIVE LOW`
53			`initial`
54			`begin`
55			`#1;`
56			`repeat (32) @(negedge clk)`
57			`rst_n <= 1;`
58			`repeat (32) @(negedge clk)`
59			`rst_n <= 0;`
60			`repeat (32) @(negedge clk)`
61			`rst_n <= 1;`
62			`end`
63
64			`// Include design parameters file`
65			`include "orpsoc-params.v"
66
67			`// Pullup bus for I2C`
68			`tri1 i2c_scl, i2c_sda;`
69
70			`ifdef JTAG_DEBUG
71			`wire tdo_pad_o;`
72			`wire tck_pad_i;`
73			`wire tms_pad_i;`
74			`wire tdi_pad_i;`
75			`endif
76			`ifdef UART0
77			`wire uart0_stx_pad_o;`
78			`wire uart0_srx_pad_i;`
79			`endif
80			`ifdef GPIO0
81			`wire [gpio0_io_width-1:0] gpio0_io;`
82			`endif
83			`ifdef SPI0
84			`wire spi0_mosi_o;`
85			`wire spi0_miso_i;`
86			`wire spi0_sck_o;`
87			`wire spi0_hold_n_o;`
88			`wire spi0_w_n_o;`
89			`wire [spi0_ss_width-1:0] spi0_ss_o;`
90			`endif
91			`ifdef ETH0
92			`wire mtx_clk_o;`
93			`wire [3:0] ethphy_mii_tx_d;`
94			`wire ethphy_mii_tx_en;`
95			`wire ethphy_mii_tx_err;`
96			`wire mrx_clk_o;`
97			`wire [3:0] mrxd_o;`
98			`wire mrxdv_o;`
99			`wire mrxerr_o;`
100			`wire mcoll_o;`
101			`wire mcrs_o;`
102			`wire ethphy_rst_n;`
103			`wire eth0_mdc_pad_o;`
104			`wire eth0_md_pad_io;`
105			`endif
106			`ifdef XILINX_DDR2
107			`include "s3adsp_ddr2_parameters_0.v"
108			`localparam DEVICE_WIDTH = 16; // Memory device data width`
109			localparam REG_ENABLE = `REGISTERED; // registered addr/ctrl
110
111			`localparam real CLK_PERIOD_NS = 7519.0 / 1000.0;`
112			`// Delay for DQS signal during operation`
113			`localparam real TPROP_DQS = 0.00;`
114			`localparam real TPROP_DQS_RD = 0.05;`
115			`localparam real TPROP_PCB_CTRL = 0.00;`
116			`localparam real TPROP_PCB_DATA = 0.00;`
117			`localparam real TPROP_PCB_DATA_RD = 0.00;`
118
119			wire [`DATA_WIDTH-1:0] ddr2_dq_sdram;
120			wire [`DATA_STROBE_WIDTH-1:0] ddr2_dqs_sdram;
121
122			`// ddr2_dqs_n signal will be driven only in case of differential dqs is enabled.`
123			wire [`DATA_STROBE_WIDTH-1:0] ddr2_dqs_n_sdram;
124			wire [`DATA_MASK_WIDTH-1:0] ddr2_dm_sdram;
125			reg [`DATA_MASK_WIDTH-1:0] ddr2_dm_sdram_tmp;
126			reg [`CLK_WIDTH-1:0] ddr2_clk_sdram;
127			reg [`CLK_WIDTH-1:0] ddr2_clk_n_sdram;
128			reg [`ROW_ADDRESS-1:0] ddr2_address_sdram;
129			reg [`BANK_ADDRESS-1:0] ddr2_ba_sdram;
130			`reg ddr2_ras_n_sdram;`
131			`reg ddr2_cas_n_sdram;`
132			`reg ddr2_we_n_sdram;`
133			`reg ddr2_cs_n_sdram;`
134			`reg ddr2_cke_sdram;`
135			`reg ddr2_odt_sdram;`
136
137
138			wire [`DATA_WIDTH-1:0] ddr2_dq_fpga;
139			wire [`DATA_STROBE_WIDTH-1:0] ddr2_dqs_fpga;
140
141			`// ddr2_dqs_n signal will be driven only in case of differential dqs is enabled.`
142			wire [`DATA_STROBE_WIDTH-1:0] ddr2_dqs_n_fpga;
143			wire [`DATA_MASK_WIDTH-1:0] ddr2_dm_fpga;
144			wire [`CLK_WIDTH-1:0] ddr2_clk_fpga;
145			wire [`CLK_WIDTH-1:0] ddr2_clk_n_fpga;
146			wire [`ROW_ADDRESS-1:0] ddr2_address_fpga;
147			wire [`BANK_ADDRESS-1:0] ddr2_ba_fpga;
148			`wire ddr2_ras_n_fpga;`
149			`wire ddr2_cas_n_fpga;`
150			`wire ddr2_we_n_fpga;`
151			`wire ddr2_cs_n_fpga;`
152			`wire ddr2_cke_fpga;`
153			`wire ddr2_odt_fpga;`
154
155			`wire ddr2_rst_dqs_div_loop;`
156
157			`endif
158
159			`orpsoc_top dut`
160			`(`
161			`ifdef JTAG_DEBUG
162			`.tms_pad_i (tms_pad_i),`
163			`.tck_pad_i (tck_pad_i),`
164			`.tdi_pad_i (tdi_pad_i),`
165			`.tdo_pad_o (tdo_pad_o),`
166			`endif
167			`ifdef XILINX_DDR2
168			`.ddr2_ras_n (ddr2_ras_n_fpga),`
169			`.ddr2_cas_n (ddr2_cas_n_fpga),`
170			`.ddr2_we_n (ddr2_we_n_fpga),`
171			`.ddr2_cs_n (ddr2_cs_n_fpga),`
172			`.ddr2_cke (ddr2_cke_fpga),`
173			`.ddr2_odt (ddr2_odt_fpga),`
174			`.ddr2_dm (ddr2_dm_fpga),`
175			`.ddr2_dq (ddr2_dq_fpga),`
176			`.ddr2_dqs (ddr2_dqs_fpga),`
177			`.ddr2_dqs_n (ddr2_dqs_n_fpga),`
178			`.ddr2_ck (ddr2_clk_fpga),`
179			`.ddr2_ck_n (ddr2_clk_n_fpga),`
180			`.ddr2_ba (ddr2_ba_fpga),`
181			`.ddr2_a (ddr2_address_fpga),`
182			`.ddr2_rst_dqs_div_in (ddr2_rst_dqs_div_loop),`
183			`.ddr2_rst_dqs_div_out (ddr2_rst_dqs_div_loop),`
184			`endif
185
186			`ifdef UART0
187			`.uart0_stx_pad_o (uart0_stx_pad_o),`
188			`.uart0_srx_pad_i (uart0_srx_pad_i),`
189			`.uart0_stx_expheader_pad_o (uart0_stx_pad_o),`
190			`.uart0_srx_expheader_pad_i (uart0_srx_pad_i),`
191			`endif
192			`ifdef SPI0
193			`.spi0_sck_o (spi0_sck_o),`
194			`.spi0_miso_i (spi0_miso_i),`
195			`.spi0_mosi_o (spi0_mosi_o),`
196			`.spi0_ss_o (spi0_ss_o),`
197			`endif
198			`ifdef I2C0
199			`.i2c0_sda_io (i2c_sda),`
200			`.i2c0_scl_io (i2c_scl),`
201			`endif
202			`ifdef GPIO0
203			`.gpio0_io (gpio0_io),`
204			`endif
205			`ifdef ETH0
206			`.eth0_tx_clk (mtx_clk_o),`
207			`.eth0_tx_data (ethphy_mii_tx_d),`
208			`.eth0_tx_en (ethphy_mii_tx_en),`
209			`.eth0_tx_er (ethphy_mii_tx_err),`
210			`.eth0_rx_clk (mrx_clk_o),`
211			`.eth0_rx_data (mrxd_o),`
212			`.eth0_dv (mrxdv_o),`
213			`.eth0_rx_er (mrxerr_o),`
214			`.eth0_col (mcoll_o),`
215			`.eth0_crs (mcrs_o),`
216			`.eth0_rst_n_o (ethphy_rst_n),`
217			`.eth0_mdc_pad_o (eth0_mdc_pad_o),`
218			`.eth0_md_pad_io (eth0_md_pad_io),`
219			`endif // `ifdef ETH0
220
221			`.sys_clk_i (clk),`
222
223			`.rst_n_pad_i (rst_n)`
224			`);`
225
226			`//`
227			`// Instantiate OR1200 monitor`
228			`//`
229			`or1200_monitor monitor();`
230
231			`ifndef SIM_QUIET
232			`define CPU_ic_top or1200_ic_top
233			`define CPU_dc_top or1200_dc_top
234			`wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;`
235			`always @(posedge ic_en)`
236			`$display("Or1200 IC enabled at %t", $time);`
237
238			`wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;`
239			`always @(posedge dc_en)`
240			`$display("Or1200 DC enabled at %t", $time);`
241			`endif
242
243
244			`ifdef JTAG_DEBUG
245			`ifdef VPI_DEBUG
246			`// Debugging interface`
247			`vpi_debug_module vpi_dbg`
248			`(`
249			`.tms(tms_pad_i),`
250			`.tck(tck_pad_i),`
251			`.tdi(tdi_pad_i),`
252			`.tdo(tdo_pad_o)`
253			`);`
254			`else
255			`// If no VPI debugging, tie off JTAG inputs`
256			`assign tdi_pad_i = 1;`
257			`assign tck_pad_i = 0;`
258			`assign tms_pad_i = 1;`
259			`endif // !`ifdef VPI_DEBUG_ENABLE
260			`endif // `ifdef JTAG_DEBUG
261
262			`ifdef SPI0
263			`// SPI flash memory - M25P16 compatible SPI protocol`
264			`AT26DFxxx`
265			`#(.MEMSIZE(2048*1024)) // 2MB flash on ML501`
266			`spi0_flash`
267			`(// Outputs`
268			`.SO (spi0_miso_i),`
269			`// Inputs`
270			`.CSB (spi0_ss_o),`
271			`.SCK (spi0_sck_o),`
272			`.SI (spi0_mosi_o),`
273			`.WPB (1'b1)`
274			`);`
275
276
277			`endif // `ifdef SPI0
278
279			`ifdef ETH0
280
281			`/* TX/RXes packets and checks them, enabled when ethernet MAC is */`
282			// Disabled for now - Julius `include "eth_stim.v"
283
284			`eth_phy eth_phy0`
285			`(`
286			`// Outputs`
287			`.mtx_clk_o (mtx_clk_o),`
288			`.mrx_clk_o (mrx_clk_o),`
289			`.mrxd_o (mrxd_o[3:0]),`
290			`.mrxdv_o (mrxdv_o),`
291			`.mrxerr_o (mrxerr_o),`
292			`.mcoll_o (mcoll_o),`
293			`.mcrs_o (mcrs_o),`
294			`.link_o (),`
295			`.speed_o (),`
296			`.duplex_o (),`
297			`.smii_clk_i (1'b0),`
298			`.smii_sync_i (1'b0),`
299			`.smii_rx_o (),`
300			`// Inouts`
301			`.md_io (eth0_md_pad_io),`
302			`// Inputs`
303			`ifndef ETH0_PHY_RST
304			`// If no reset out from the design, hook up to the board's active low rst`
305			`.m_rst_n_i (rst_n),`
306			`else
307			`.m_rst_n_i (ethphy_rst_n),`
308			`endif
309			`.mtxd_i (ethphy_mii_tx_d[3:0]),`
310			`.mtxen_i (ethphy_mii_tx_en),`
311			`.mtxerr_i (ethphy_mii_tx_err),`
312			`.mdc_i (eth0_mdc_pad_o));`
313
314			`endif // `ifdef ETH0
315
316			`ifdef XILINX_DDR2
317
318			`always @( * ) begin`
319			`ddr2_clk_sdram <= #(TPROP_PCB_CTRL) ddr2_clk_fpga;`
320			`ddr2_clk_n_sdram <= #(TPROP_PCB_CTRL) ddr2_clk_n_fpga;`
321			`ddr2_address_sdram <= #(TPROP_PCB_CTRL) ddr2_address_fpga;`
322			`ddr2_ba_sdram <= #(TPROP_PCB_CTRL) ddr2_ba_fpga;`
323			`ddr2_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ras_n_fpga;`
324			`ddr2_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cas_n_fpga;`
325			`ddr2_we_n_sdram <= #(TPROP_PCB_CTRL) ddr2_we_n_fpga;`
326			`ddr2_cs_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cs_n_fpga;`
327			`ddr2_cke_sdram <= #(TPROP_PCB_CTRL) ddr2_cke_fpga;`
328			`ddr2_odt_sdram <= #(TPROP_PCB_CTRL) ddr2_odt_fpga;`
329			`ddr2_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation`
330			`end // always @ ( * )`
331
332			`assign ddr2_dm_sdram = ddr2_dm_sdram_tmp;`
333
334
335			`// Model delays on bi-directional BUS`
336			`genvar dqwd;`
337			`generate`
338			for (dqwd = 0;dqwd < `DATA_WIDTH;dqwd = dqwd+1) begin : dq_delay
339			`wiredelay #`
340			`(`
341			`.Delay_g (TPROP_PCB_DATA),`
342			`.Delay_rd (TPROP_PCB_DATA_RD)`
343			`)`
344			`u_delay_dq`
345			`(`
346			`.A (ddr2_dq_fpga[dqwd]),`
347			`.B (ddr2_dq_sdram[dqwd]),`
348			`.reset (rst_n)`
349			`);`
350			`end`
351			`endgenerate`
352			`genvar dqswd;`
353			`generate`
354			for (dqswd = 0;dqswd < `DATA_STROBE_WIDTH;dqswd = dqswd+1)
355			`begin : dqs_delay`
356			`wiredelay #`
357			`(`
358			`.Delay_g (TPROP_DQS),`
359			`.Delay_rd (TPROP_DQS_RD)`
360			`)`
361			`u_delay_dqs`
362			`(`
363			`.A (ddr2_dqs_fpga[dqswd]),`
364			`.B (ddr2_dqs_sdram[dqswd]),`
365			`.reset (rst_n)`
366			`);`
367
368			`wiredelay #`
369			`(`
370			`.Delay_g (TPROP_DQS),`
371			`.Delay_rd (TPROP_DQS_RD)`
372			`)`
373			`u_delay_dqs_n`
374			`(`
375			`.A (ddr2_dqs_n_fpga[dqswd]),`
376			`.B (ddr2_dqs_n_sdram[dqswd]),`
377			`.reset (rst_n)`
378			`);`
379			`end`
380			`endgenerate`
381
382
383			`assign ddr2_dm_sdram = ddr2_dm_sdram_tmp;`
384			`//parameter NUM_PROGRAM_WORDS=1048576;`
385			`parameter NUM_PROGRAM_WORDS=262144;`
386			`integer ram_ptr, program_word_ptr, k;`
387			`reg [31:0] tmp_program_word;`
388			`reg [31:0] program_array [0:NUM_PROGRAM_WORDS-1]; // 256k words = 1MB`
389			`reg [816-1:0] ddr2_ram_mem_line; //816-bits= 8 shorts (half-words)`
390			`genvar i,j;`
391
392			`generate`
393			for(i = 0; i < `DATA_STROBE_WIDTH/2; i = i+1) begin : gen_bytes
394
395			`initial`
396			`begin`
397			`ifdef PRELOAD_RAM
398			`include "ddr2_model_preload.v"
399			`endif
400			`end`
401
402			`ddr2_model u_mem0`
403			`(`
404			`.ck (ddr2_clk_sdram[i]),`
405			`.ck_n (ddr2_clk_n_sdram[i]),`
406			`.cke (ddr2_cke_sdram),`
407			`.cs_n (ddr2_cs_n_sdram),`
408			`.ras_n (ddr2_ras_n_sdram),`
409			`.cas_n (ddr2_cas_n_sdram),`
410			`.we_n (ddr2_we_n_sdram),`
411			`.dm_rdqs (ddr2_dm_sdram[(2(i+1))-1 : i2]),`
412			`.ba (ddr2_ba_sdram),`
413			`.addr (ddr2_address_sdram),`
414			`.dq (ddr2_dq_sdram[(16(i+1))-1 : i16]),`
415			`.dqs (ddr2_dqs_sdram[(2(i+1))-1 : i2]),`
416			`.dqs_n (ddr2_dqs_n_sdram[(2(i+1))-1 : i2]),`
417			`.rdqs_n (),`
418			`.odt (ddr2_odt_sdram)`
419			`);`
420			`end // block: gen_bytes`
421			`endgenerate`
422
423			`task ddr2_read32;`
424			`input [31:0] addr;`
425			`output [31:0] word;`
426			`begin`
427			`// TODO fill this in`
428			`word = 0;`
429			`end`
430			`endtask // ddr2_read32`
431
432			`endif // `ifdef XILINX_DDR2
433
434			`ifdef VCD
435			`reg vcd_go = 0;`
436			`always @(vcd_go)`
437			`begin`
438
439			`ifdef VCD_DELAY
440			#(`VCD_DELAY);
441			`endif
442
443			`// Delay by x insns`
444			`ifdef VCD_DELAY_INSNS
445			`#10; // Delay until after the value becomes valid`
446			while (monitor.insns < `VCD_DELAY_INSNS)
447			`@(posedge clk);`
448			`endif
449
450			`ifdef SIMULATOR_MODELSIM
451			`// Modelsim can GZip VCDs on the fly if given in the suffix`
452			`define VCD_SUFFIX ".vcd.gz"
453			`else
454			`define VCD_SUFFIX ".vcd"
455			`endif
456
457			`ifndef SIM_QUIET
458			$display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
459			`endif
460			$dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
461			`ifndef VCD_DEPTH
462			`define VCD_DEPTH 0
463			`endif
464			$dumpvars(`VCD_DEPTH);
465
466			`end`
467			`endif // `ifdef VCD
468
469			`initial`
470			`begin`
471			`ifndef SIM_QUIET
472			`$display("\n* Starting simulation of design RTL.\n* Test: %s\n",`
473			`TEST_NAME_STRING );
474			`endif
475
476			`ifdef VCD
477			`vcd_go = 1;`
478			`endif
479
480			`end // initial begin`
481
482			`ifdef END_TIME
483			`initial begin`
484			#(`END_TIME);
485			`ifndef SIM_QUIET
486			`$display("* Finish simulation due to END_TIME being set at %t", $time);`
487			`endif
488			`$finish;`
489			`end`
490			`endif
491
492			`ifdef END_INSNS
493			`initial begin`
494			`#10`
495			while (monitor.insns < `END_INSNS)
496			`@(posedge clk);`
497			`ifndef SIM_QUIET
498			`$display("* Finish simulation due to END_INSNS count (%d) reached at %t",`
499			`END_INSNS, $time);
500			`endif
501			`$finish;`
502			`end`
503			`endif
504
505			`ifdef UART0
506			`//`
507			`// UART0 decoder`
508			`//`
509			`uart_decoder`
510			`#(`
511			`.uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS`
512			`)`
513			`uart0_decoder`
514			`(`
515			`.clk(clk),`
516			`.uart_tx(uart0_stx_pad_o)`
517			`);`
518
519			`// Loopback UART lines`
520			`assign uart0_srx_pad_i = uart0_stx_pad_o;`
521
522			`endif // `ifdef UART0
523
524			`endmodule // orpsoc_testbench`
525
526			`// Local Variables:`
527			`// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")`
528			`// verilog-library-files:()`
529			`// verilog-library-extensions:(".v" ".h")`
530			`// End:`
531