URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [rtl/] [verilog/] [include/] [orpsoc-defines.v] - Blame information for rev 592

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
//// orpsoc-defines                                               ////
////                                                              ////
//// Top level ORPSoC defines file                                ////
////                                                              ////
//// Included in toplevel and testbench                           ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 `define XILINX
 `define XILINX_PLL
 `define FPGA_BOARD_XILINX_S3ADSP1800
 `define IOCONFIG_XILINX_S3ADSP1800
 `define BOARD_CLOCK_PERIOD 8000 // 125 MHz
 
 `define JTAG_DEBUG
// `define RAM_WB
 `define XILINX_DDR2
 `define UART0
 `define GPIO0
 `define SPI0
// `define I2C0
 `define ETH0
 `define ETH0_PHY_RST
 
// end of included module defines - keep this comment line here, scripts depend on it!!
 
 
//
// Arbiter defines
//
 
// Uncomment to register things through arbiter (hopefully quicker design)
// Instruction bus arbiter
//`define ARBITER_IBUS_REGISTERING
`define ARBITER_IBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles
// This has to be kind of long, as DDR2 initialisation can take a little while
// and after reset, and if this is too short we'll always get bus error.
`ifdef XILINX_DDR2
 `define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 20
`else
 `define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 6
`endif
 
// Data bus arbiter
 
//`define ARBITER_DBUS_REGISTERING
`define ARBITER_DBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`ifdef XILINX_DDR2
 `define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 20
`else
 `define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 6
`endif
 
// Byte bus (peripheral bus) arbiter
// Don't really need the watchdog here - the databus will pick it up
//`define ARBITER_BYTEBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`define ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH 9
 

Line No.	Rev	Author	Line
1	568	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// orpsoc-defines ////`
4			`//// ////`
5			`//// Top level ORPSoC defines file ////`
6			`//// ////`
7			`//// Included in toplevel and testbench ////`
8			`//// ////`
9			`//////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer. ////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation; ////`
21			`//// either version 2.1 of the License, or (at your option) any ////`
22			`//// later version. ////`
23			`//// ////`
24			`//// This source is distributed in the hope that it will be ////`
25			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
26			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
27			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
28			`//// details. ////`
29			`//// ////`
30			`//// You should have received a copy of the GNU Lesser General ////`
31			`//// Public License along with this source; if not, download it ////`
32			`//// from http://www.opencores.org/lgpl.shtml ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35
36			`define XILINX
37			`define XILINX_PLL
38			`define FPGA_BOARD_XILINX_S3ADSP1800
39			`define IOCONFIG_XILINX_S3ADSP1800
40			`define BOARD_CLOCK_PERIOD 8000 // 125 MHz
41
42			`define JTAG_DEBUG
43			// `define RAM_WB
44			`define XILINX_DDR2
45			`define UART0
46			`define GPIO0
47			`define SPI0
48			// `define I2C0
49			`define ETH0
50			`define ETH0_PHY_RST
51
52			`// end of included module defines - keep this comment line here, scripts depend on it!!`
53
54
55			`//`
56			`// Arbiter defines`
57			`//`
58
59			`// Uncomment to register things through arbiter (hopefully quicker design)`
60			`// Instruction bus arbiter`
61			//`define ARBITER_IBUS_REGISTERING
62			`define ARBITER_IBUS_WATCHDOG
63			`// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles`
64			`// This has to be kind of long, as DDR2 initialisation can take a little while`
65			`// and after reset, and if this is too short we'll always get bus error.`
66			`ifdef XILINX_DDR2
67			`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 20
68			`else
69			`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 6
70			`endif
71
72			`// Data bus arbiter`
73
74			//`define ARBITER_DBUS_REGISTERING
75			`define ARBITER_DBUS_WATCHDOG
76			`// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles`
77			`ifdef XILINX_DDR2
78			`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 20
79			`else
80			`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 6
81			`endif
82
83			`// Byte bus (peripheral bus) arbiter`
84			`// Don't really need the watchdog here - the databus will pick it up`
85			//`define ARBITER_BYTEBUS_WATCHDOG
86			`// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles`
87			`define ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH 9
88

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [rtl/] [verilog/] [include/] [orpsoc-defines.v] - Blame information for rev 592