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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [rtl/] [verilog/] [xilinx_s3adsp_ddr2/] [s3adsp_ddr2.v] - Blame information for rev 568

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1 568 julius
//*****************************************************************************
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// DISCLAIMER OF LIABILITY
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//
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// This file contains proprietary and confidential information of
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// Xilinx, Inc. ("Xilinx"), that is distributed under a license
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// from Xilinx, and may be used, copied and/or disclosed only
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// pursuant to the terms of a valid license agreement with Xilinx.
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//
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// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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// does not warrant that functions included in the Materials will
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// meet the requirements of Licensee, or that the operation of the
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// Materials will be uninterrupted or error-free, or that defects
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// in the Materials will be corrected. Furthermore, Xilinx does
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// not warrant or make any representations regarding use, or the
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// results of the use, of the Materials in terms of correctness,
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// accuracy, reliability or otherwise.
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//
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// Xilinx products are not designed or intended to be fail-safe,
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// or for use in any application requiring fail-safe performance,
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// such as life-support or safety devices or systems, Class III
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// medical devices, nuclear facilities, applications related to
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// the deployment of airbags, or any other applications that could
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// lead to death, personal injury or severe property or
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// environmental damage (individually and collectively, "critical
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// applications"). Customer assumes the sole risk and liability
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// of any use of Xilinx products in critical applications,
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// subject only to applicable laws and regulations governing
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// limitations on product liability.
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//
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// Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
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// All rights reserved.
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//
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// This disclaimer and copyright notice must be retained as part
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// of this file at all times.
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//*****************************************************************************
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//   ____  ____
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//  /   /\/   /
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// /___/  \  /   Vendor             : Xilinx
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// \   \   \/    Version            : 3.6.1
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//  \   \        Application        : MIG
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//  /   /        Filename           : s3adsp_ddr2.v
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// /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:42 $
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// \   \  /  \   Date Created       : Mon May 2 2005
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//  \___\/\___\
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// Device       : Spartan-3/3A/3A-DSP
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// Design Name  : DDR2 SDRAM
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// Purpose      : This module has the instantiations main and infrastructure_top
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//                modules
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//*****************************************************************************
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`timescale 1ns/100ps
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(* X_CORE_INFO = "mig_v3_61_ddr2_sp3, Coregen 12.4" ,
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   CORE_GENERATION_INFO = "ddr2_sp3,mig_v3_61,{component_name=ddr2_sp3, data_width=32, memory_width=8, clk_width=2, bank_address=2, row_address=13, column_address=10, no_of_cs=1, cke_width=1, registered=0, data_mask=1, mask_enable=1, load_mode_register=13'b0010100110011, ext_load_mode_register=13'b0000000000000, language=Verilog, synthesis_tool=ISE, interface_type=DDR2_SDRAM, no_of_controllers=1}" *)
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module s3adsp_ddr2
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  (
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   inout  [31:0]   cntrl0_ddr2_dq,
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   output [12:0]   cntrl0_ddr2_a,
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   output [1:0]    cntrl0_ddr2_ba,
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   output          cntrl0_ddr2_cke,
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   output          cntrl0_ddr2_cs_n,
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   output          cntrl0_ddr2_ras_n,
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   output          cntrl0_ddr2_cas_n,
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   output          cntrl0_ddr2_we_n,
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   output          cntrl0_ddr2_odt,
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   output [3:0]    cntrl0_ddr2_dm,
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   input           cntrl0_rst_dqs_div_in,
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   output          cntrl0_rst_dqs_div_out,
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   input           sys_clk_in,
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   input           reset_in_n,
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   input           cntrl0_burst_done,
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   output          cntrl0_init_done,
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   output          cntrl0_ar_done,
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   output          cntrl0_user_data_valid,
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   output          cntrl0_auto_ref_req,
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   output          cntrl0_user_cmd_ack,
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   input  [2:0]    cntrl0_user_command_register,
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   output          cntrl0_clk_tb,
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   output          cntrl0_clk90_tb,
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   output          cntrl0_sys_rst_tb,
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   output          cntrl0_sys_rst90_tb,
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   output          cntrl0_sys_rst180_tb,
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   input  [7:0]    cntrl0_user_data_mask,
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   output [63:0]   cntrl0_user_output_data,
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   input  [63:0]   cntrl0_user_input_data,
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   input  [24:0]   cntrl0_user_input_address,
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   inout  [3:0]    cntrl0_ddr2_dqs,
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   inout  [3:0]    cntrl0_ddr2_dqs_n,
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   output [1:0]    cntrl0_ddr2_ck,
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   output [1:0]    cntrl0_ddr2_ck_n
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   );
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   wire       wait_200us;
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   wire       clk_0;
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   wire       clk90_0;
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   wire       sys_rst;
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   wire       sys_rst90;
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   wire       sys_rst180;
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   wire [4:0] delay_sel_val;
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 // debug signals declarations
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   wire [4:0] dbg_delay_sel;
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   wire [4:0] dbg_phase_cnt;
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   wire [5:0] dbg_cnt;
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   wire       dbg_trans_onedtct;
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   wire       dbg_trans_twodtct;
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   wire       dbg_enb_trans_two_dtct;
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   wire       dbg_rst_calib;
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// chipscope signals
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   wire [19:0] dbg_data;
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   wire [3:0]  dbg_trig;
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   wire [35:0] control0;
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   wire [35:0] control1;
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   wire [11:0] vio_out;
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   wire [4:0]  vio_out_dqs;
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   wire        vio_out_dqs_en;
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   wire [4:0]  vio_out_rst_dqs_div;
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   wire        vio_out_rst_dqs_div_en;
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  wire sys_clkb;
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  wire sys_clk;
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  assign sys_clkb = 1'b0;
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  assign sys_clk = 1'b0;
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s3adsp_ddr2_top_0 top_00
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  (
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     .ddr2_dq                   (cntrl0_ddr2_dq),
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     .ddr2_a                    (cntrl0_ddr2_a),
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     .ddr2_ba                   (cntrl0_ddr2_ba),
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     .ddr2_cke                  (cntrl0_ddr2_cke),
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     .ddr2_cs_n                 (cntrl0_ddr2_cs_n),
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     .ddr2_ras_n                (cntrl0_ddr2_ras_n),
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     .ddr2_cas_n                (cntrl0_ddr2_cas_n),
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     .ddr2_we_n                 (cntrl0_ddr2_we_n),
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     .ddr2_odt                  (cntrl0_ddr2_odt),
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     .ddr2_dm                   (cntrl0_ddr2_dm),
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     .rst_dqs_div_in            (cntrl0_rst_dqs_div_in),
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     .rst_dqs_div_out           (cntrl0_rst_dqs_div_out),
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     .burst_done                (cntrl0_burst_done),
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     .init_done                 (cntrl0_init_done),
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     .ar_done                   (cntrl0_ar_done),
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     .user_data_valid           (cntrl0_user_data_valid),
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     .auto_ref_req              (cntrl0_auto_ref_req),
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     .user_cmd_ack              (cntrl0_user_cmd_ack),
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     .user_command_register     (cntrl0_user_command_register),
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     .clk_tb                    (cntrl0_clk_tb),
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     .clk90_tb                  (cntrl0_clk90_tb),
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     .sys_rst_tb                (cntrl0_sys_rst_tb),
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     .sys_rst90_tb              (cntrl0_sys_rst90_tb),
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     .sys_rst180_tb             (cntrl0_sys_rst180_tb),
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     .user_data_mask            (cntrl0_user_data_mask),
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     .user_output_data          (cntrl0_user_output_data),
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     .user_input_data           (cntrl0_user_input_data),
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     .user_input_address        (cntrl0_user_input_address),
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     .ddr2_dqs                  (cntrl0_ddr2_dqs),
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     .ddr2_dqs_n                (cntrl0_ddr2_dqs_n),
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     .ddr2_ck                   (cntrl0_ddr2_ck),
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     .ddr2_ck_n                 (cntrl0_ddr2_ck_n),
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     .wait_200us                (wait_200us),
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     .clk_int                   (clk_0),
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     .clk90_int                 (clk90_0),
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     .sys_rst                   (sys_rst),
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     .sys_rst90                 (sys_rst90),
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     .sys_rst180                (sys_rst180),
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     .delay_sel_val             (delay_sel_val),
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    //Debug signals
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     .dbg_delay_sel            (dbg_delay_sel),
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     .dbg_rst_calib            (dbg_rst_calib),
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     .vio_out_dqs              (vio_out_dqs),
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     .vio_out_dqs_en           (vio_out_dqs_en),
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     .vio_out_rst_dqs_div      (vio_out_rst_dqs_div),
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     .vio_out_rst_dqs_div_en   (vio_out_rst_dqs_div_en)
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  );
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s3adsp_ddr2_infrastructure_top infrastructure_top0
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  (
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     .sys_clkb                  (sys_clkb),
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     .sys_clk                   (sys_clk),
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     .sys_clk_in                (sys_clk_in),
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     .reset_in_n                (reset_in_n),
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   .wait_200us_rout        (wait_200us),
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   .delay_sel_val1_val     (delay_sel_val),
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   .sys_rst_val            (sys_rst),
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   .sys_rst90_val          (sys_rst90),
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   .clk_int_val            (clk_0),
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   .clk90_int_val          (clk90_0),
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   .sys_rst180_val         (sys_rst180),
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   .dbg_phase_cnt          (dbg_phase_cnt),
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   .dbg_cnt                (dbg_cnt),
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   .dbg_trans_onedtct      (dbg_trans_onedtct),
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   .dbg_trans_twodtct      (dbg_trans_twodtct),
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   .dbg_enb_trans_two_dtct (dbg_enb_trans_two_dtct)
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   );
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endmodule
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