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// You must compile the wrapper file s3adsp_ddr2_cache.v when simulating

// the core, s3adsp_ddr2_cache. When compiling the wrapper file, be sure to

// reference the XilinxCoreLib Verilog simulation library. For detailed

// instructions, please refer to the "CORE Generator Help".

// The synthesis directives "translate_off/translate_on" specified below are

// supported by Xilinx, Mentor Graphics and Synplicity synthesis

// tools. Ensure they are correct for your synthesis tool(s).

`timescale 1ns/1ps

module s3adsp_ddr2_cache(

  clka,

  ena,

  wea,

  addra,

  dina,

  douta,

  clkb,

  enb,

  web,

  addrb,

  dinb,

  doutb

);

input clka;

input ena;

input [3 : 0] wea;

input [9 : 0] addra;

input [31 : 0] dina;

output [31 : 0] douta;

input clkb;

input enb;

input [7 : 0] web;

input [8 : 0] addrb;

input [63 : 0] dinb;

output [63 : 0] doutb;

// synthesis translate_off

  BLK_MEM_GEN_V6_1 #(

    .C_ADDRA_WIDTH(10),

    .C_ADDRB_WIDTH(9),

    .C_ALGORITHM(1),

    .C_AXI_ID_WIDTH(4),

    .C_AXI_SLAVE_TYPE(0),

    .C_AXI_TYPE(1),

    .C_BYTE_SIZE(8),

    .C_COMMON_CLK(0),

    .C_DEFAULT_DATA("0"),

    .C_DISABLE_WARN_BHV_COLL(1),

    .C_DISABLE_WARN_BHV_RANGE(0),

    .C_FAMILY("spartan3"),

    .C_HAS_AXI_ID(0),

    .C_HAS_ENA(1),

    .C_HAS_ENB(1),

    .C_HAS_INJECTERR(0),

    .C_HAS_MEM_OUTPUT_REGS_A(0),

    .C_HAS_MEM_OUTPUT_REGS_B(0),

    .C_HAS_MUX_OUTPUT_REGS_A(0),

    .C_HAS_MUX_OUTPUT_REGS_B(0),

    .C_HAS_REGCEA(0),

    .C_HAS_REGCEB(0),

    .C_HAS_RSTA(0),

    .C_HAS_RSTB(0),

    .C_HAS_SOFTECC_INPUT_REGS_A(0),

    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),

    .C_INIT_FILE_NAME("no_coe_file_loaded"),

    .C_INITA_VAL("0"),

    .C_INITB_VAL("0"),

    .C_INTERFACE_TYPE(0),

    .C_LOAD_INIT_FILE(0),

    .C_MEM_TYPE(2),

    .C_MUX_PIPELINE_STAGES(0),

    .C_PRIM_TYPE(1),

    .C_READ_DEPTH_A(1024),

    .C_READ_DEPTH_B(512),

    .C_READ_WIDTH_A(32),

    .C_READ_WIDTH_B(64),

    .C_RST_PRIORITY_A("CE"),

    .C_RST_PRIORITY_B("CE"),

    .C_RST_TYPE("SYNC"),

    .C_RSTRAM_A(0),

    .C_RSTRAM_B(0),

    .C_SIM_COLLISION_CHECK("NONE"),

    .C_USE_BYTE_WEA(1),

    .C_USE_BYTE_WEB(1),

    .C_USE_DEFAULT_DATA(0),

    .C_USE_ECC(0),

    .C_USE_SOFTECC(0),

    .C_WEA_WIDTH(4),

    .C_WEB_WIDTH(8),

    .C_WRITE_DEPTH_A(1024),

    .C_WRITE_DEPTH_B(512),

    .C_WRITE_MODE_A("WRITE_FIRST"),

    .C_WRITE_MODE_B("WRITE_FIRST"),

    .C_WRITE_WIDTH_A(32),

    .C_WRITE_WIDTH_B(64),

    .C_XDEVICEFAMILY("spartan3adsp")

  )

  inst (

    .CLKA(clka),

    .ENA(ena),

    .WEA(wea),

    .ADDRA(addra),

    .DINA(dina),

    .DOUTA(douta),

    .CLKB(clkb),

    .ENB(enb),

    .WEB(web),

    .ADDRB(addrb),

    .DINB(dinb),

    .DOUTB(doutb),

    .RSTA(),

    .REGCEA(),

    .RSTB(),

    .REGCEB(),

    .INJECTSBITERR(),

    .INJECTDBITERR(),

    .SBITERR(),

    .DBITERR(),

    .RDADDRECC(),

    .S_ACLK(),

    .S_ARESETN(),

    .S_AXI_AWID(),

    .S_AXI_AWADDR(),

    .S_AXI_AWLEN(),

    .S_AXI_AWSIZE(),

    .S_AXI_AWBURST(),

    .S_AXI_AWVALID(),

    .S_AXI_AWREADY(),

    .S_AXI_WDATA(),

    .S_AXI_WSTRB(),

    .S_AXI_WLAST(),

    .S_AXI_WVALID(),

    .S_AXI_WREADY(),

    .S_AXI_BID(),

    .S_AXI_BRESP(),

    .S_AXI_BVALID(),

    .S_AXI_BREADY(),

    .S_AXI_ARID(),

    .S_AXI_ARADDR(),

    .S_AXI_ARLEN(),

    .S_AXI_ARSIZE(),

    .S_AXI_ARBURST(),

    .S_AXI_ARVALID(),

    .S_AXI_ARREADY(),

    .S_AXI_RID(),

    .S_AXI_RDATA(),

    .S_AXI_RRESP(),

    .S_AXI_RLAST(),

    .S_AXI_RVALID(),

    .S_AXI_RREADY(),

    .S_AXI_INJECTSBITERR(),

    .S_AXI_INJECTDBITERR(),

    .S_AXI_SBITERR(),

    .S_AXI_DBITERR(),

    .S_AXI_RDADDRECC()

  );

// synthesis translate_on

endmodule