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//*****************************************************************************
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// DISCLAIMER OF LIABILITY
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//
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// This file contains proprietary and confidential information of
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// Xilinx, Inc. ("Xilinx"), that is distributed under a license
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// from Xilinx, and may be used, copied and/or disclosed only
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// pursuant to the terms of a valid license agreement with Xilinx.
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//
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// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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// does not warrant that functions included in the Materials will
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// meet the requirements of Licensee, or that the operation of the
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// Materials will be uninterrupted or error-free, or that defects
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// in the Materials will be corrected. Furthermore, Xilinx does
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// not warrant or make any representations regarding use, or the
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// results of the use, of the Materials in terms of correctness,
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// accuracy, reliability or otherwise.
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//
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// Xilinx products are not designed or intended to be fail-safe,
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// or for use in any application requiring fail-safe performance,
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// such as life-support or safety devices or systems, Class III
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// medical devices, nuclear facilities, applications related to
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// the deployment of airbags, or any other applications that could
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// lead to death, personal injury or severe property or
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// environmental damage (individually and collectively, "critical
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// applications"). Customer assumes the sole risk and liability
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// of any use of Xilinx products in critical applications,
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// subject only to applicable laws and regulations governing
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// limitations on product liability.
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//
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// Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
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// All rights reserved.
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//
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// This disclaimer and copyright notice must be retained as part
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// of this file at all times.
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 3.6.1
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// \ \ Application : MIG
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// / / Filename : s3adsp_ddr2_data_read_controller_0.v
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// /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:41 $
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// \ \ / \ Date Created : Mon May 2 2005
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// \___\/\___\
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// Device : Spartan-3/3A/3A-DSP
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// Design Name : DDR2 SDRAM
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// Purpose : This module has instantiations fifo_0_wr_en, fifo_1_wr_en,
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// dqs_delay and wr_gray_cntr.
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//*****************************************************************************
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`timescale 1ns/100ps
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`include "s3adsp_ddr2_parameters_0.v"
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module s3adsp_ddr2_data_read_controller_0
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(
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input clk,
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input reset,
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input rst_dqs_div_in,
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input [4:0] delay_sel,
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input [(`DATA_STROBE_WIDTH-1):0] dqs_int_delay_in,
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output [(`DATA_STROBE_WIDTH-1):0] fifo_0_wr_en_val,
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output [(`DATA_STROBE_WIDTH-1):0] fifo_1_wr_en_val,
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output [(4*`DATA_STROBE_WIDTH)-1:0] fifo_0_wr_addr_val,
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output [(4*`DATA_STROBE_WIDTH)-1:0] fifo_1_wr_addr_val,
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output [(`DATA_STROBE_WIDTH-1):0] dqs_delayed_col0_val,
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output [(`DATA_STROBE_WIDTH-1):0] dqs_delayed_col1_val,
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//debug_signals
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input [4:0] vio_out_dqs,
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input vio_out_dqs_en,
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input [4:0] vio_out_rst_dqs_div,
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input vio_out_rst_dqs_div_en
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);
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reg reset_r;
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wire rst_dqs_div;
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wire [(4*`DATA_STROBE_WIDTH)-1:0] fifo_0_wr_addr;
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wire [(4*`DATA_STROBE_WIDTH)-1:0] fifo_1_wr_addr;
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wire [(`DATA_STROBE_WIDTH-1):0] rst_dqs_delay_n;
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wire [(`DATA_STROBE_WIDTH-1):0] dqs_delayed_col0_n;
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wire [(`DATA_STROBE_WIDTH-1):0] dqs_delayed_col1_n;
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wire [(`DATA_STROBE_WIDTH-1):0] fifo_0_wr_en/* synthesis syn_keep=1 */;
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wire [(`DATA_STROBE_WIDTH-1):0] fifo_1_wr_en/* synthesis syn_keep=1 */;
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wire [4:0] delay_sel_rst_dqs_div;
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wire [4:0] delay_sel_dqs;
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(* BUFFER_TYPE = "none" *) wire [(`DATA_STROBE_WIDTH-1):0] dqs_delayed_col0;
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(* BUFFER_TYPE = "none" *) wire [(`DATA_STROBE_WIDTH-1):0] dqs_delayed_col1;
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assign fifo_0_wr_addr_val = fifo_0_wr_addr;
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assign fifo_1_wr_addr_val = fifo_1_wr_addr;
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assign fifo_0_wr_en_val = fifo_0_wr_en;
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assign fifo_1_wr_en_val = fifo_1_wr_en;
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assign dqs_delayed_col0_val = dqs_delayed_col0;
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assign dqs_delayed_col1_val = dqs_delayed_col1;
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assign dqs_delayed_col0_n = ~ dqs_delayed_col0;
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assign dqs_delayed_col1_n = ~ dqs_delayed_col1;
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always @(posedge clk)
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reset_r <= reset;
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generate
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if(`DEBUG_EN)
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assign delay_sel_rst_dqs_div = (vio_out_rst_dqs_div_en) ?
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vio_out_rst_dqs_div[4:0] :
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delay_sel;
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else
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assign delay_sel_rst_dqs_div = delay_sel;
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endgenerate
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// rst_dqs_div instantation.
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s3adsp_ddr2_dqs_delay rst_dqs_div_delayed
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(
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.clk_in(rst_dqs_div_in),
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.sel_in(delay_sel_rst_dqs_div),
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.clk_out(rst_dqs_div)
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);
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generate
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if(`DEBUG_EN)
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assign delay_sel_dqs = vio_out_dqs_en ? vio_out_dqs[4:0] : delay_sel;
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else
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assign delay_sel_dqs = delay_sel;
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endgenerate
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//DQS Internal Delay Circuit implemented in LUTs
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genvar dly_i;
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generate
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for(dly_i = 0; dly_i < `DATA_STROBE_WIDTH; dly_i = dly_i + 1)
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begin: gen_delay
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s3adsp_ddr2_dqs_delay dqs_delay_col0
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(
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.clk_in (dqs_int_delay_in[dly_i]),
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.sel_in (delay_sel_dqs),
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.clk_out (dqs_delayed_col0[dly_i])
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)/* synthesis syn_preserve=1 */;
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s3adsp_ddr2_dqs_delay dqs_delay_col1
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(
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.clk_in (dqs_int_delay_in[dly_i]),
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.sel_in (delay_sel_dqs),
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.clk_out (dqs_delayed_col1[dly_i])
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)/* synthesis syn_preserve=1 */;
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end
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endgenerate
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// FIFO write enables instances
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genvar wren_i;
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generate
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for(wren_i = 0; wren_i < `DATA_STROBE_WIDTH; wren_i = wren_i + 1)
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begin: gen_wr_en
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s3adsp_ddr2_fifo_0_wr_en_0 fifo_0_wr_en_inst
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(
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.clk (dqs_delayed_col1_n [wren_i]),
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.reset (reset_r),
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.din (rst_dqs_div),
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.rst_dqs_delay_n (rst_dqs_delay_n[wren_i]),
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.dout (fifo_0_wr_en[wren_i])
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);
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s3adsp_ddr2_fifo_1_wr_en_0 fifo_1_wr_en_inst
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(
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.clk (dqs_delayed_col0[wren_i]),
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.rst_dqs_delay_n (rst_dqs_delay_n[wren_i]),
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.reset (reset_r),
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.din (rst_dqs_div),
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.dout (fifo_1_wr_en[wren_i])
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);
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end
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endgenerate
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//FIFO write pointer instances
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genvar wr_addr_i;
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generate
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for(wr_addr_i = 0; wr_addr_i < `DATA_STROBE_WIDTH; wr_addr_i = wr_addr_i + 1)
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begin: gen_wr_addr
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s3adsp_ddr2_wr_gray_cntr fifo_0_wr_addr_inst
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(
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.clk (dqs_delayed_col1[wr_addr_i]),
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.reset (reset_r),
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.cnt_en (fifo_0_wr_en[wr_addr_i]),
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.wgc_gcnt (fifo_0_wr_addr[wr_addr_i*4+:4])
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);
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s3adsp_ddr2_wr_gray_cntr fifo_1_wr_addr_inst
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(
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.clk (dqs_delayed_col0_n[wr_addr_i]),
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.reset (reset_r),
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.cnt_en (fifo_1_wr_en[wr_addr_i]),
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.wgc_gcnt (fifo_1_wr_addr[wr_addr_i*4+:4])
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);
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end
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endgenerate
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endmodule
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