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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [rtl/] [verilog/] [xilinx_s3adsp_ddr2/] [s3adsp_ddr2_data_write_0.v] - Blame information for rev 568

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1 568 julius
//*****************************************************************************
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// DISCLAIMER OF LIABILITY
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//
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// This file contains proprietary and confidential information of
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// Xilinx, Inc. ("Xilinx"), that is distributed under a license
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// from Xilinx, and may be used, copied and/or disclosed only
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// pursuant to the terms of a valid license agreement with Xilinx.
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//
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// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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// does not warrant that functions included in the Materials will
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// meet the requirements of Licensee, or that the operation of the
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// Materials will be uninterrupted or error-free, or that defects
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// in the Materials will be corrected. Furthermore, Xilinx does
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// not warrant or make any representations regarding use, or the
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// results of the use, of the Materials in terms of correctness,
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// accuracy, reliability or otherwise.
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//
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// Xilinx products are not designed or intended to be fail-safe,
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// or for use in any application requiring fail-safe performance,
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// such as life-support or safety devices or systems, Class III
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// medical devices, nuclear facilities, applications related to
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// the deployment of airbags, or any other applications that could
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// lead to death, personal injury or severe property or
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// environmental damage (individually and collectively, "critical
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// applications"). Customer assumes the sole risk and liability
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// of any use of Xilinx products in critical applications,
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// subject only to applicable laws and regulations governing
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// limitations on product liability.
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//
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// Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
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// All rights reserved.
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//
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// This disclaimer and copyright notice must be retained as part
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// of this file at all times.
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//*****************************************************************************
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//   ____  ____
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//  /   /\/   /
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// /___/  \  /   Vendor             : Xilinx
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// \   \   \/    Version            : 3.6.1
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//  \   \        Application        : MIG
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//  /   /        Filename           : data_write.v
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// /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:41 $
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// \   \  /  \   Date Created       : Mon May 2 2005
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//  \___\/\___\
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// Device       : Spartan-3/3A/3A-DSP
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// Design Name  : DDR2 SDRAM
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// Purpose      : Data write operation performed through the pipelines in this
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//                module.
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//*****************************************************************************
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`timescale 1ns/100ps
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`include "s3adsp_ddr2_parameters_0.v"
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module  s3adsp_ddr2_data_write_0
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  (
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   input     [((`DATA_WIDTH*2)-1):0]  user_input_data,
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   input [((`DATA_MASK_WIDTH*2)-1):0] user_data_mask,
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   input                              clk90,
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   input                              write_enable,
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   output reg                         write_en_val,
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   output [((`DATA_WIDTH)-1):0]       write_data_falling,
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   output [((`DATA_WIDTH)-1):0]       write_data_rising,
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   output [((`DATA_MASK_WIDTH)-1):0]  data_mask_f,
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   output [((`DATA_MASK_WIDTH)-1):0]  data_mask_r
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   );
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   reg                                write_en_P1;
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   reg [((`DATA_WIDTH*2)-1):0]        write_data1;
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   reg [((`DATA_WIDTH*2)-1):0]        write_data2;
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   reg [((`DATA_WIDTH*2)-1):0]        write_data3;
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   reg [((`DATA_WIDTH*2)-1):0]        write_data4
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   /* synthesis syn_srlstyle="registers" */;
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   reg [((`DATA_MASK_WIDTH*2)-1):0]   write_data_m1;
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   reg [((`DATA_MASK_WIDTH*2)-1):0]   write_data_m2;
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   reg [((`DATA_MASK_WIDTH*2)-1):0]   write_data_m3;
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   reg [((`DATA_MASK_WIDTH*2)-1):0]   write_data_m4;
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   reg [(`DATA_WIDTH-1):0]            write_data90;
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   reg [(`DATA_WIDTH-1):0]            write_data90_1;
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   reg [(`DATA_WIDTH-1):0]            write_data90_2;
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   reg [(`DATA_WIDTH-1):0]            write_data270;
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   reg [(`DATA_WIDTH-1):0]            write_data270_1;
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   reg [(`DATA_WIDTH-1):0]            write_data270_2;
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   reg [(`DATA_MASK_WIDTH-1):0]       write_data_m90;
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   reg [(`DATA_MASK_WIDTH-1):0]       write_data_m90_1;
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   reg [(`DATA_MASK_WIDTH-1):0]       write_data_m90_2;
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   reg [((`DATA_MASK_WIDTH)-1):0]     write_data_m270;
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   reg [((`DATA_MASK_WIDTH)-1):0]     write_data_m270_1;
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   reg [((`DATA_MASK_WIDTH)-1):0]     write_data_m270_2;
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   wire [((`DATA_WIDTH*2)-1):0]       write_data0;
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   wire [((`DATA_MASK_WIDTH*2)-1):0]  write_data_m0;
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   assign write_data0   = user_input_data;
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   assign write_data_m0 = user_data_mask;
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   always@(posedge clk90) begin
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      write_data1 <= write_data0;
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      write_data2 <= write_data1;
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      write_data3 <= write_data2;
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      write_data4 <= write_data3;
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   end
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   always@(posedge clk90) begin
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      write_data_m1 <= write_data_m0;
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      write_data_m2 <= write_data_m1;
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      write_data_m3 <= write_data_m2;
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      write_data_m4 <= write_data_m3;
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   end
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   always@(posedge clk90) begin
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      write_data90   <= write_data4[`DATA_WIDTH-1 : 0];
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      write_data_m90       <= write_data_m4[`DATA_MASK_WIDTH-1:0];
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      write_data90_1      <= write_data90;
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      write_data_m90_1    <= write_data_m90;
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      write_data90_2      <= write_data90_1;
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      write_data_m90_2    <= write_data_m90_1;
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   end
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   always@ (negedge clk90) begin
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      write_data270      <= write_data4[(`DATA_WIDTH*2)-1 : `DATA_WIDTH];
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      write_data_m270    <= write_data_m4[(`DATA_MASK_WIDTH*2)-1:`DATA_MASK_WIDTH];
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      write_data270_1    <= write_data270;
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      write_data_m270_1  <= write_data_m270;
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      write_data270_2    <= write_data270_1;
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      write_data_m270_2  <= write_data_m270_1;
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   end
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   assign write_data_rising  = write_data270_2;
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   assign write_data_falling = write_data90_2;
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   assign data_mask_r = write_data_m270_2;
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   assign data_mask_f = write_data_m90_2;
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// write enable for data path
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   always@(posedge clk90) begin
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     write_en_P1 <= write_enable;
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   end
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   always@(negedge clk90) begin
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     write_en_val   <= write_en_P1;
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   end
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endmodule

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