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//*****************************************************************************

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//   ____  ____

//  /   /\/   /

// /___/  \  /   Vendor             : Xilinx

// \   \   \/    Version            : 3.6.1

//  \   \        Application        : MIG

//  /   /        Filename           : s3adsp_ddr2_fifo_1_wr_en_0.v

// /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:41 $

// \   \  /  \   Date Created       : Mon May 2 2005

//  \___\/\___\

// Device       : Spartan-3/3A/3A-DSP

// Design Name  : DDR2 SDRAM

// Purpose      : This module generate the write enable signal to the fifos, 

//                which are driven by posedge data strobe.

//*****************************************************************************

`timescale 1ns/100ps

module s3adsp_ddr2_fifo_1_wr_en_0

  (

   input  clk,

   input  rst_dqs_delay_n,

   input  reset,

   input  din,

   output dout

   );

   localparam TIE_HIGH = 1'b1;

   wire din_delay;

   wire dout0;

   wire rst_dqs_delay;

   assign rst_dqs_delay = ~rst_dqs_delay_n;

   assign dout0         = din & rst_dqs_delay_n;

   assign dout          = rst_dqs_delay | din_delay;

   FDCE delay_ff_1

     (

      .Q  (din_delay),

      .C  (clk),

      .CE (TIE_HIGH),

      .CLR  (reset),

      .D  (dout0)

      );

endmodule